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Posts Tagged ‘embedded’

Blog Review –Monday, October 24 2016

Monday, October 24th, 2016

The how, what and why of time-of-flight sensors; Conference season: ARM TechCon 2016 and IoT Solutions Congress; Save time on big data analysis; In praise of FPGAs; Is it time for augmented and virtual reality?

Drastically reducing big data analysis is music to a data scientist’s ears. Larry Hardesty reports on researchers at MIT (Massachusetts Institute of Technology) have presented an automated system that can reduce preparation and analysis from months to just hours.

Keeping an eye on the nation’s bank vaults, Robert Vamosi, Synopsys, looks at the what bank regulators are doing to ramp up cybersecurity.

If you can’t head to Barcelona, Spain this week for IoT Solutions World Congress (October 25-27), Jonathan Ballon, Intel, reveals what the company will unveil, including a keynote: IoT: From Hype to Reality, what 5G means, smart cities and a hackathon.

Tired of the buzz, and seeking enlightenment, Jeff Bier, Berkeley Design, delves into just what is augmented reality and virtual reality. He examines hardware and software, markets and what is needed for widespread adoption.

Closer to home, 2016 ARM TechCon, in Santa Clara, California (October 25 – 27), Phil Brumby, Mentor Graphics, offers a heads-up on its industrial robot demo, using Nucleus RTOS separated by ARM TrustZone, and the ECU (Engine Control Unit) demo in a Linux-hosted In-Vehicle Infotainment (IVI) system. There is also a technical session: Making Sure your UI makes the most of the ARM-based SoC (Thurs, 10.30am, Ballroom E)

The role of memory is reviewed by Paul McLellan, Cadence Design System, as he discusses MemCon keynotes by Hugh Durdan, VP of the IP Group and Steve Pwalowski, VP of Advanced Computing Solutions at Micron. There is comprehensive pricing strategy and a look at industry trends.

A teardown of the Apple iPhone 7, by Dick James, Chipworks, links STMicroelectronics’ time-of-flight sensors with the Starship Enterprise. The blog has a comprehensive answer to questions such as what are these sensors and why are they in phones.

If the IoT is flexible, Zibi Zalewski, Aldec, argues, then FPGAs can tailor solutions without major investments in an ASIC. He takes Xilinx’s Zynq-7000 All-Programmable SoC as a starting point and illustrates how it can boost performance for IoT gateways.

Elegantly illustrating how multiple Eclipse projects can be run on a single microcontroller with MicroEJ, Charlottem, ARM, runs through a connected washing machine that can communicate via Bluetooth, MQTT, Z-Wave and LWM2M.

Caroline Hayes, Senior Editor

Blog Review – Monday May 16, 2016

Monday, May 16th, 2016

Ramifications for Intel; Verification moves to ASIC; Connected cars; Deep learning is coming; NXP TFT preview

Examining the industry’s transition to 5G, Dr. Venkata Renduchintala, Intel, describes the revolution of connectivity and why the company is shifting its SoC focus and exploit its ecosystem.

Coming from another angle, Chris Ciufo, Intel Embedded, assess the impacts of the recently announced changes at Intel, including the five pillars designed to support the company: data center, memory, FPGAs, IoT and 5G, with his thoughts on what it has in its arsenal to achieve the new course.

As FPGA verification flows move closer to those of ASICs, Dr. Stanley Hyduke, Aldec, looks at why the company has extended its verification tools for digital ASIC design, including the steps involved.

Software in vehicles is a sensitive topic for some, since the VW emissions scandal, but Synopsys took the opportunity of the Future Connect Cars Conference in Santa Clara, to highlight its Software Integrity Platform. Robert Vamosi, Synopsys, reports on some of the presentations at the event on the automotive industry.

Identifying excessive blocking in sequential programming as evil, Miro Samek, ARM, write a spirited and interesting blog on real-time design strategy and the need to keep it flexible, from the earliest stages.

Santa Clara also hosted the Embedded Vision Summit, and Chris Longstaff, Imagination Technologies, writes about deep learning on mobile devices. He notes that Cadence Design Systems highlighted the increase in the number of sensors in devices today, and Google Brain’s Jeff Dean talked about the use of deep learning via GoogLeNet Inception architecture. The blog also includes examples of Convolutional Neural Networks (CNN) and how PowerVR mobile GPUs can process the complex algorithms.

This week, NXP FTF (Freescale Technology Forum), in Austin, Texas, is previewed by Ricardo Anguiano, Mentor Graphics. He looks at a demo from the company, where a simultaneous debug of a patient monitoring system runs Nucleus RTOS on the ARM Cortex-M4. He hints at what attendees can see using Sourcery CodeBench with ARM processors and a link to heterogeneous solutions from the company.

Caroline Hayes, Senior Editor

Smart Bluetooth, Sensors and Hackers Showcased at CES 2015

Wednesday, January 14th, 2015

Internet of Things (IoT) devices ranged from Bluetooth gateways and smart sensors to intensive cloud-based data processors and hackathons – all powered by ARM.

By John Blyler, Editorial Director

Connectivity continues to be a major theme at the International Consumer Electronics Show (CES). The only difference each year is the way in which the connectivity is express in products. For example, this year’s (2015) event showcased an increase in gateway networking devices that permitted Bluetooth Low Energy-equipped gadgets to connect to a WiFi router or other interfaces with the outside world.

According to a recent IHS report, the global market for low-power, Bluetooth Smart integrated circuits (IC) will see shipments rise nearly tenfold over the next 5 years. This is good news for very low power wireless semiconductor intellectual property (IP) and device manufacturers in the wearable and connected markets. One example out of many is Atmel’s BTLC1000 chip, which the company claims will help improve battery life by over 30% of current devices. The chip architecture is based on a ARM® Cortex®-M0 processor.

Bluetooth Smart is the intelligent, low-power version of traditional Bluetooth wireless technology that works with existing smartphone and tablet applications. The technology brings smart connectivity to every day devices such as toothbrushes, heart-rate monitors, fitness devices and more. (See, Wearable Technologies Meet Bluetooth Low Energy)

For the IoT to be useful, sensor data at the edge of the connectivity node must be communicated to the cloud for high performance processing of all the IoT data. This year’s CES showcased a number of multicore 64-bit devices like NVIDIA ARM-based Tegra X1. Another example of a high-end computing system is Samsung’s Exynos 5422 processor that is based upon ARM’s big.LITTLE™ technology and contains four Cortex-A15 cores and four Cortex-A7 cores. These types of products can run Android and 4K video displays on a 28nm process node.

Team mbed

Many embedded software developers enjoy the challenge of creating something new. Today, it is fashionable to call these people hackers, in part because they exhibit the prerequisite mindset, namely, “one who programs enthusiastically…”  – from the Hacker’s Jargon File, circa 1988.

Special events called hackathons have been created for these enthusiastic programmers to practice and demonstrate their skills. For example, back in August of 2014, ARM provided a group of hackers know as Team mbed™ with hardware and software development platforms for the AT&T Hackathon at Super Mobility Week. Last week, Team mbed returned to participate in the ATT Hackathon at the CES 2015. The team consisted of Internet of Things (IoT) industry participants from Freescale, Multi-Tech, Nordic Semiconductor, STMicroelectronics, u-blox and ARM. The team was supplied with a number of cool resources including ARM mbed-enabled development boards, connectivity modules, and a variety of different actuators and sensors. These resources combined with available guidance and inspiration enabled the developers to bring their own ideas to reality.

Following the show’s IoT theme, these software developer were given a ‘smorgasbord’ of sensors and actuators to go along with a variety of hardware platforms and I/O connectivity subsystems including Bluetooth®, cellular, Ethernet, and Wi-Fi®.  Recent projects are built around this IoT platform are highlighted at haster.io/mbed (see Figure 1).

Figure 1: Krisztian Flautner, GM of IoTBU at ARM, discusses this new mbed offering that sets out to simplify and speed up the creation and deployment of Internet of Things (IoT) products

Next to connectivity, sensors are the defining component of any IoT technology. Maybe that is why sensor companies have been a growing presence on the CES show floor. This year, sensor-related vendors accounted for over 10% of total exhibitors. Many new IoT sensor technology is implemented using tiny MEMS physical structures. At CES, a relatively new company known as Invensense announced a Sensor System on Chip that combines an ARM Cortex-M0 processor with 2 motion co-processors (see Figure 2). This combination enables a 6-axis motion measurement all in a 3mm x 3mm x 1mm package. To complete the package, this device has its own RTOS that is compatible with Android Lollipop.

Figure 2: InverSense chip with sensors.

Such sensor systems on chip would make a fine addition for the resources available for Team mbed at their next hackathon.

Research Roundup Dec 31 2013

Tuesday, December 31st, 2013

As we say goodbye to 2013, the work of research institutes and teams at universities around the world bring us an insight into what 2014 may hold. By Caroline Hayes.

Graphene research reveals magnetic field behavior
A tale with a twist emerges from MIT and is reported in Nature, reporting another property of the material graphene.

Placed under a powerful magnetic field, at low temperatures, A.F. Young, J.D. Sanchez-Yamagishi and B. Hunt and their team found that the graphene’s behavior changed as electrons moved around the conducting helical edge. Depending on whether the movement was clockwise or counter-clockwise. The researchers found that when the magnetic field was varied, edge states could be turned on or off. The properties of the helical edge states can be modulated, by balancing the applied field against an intrinsic anti-ferromagnetic instability, which spontaneously breaks the spin-rotation symmetry.

Mass production technique prepares way for semiconductor-ready graphene

image from UNIST

More graphene research, this time into an efficient method for mass production of BCN-graphene (boron/nitrogen co-doped graphene nanoplatelets). The team of UNIST (Ulsan National Institute of Science and Technology) led by Professor Jong-Beom Baek, have been able to add boron into the framework to enable semiconductor applications.

The research team used nitrogen, which is smaller than carbon and boron, and paired two nitrogen atoms and two boron atoms to compensate the atomic size mismatch and allow it to be introduced into the graphitic network. The team reports that the resultant BCN-graphene generates a band-gap for FETs (field effect transistors).

First author Ph.D. candidate Sun-Min Jung believes “ this work is one of the biggest advancements in considering viability of a simple synthetic approach,” and Professor Baek explains its implications: “Now, the remaining challenge is fine-tuning the band-gap to improve the on/off current ratio for real device applications”.

Researchers are Professors Joon Hak Oh, Noejung Park, HuYoung Jeong and six graduate students.

Superconductors have to live up to their name
Two studies by international teams are challenging views of superconductivity. First, a group from Helmholtz-Zentrum, Berlin and Max Planck, based in Stuttgart, screened two materials, Bi2201 and Bi2212, which contain the characteristic components of copper oxide and bismuth. Resonant X-ray scattering using BESSY, the Helmholtz synchrotron, revealed the charge distribution on the inside of the materials.

Researchers at Princeton University scanned the samples with a raster tunnel microscope that records the charge distribution at the surface. Physicists at the University of British Columbia also examined the Bi2201 sample using angle-resolved photoemission spectroscopy, revealing more details of the electronic structure of the material.

China’s telematics markets is set to change course
The shift from telematics to consumer-focused, electronics based automotive systems in the Chinese market will increase the use of wireless devices, such as smartphones, reports the Infotainment Market Overview from IHS.

Embedded telematics systems generated 1.5million units sold in 2013, rising to 4.3million by the end of 2020. However consumer electronics and hybrid alternatives are projected to surpass this with approximately 4.6million units sold during that year.

CE-device-based services are cheaper as they are able to use mobile devices to establish a two-way data connection for services. Hybrid systems feature both an embedded transmission control unit and the option to use a connected consumer electronics device to provide a data connection.

The introduction of Chevrolet’s Epica model in April 2011 started the era of CE-device telematics in China, the world’s largest car market. Since then, nine brands have adopted consumer electronics-device telematics. The profile of the customer is one that buys more high-end vehicles, and uses more wireless devices, to increase the market, and accounting for the triple digital annual expansion over the next three years in consumer electronics and hybrid telematics.

Legacy vs New IP – Trends in IOT JPG and Drone Applications

Thursday, February 23rd, 2017
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Has The Time Come for SOC Embedded FPGAs?

Tuesday, October 25th, 2016
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Clarifing Embedded IOT Connectivity Confusion

Tuesday, June 28th, 2016
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Security Challenges in a Connected World

Thursday, February 20th, 2014

By Caroline Hayes, Senior Editor

One of the joys of today’s electronics devices is that they are connected – endlessly connected. Anyone can tweet, engage in social media, share data, video, audio and graphic files wherever they happen to be. However, with the freedom of connectivity, comes the vulnerability of security breaches.

The access to applications and interfaces can bring us closer together – but it can also leave devices, and their users’ data, vulnerable to exploitation, attack and theft.

The business risk
The rise of connected devices is exposing networks to security breaches and cyber-attacks. In industrial use, automation networks, for example, the wireless network connections brings a serious threat, says IHS, of attack from malware. It recalls the Stuxnet computer worm that hit industrial control systems in Iran. It was designed to subvert and engage in the surveillance of supervisory control and data acquisition systems made by German manufacturer, Siemens.

As well as factory automation, many businesses, large and small, employ staff that bring their own devices to the workplace. The risk is that tablets and smartphones may lack sufficient security levels and expose a network, allowing hackers to access data or to spread malware through an international network.

The embedded revolution
Felix Baum, Senior Product Manager, Runtime Solutions, Mentor Embedded Software Division, agrees that unfettered connectivity is a double-edged sword. “We find ourselves in the midst of an embedded market undergoing revolutionary change. Unlike devices of yesterday that had limited access to the Internet and were mostly purpose- built, today’s embedded devices, with more powerful processing power and numerous built-in connectivity options, run on Linux and/or other modern operating systems side-by-side, which allows these devices to extend features and functionality via upgrades by device manufacturers or by downloaded third party applications. These embedded devices are capable of handling massive amounts of data of increasing value such as personal health records and banking/credit credentials putting them in a position of high risk to be exploited,” he warns.

Most attacks on embedded devices exploit vulnerabilities in software, for example with Linux and another operating system side-by-side; weaknesses in hardware interfacing, multi-tasking and timing or through Internet access via the connectivity options, rather than general data processing or network security issues.

Addressing these issues, Baum expands on what Mentor Graphics offers in the way of embedded protection for today’s and the next-generation of embedded, mobile devices. The company’s portfolio spans general-purpose operating systems, such as Mentor Embedded Linux, to the RTOS (Real-Time Operating System) Nucleus, an OpenSSL-based solution, with security facilities, such as encryption protocols and a set of algorithms for security. It supports cryptographic APIs (Application Programming Interfaces) and AES (Advanced Encryption Standard) 128 and AES 256, DES (Data Encryption Standard), 3DES (Triple DES), Blowfish and Cast-128 security protocols.

“These operating systems undergo network penetration testing, offer customers the ability to run kernel and application code in separate isolated areas and offer encryption capabilities. When a design relies on the multi-core ARM devices, customers can utilize the Mentor Embedded Hypervisor for additional separation and isolation capabilities to enhance design robustness. The Hypervisor also fully supports ARM TrustZone technology allowing designers to protect sensitive data and code by placing them into Secure World”.

Prevention is better than cure
Rob Coombs, Security Systems Marketing Director, ARM (right), considers a little forethought will go a long way. “Security engineering is a specialized topic where developers need to think about how a malicious adversary would attack the system, not just “does it work”. Typically a specialized secure Trusted OS is needed to provide secure services that live in hardware isolation to the main code. In ARM designs the Trusted OS normally exists in the Secure World that TrustZone architecture provides,” he says.

For Coombs, the process begins with consideration for where an attack may come from. “System designers benefit from thinking from the start how they are going to protect the system from software attack. Security needs to be designed into the hardware with roots of trust and secure boot and then build outwards from there”.

Consumers and business people alike will not give up their connected worlds, so what can be done to design safe, secure embedded devices?

Both Baum and Coombs agree that a holistic approach is necessary. For Baum, this includes hardware, software and the development process “to develop robust and reliable devices. Only by doing so, will they be able to ensure that the chain of trust is not broken,” he says. When devices are booted into a trusted state and application code has been authenticated, they provide some security, he says.

The same holistic approach is advised by Coombs. He points out that the problem with mobile devices is that their very nature means that they are made up of elements that need security yet are accessed by other parties. For example, a cell phone’s SIM (Subscriber Identity Module) will be provided by the OEM, which may need to access the operating system and other secure elements for holding keys and performing system integrity checks. Making the secure elements tamperproof resists physical attacks.

“ARM has a four compartment model of security providing a hierarchy of trust. System designers can decide which assets are best protected in which compartment e.g. hypervisor or TrustZone based TEE (Trusted Execution Environment)”. Coombs describes the latter as an important component in delivering secure services and applications.

Isolation policy
The first compartment is Normal World –or user/system mode (as opposed to the Trusted World). This is where processes or application are isolated from each other by the operating system and the MMU (Memory Management Unit). Each process has its own addressable memory, a set of capabilities and permissions, administered by the operating system kernel, which executes with system-level privilege.

Another weapon in the security armor is Hypervisor Mode, where multiple instances of the same or different operating systems execute on the same processor as a virtual machine. Each virtual machine can be isolated and virtualized through the use of a system MMU, to virtualize other bus masters. By separating them, resources and assets in each virtual machine can be protected from the others.

In the Trusted World secure state, the company’s TrustZone security extensions allow the system to be physically partitioned into secure and non-secure components. Again, this serves to isolate assets and ensures that software cannot directly access secure memory or secure peripherals.

Finally, the SecurCore processors enable physically separate, tamper proof ICs, delivering secure processing and storage that is protected against physical attack or loss through improperly secured devices, and also protection from software attack.

Given all these elements, how can designers balance speed and accuracy in system design? Coombs again points to TrustZone, by which SoC designers can be guided to select the security hardware features needed to address different markets. “ARM Trusted Firmware provides an open source base of critical low level code that the industry can align with. Other security code can then be ported on top”. The benefits of this are reduced time to market and reduced fragmentation, says Coombs, as well as easier porting of Secure World software and the ability to support new features in the latest 64bit platforms.

The next stage is to look to the future. I asked what can be done to future-proof designs for authentication. “ARM has recently joined the FIDO (Fast Identity Online) Alliance and views it is a good place to create a verification framework that works for website owners and device manufacturers,” says Coombs. “A TrustZone based TEE can support secure peripherals (such as a touchscreen) and this can be integrated to create a strong authentication of person and device.

“For Crypto and key stores this is ideally managed from the TrustZone-based TEE to provide hardware isolation from malicious code. If the TEE provider offers Over The Air provisioning of Secure World code then updates can be delivered to future-proof the design”.

Deeper Dive – IPextreme Blows Hot for ColdFire

Thursday, October 24th, 2013

By Caroline Hayes

There is a shift occurring in the semiconductor market, driven by the consumer space, believes Warren Savage, president and CEO, IPextreme. The IP provider has added the new ColdFire V1 platform to its portfolio. Savage describes the company as product-oriented, whose soft IP can be used with each, successive generation and can serve the ASSP (application specific standard product) or FPGA (field programmable gate array) markets.
To if to illustrate this versatility, this latest configurable platform is available to license now. It consists of a V1 core and pre-integrated subsystem of configurable peripherals. The peripherals can be configured in the platform or out of it and configuration is automatically handled by the company’s IP management platform, Xena.
“The semiconductor market is changing to diversification and specialization” Warren told ChipDesign, explaining the configurable options for the CPU (central processing unit) and the subsystem options. The ColdFire V1 platform has an enhanced MAC (multiple accumulate) engine, an industry-standard AMBA 3 AHB-Lite system bus interface for fast system integration, an improved hardware divider and cryptographic acceleration unit, all of which are optional.
The debug unit is also optional and has a single-wire debug interface and 64-entry trace buffer. HDL parameters can be adjusted so that only the hardware needed for a final implementation needs to be included after tradeoffs have been explored.
Configurability is conducted via the web in a Xena account. Xena was introduced two years ago and manages IP, royalties, export control, contracts, suppliers, device, bugs, tracking, deliverables, access control and support, under one database. There is also a helpdesk, contract terms and supplier management to assist SoC (system on chip) companies building embedded devices.
Developed for the embedded market, the platform implements commonly-required functions, such as interrupt control, DMA (direct memory access), GPIO (general purpose input/output) timers and serial interfaces. An AHB (advanced high performance bus) crossbar switch provides the system interconnect ad supports simultaneous AHB transfers between multiple masters and slaves, including those that are externally connected.
Among the on board peripherals there are several optional components. Savage identifies the industry’s move toward platform based design “as the norm,” explaining that it allows “not only hardware reuse but also to allow software reuse across multiple product lines to get embedded products to market faster”.

An optional RAM controller, supports tightly-coupled RAM random access memory) with a single-cycle access and is available up to 64kbyte. Other options are the ROM (read only memory) controller which can be up to 1024kbyte in size; an optional minibus controller which connector one or two memories or devices, which can be on- or off-chip. This allows for characteristics for each device, for example wait states, address set-up/ hold, data width and the choice of multiplexed or non-multiplexed mode. Also option is the DMA controller, the queued SPI (serial peripheral interface) module, which allows users to program a queue of up to 16 SPI transfers apt o nd to program baud rate before and after transfer delays, clock phase and polarity. Other options are the I2C interface module, supporting up to 3.4Mbit/s baud rates; up to three UARTs (universal asynchronous receiver/transmitters) and up to four DMA timer modules. Standard peripherals are the interrupt controller, which supports up to 30 peripheral interrupt requests and seven interrupt requests, and also supports low power mode wake-up. Also standard is the platform control, including a software watchdog timer, reset status, low-power control and core fault status registers.

Software controlled shutdown of specific clocks can support low power modes, by independent shutdown of peripheral clocks or shutdown of the CPU clock.

Debug support is available with a single-wire background debug mode interface, real-time debug and on-chip, 64-entry trace buffer.

www.ip-extreme.com

Software Programmers Face Multicore Challenges

Thursday, February 19th, 2009

By John Blyler
As multicore technology moves into the embedded systems, software developers face tool shortcomings, legacy code preservation and scalability challenges.

Max Domeika , an embedded tools consultant in the Software and Services Group at Intel, explained that one of the biggest challenges facing embedded system software developers is the growing number and types of multicore processors. “There are so many different cores with varying capabilities even within a given architectural family of processors, not to mention virtual enhancements like hyperthreading techniques, which enable a single core processor to look like two cores to the operating system.”

Hyperthreading is based on “out of order” scheduling of a processor in which the incoming code instructions are identified early enough so they can be executed in parallel. From a programmer’s viewpoint, it looks like you have two different processors, even though you are sharing many of the same resources, such as execution units and memory caches. It gives the programmer more options, but it is not the same as having two distinct cores as in a multicore environment.

Why are embedded designers upgrading to multicore technology? Many have found that the use of multiple processor cores reduces system latency or delay. “If you have latency sensitive applications – even something as simple as a user interface – you can spawn threads with reduced latency,” notes Domeika. Threads, or a collection of related code segments, are at the heart of multithreading paradigm, which allows programmers to design software applications whose threads can be executed concurrently.

Scalability is one of the biggest obstacles faced by embedded developers who want to or must use multicore systems. “You may ship with a two-core architecture, but the next revision of the product my have four cores. This means that you want to create your software in such a manner that it scales with as little effort as possible,” Domeika says. Many developers have found out the hard way that a system hard-coded for a two-core architecture must be completely rewritten to run on a four-core system. This translates to additional product cost and a longer time to market.

To accommodate the next product revision, a programmer has to look at all of their routines and figure out how to re-partition the executions among an increased number of processors.

At the heart of the scalability question is the balance between different types of available parallelism.  Besides multithreading, another means of providing for parallel execution is through the use of Single Instruction – Multiple Data processing.  Intel’s implementation of SIMD instruction is embodied by its Intel SSE instructions.  Another example of SIMD instruction set processing is AltiVec, used by the PowerPC community – namely IBM and Freescale.

“In many ways, it is still left up to the programmer to decide how best to balance the amount and type of parallelism to be used. Programmers must think about what happens at the tread level for a shared memory machine, the process level, and also the SIMD vector level. This is a very hard problem,” notes Domeika.
Scalability and parallel implementation issues help to reinforce the need for better development tools and environments. One way to address these needs is through standards and automation. In the multicore space, several companies – including Intel – have worked on a standard called OpenMP which enables concurrency on shared memory machines. One challenge with using OpenMP in the past was balancing parallelization operating on multiple cores and parallelization available through use of SIMD instruction sets.To address this challenge, the Intel Compiler recently added support for automatic vectorization inside of OpenMP pragmas, which are used for compiler control. Automatic vectorization is a technique that transforms a series of sequential operations into operation performed in parallel. Hence, automatic vectorization analyzes the code to take advantage of SIMD instructions, while working within the OpenMP environment to balance different forms of parallelism.

All of these advances are great. However, for many embedded software developers, the main issue is how to preserve their legacy embedded C code while still upgrading to multicore technology. “Most customers that I talk with are interested in new technologies like multicore but are more interested in preserving their business, which means their 10 million lines of legacy C code,” explains Domeika. “That is why I’m one of the co-chairs—along with David Stewart, CEO at CriticalBlue —of the Multicore Programming Practices (MPP) Group. The charter of the group is to collect the best known methods of programming practices using today’s technology. For embedded developers, that means C/C++ and libraries, mainly POSIX threads.

Such cooperation among embedded software developers will be critical for the continued growth of multicore technology. As in the desktop world, embedded software is the last – but certainly not the least – component necessary for a successful system.

View the video interview with Max.