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Blog Review – Monday, November 6, 2017

Monday, November 6th, 2017

This week, we find that ANSYS gets hyper about Hyperloop development, Xilinx puts its mind to networks, Maxim supports factory automation and NXP, Mentor and ON Semiconductor explain why and how a product can be used.

A positively upbeat tone is set by Maxim Integrated’s Jeff DeAngelis, as he looks at how Industry 4.0 and automation is bringing back jobs. He looks at how being competitive through automation is leading to reshoring activity.

The now infamous ‘Jeep hack’ is the starting point for Timo van Roermund, the security architect at NXP considers what safeguards are needed and how the car domain needs to be re-thought for security on the roads. As well as citing several NXP products, there are also some useful links.

There’s a new look to the Mentor Graphics blogs and Michael Nopp uses it to good effect to take us through the company’s PADS Professional. His use of clear, colourful graphics adds to a simply told design guide.

Who isn’t super-excited about Hyperloop technology at the moment? Adora Anound Tadros, HyperXite guests on the ANSYS site to tell us how the team from University of California, Irvine, used simulation tools for its entry in the SpaceX Hyperloop Pod competition. The team is gaining momentum and was in the top six of this year’ competition and is planning to compete again in 2018 – with a self-propulsion pod design.

Smile, you’re on camera, says an image-conscious Jason Liu, ON Semiconductor. He looks at the changing roles of cameras in our lives and introduces the company’s digital image sensor.

Another current favourite topic is neural networks. Steve Leibson proudly relates how a team at the University of Birmingham in the UK has implemented a deep recurrent neural network on a Xilinx Zynq Z-7020 SoC using the Python programming language.

Caroline Hayes, Senior Editor

Blog Review – Tuesday, August 29, 2017

Monday, August 28th, 2017

This week, we find Trust issues for autonomous cars; Something old to wear; How to get design teams to talk; Discover Cadence adds ARM to its library; and Unravelling RTOS with Mentor

Autonomous driving – it’s all a matter of trust, says Jack Weast, Intel. Fearing the robot at the wheel can be overcome, he maintains, reviewing the findings of a Trust Interaction Study. His blog covers human-machine judgement, personal space and lack of assistance, awareness and information balance and giving up control.

Proving there is nothing new under the sun, Maeva Mandard, Dassault Systèmes, considers wearable technology and the earliest example of a wearable calculator. She outlines how an integrated view, mechanics, electronics and embedded software will allow design and test teams to work together.

Adopting a novel approach –i.e. different teams communicating – Lucid Motors designed a luxury electric vehicle by locking different engineering teams in a room. Another significant factor, relates Sandeep Sovani, ANSYS, is the use of multiphysics simulation on the Workbench platform for simultaneous optimisation.

Keeping up with multi-core, SoCs, Steve Brown, Cadence explains how the company’s library of portable stimulus is designed for specific functional sub-systems that are common in complex SoCs. The first, for multi-core ARMv8 and ARMv8.2 architectures, are introduced, with a link to Nick Heaton, ARM’s blog on the library. More libraries are promised for later this year.

Some economic policy advice becomes an analogy for Tom De Schutter, Synopsys, for engineers moving from single FPGA prototypes to multiple FPGA ones. How to make the leap painlessly is an interesting read addressing a topic that many will recognize.

A very informative piece by Colin Walls, Mentor Graphics, continues his RTOS focus, with a blog about data transfer. He provides some clear graphics to show the task of data transfer and opens a window on this procedure.

Blog Review – Monday, June 26, 2017

Monday, June 26th, 2017

This week, hot on the heels of DAC, a review of the Austin event; Intel administers a dose of precision medicine; Challenges for drivers; How to choose between a GPU or FPGA and a blockchain reaction for the IoT

DAC 2017 took place in Austin, Texas, and Paul MeLellan, Cadence Design Systems, was there and has collated a wide-ranging report, with day-by-day news, including bats and bagpipes from the 54 th incarnation of the event.

Writing from a very personal viewpoint, Bryce Olson, Intel, advocates precision medicine, and looks at Intel’s scalable reference architecture to speed up the research and answers in medical care.

Vehicle safety is critical, and Stephen Pateras, Mentor Graphics, looks at self-test and monitoring in autonomous cars, using the Tessent MissionMode architecture. He explains in a clear, detailed manner, the IC test capabilities and simulation for self-driving cars.

Still with vehicle design, Robert Vamosi, Synopsys, flags up the security hazards around the connected car as sensors proliferate and hackers ramp up their assaults. He advocates software security and the communication protection afforded by the IEEE 802.11p protocol.

A handy white paper is brought to our attention by Steve Leibson, Xilinx, for those deciding whether a GPU is better than an FPGA in cloud computing, machine leaning, video and image processing applications.

I learned a couple of things from Christine Young, Maxim Integrated this week. One is that there is a job title of ‘chief IoTologist’, the other was to put the term ‘blockchain’ into context for the IoT. She reports from the IoT World Conference about how blockchain, using advanced cryptography, provides a “tamper-proof distributed record of transactions” and how the IoT Alliance is occupied in developing a shared blockchain protocol as a common identifier to secure IoT products.

Starstruck John Blyler, looks at the reality behind the stardust and conducts an interview with Dr Clifford Johnson, physicist at University of Southern California and script adviser for the National Geographic Channel’s TV program, Genius, about Albert Einstein.

Cadence Launches New Verification Solutions

Tuesday, March 14th, 2017

Gabe Moretti, Senior Editor

During this year’s DVCon U.S. Cadence introduced two new verification solutions: the Xcelium Parallel Simulator and the Protium S1 FPGA-Based Prototyping Platform, which incorporates innovative implementation algorithms to boost engineering productivity.

Xcelium Parallel Simulator

.The new simulation engine is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, internet of things (IoT) and automotive projects.

The Xcelium simulator offers the following benefits aimed at accelerating system development:

  • Multi-core simulation improves runtime while also reducing project schedules: The third generation Xcelium simulator is built on the technology acquired from Rocketick. It speeds runtime by an average of 3X for register-transfer level (RTL) design simulation, 5X for gate-level simulation and 10X for parallel design for test (DFT) simulation, potentially saving weeks to months on project schedules.
  • Broad applicability: The simulator supports modern design styles and IEEE standards, enabling engineers to realize performance gains without recoding.
  • Easy to use: The simulator’s compilation and elaboration flow assigns the design and verification testbench code to the ideal engines and automatically selects the optimal number of cores for fast execution speed.
  • Incorporates several new patent-pending technologies to improve productivity: New features that speed overall SoC verification time include SystemVerilog testbench coverage for faster verification closure and parallel multi-core build.

“Verification is often the primary cost and schedule challenge associated with getting new, high-quality products to market,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Xcelium simulator combined with JasperGold Apps, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform offer customers the strongest verification suite on the market”

The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Protium S1

The Protium S1 platform provides front-end congruency with the Cadence Palladium Z1 Enterprise Emulation Platform. BY using Xilinx Virtex UltraScale FPGA technology, the new Cadence platform features 6X higher design capacity and an average 2X performance improvement over the previous generation platform. The Protium S1 platform has already been deployed by early adopters in the networking, consumer and storage markets.

Protium S1 is fully compatible with the Palladium Z1 emulator

To increase designer productivity, the Protium S1 platform offers the following benefits:

  • Ultra-fast prototype bring-up: The platform’s advanced memory modeling and implementation capabilities allow designers to reduce prototype bring-up from months to days, thus enabling them to start firmware development much earlier.
  • Ease of use and adoption: The platform shares a common compile flow with the Palladium Z1 platform, which enables up to 80 percent re-use of the existing verification environment and provides front-end congruency between the two platforms.
  • Innovative software debug capabilities: The platform offers firmware and software productivity-enhancing features including memory backdoor access, waveforms across partitions, force and release, and runtime clock control.

“The rising need for early software development with reduced overall project schedules has been the key driver for the delivery of more advanced emulation and FPGA-based prototyping platforms,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Protium S1 platform offers software development teams the required hardware and software components, a fully integrated implementation flow with fast bring-up and advanced debug capabilities so they can deliver the most compelling end products, months earlier.”

The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Blog Review – Monday May 16, 2016

Monday, May 16th, 2016

Ramifications for Intel; Verification moves to ASIC; Connected cars; Deep learning is coming; NXP TFT preview

Examining the industry’s transition to 5G, Dr. Venkata Renduchintala, Intel, describes the revolution of connectivity and why the company is shifting its SoC focus and exploit its ecosystem.

Coming from another angle, Chris Ciufo, Intel Embedded, assess the impacts of the recently announced changes at Intel, including the five pillars designed to support the company: data center, memory, FPGAs, IoT and 5G, with his thoughts on what it has in its arsenal to achieve the new course.

As FPGA verification flows move closer to those of ASICs, Dr. Stanley Hyduke, Aldec, looks at why the company has extended its verification tools for digital ASIC design, including the steps involved.

Software in vehicles is a sensitive topic for some, since the VW emissions scandal, but Synopsys took the opportunity of the Future Connect Cars Conference in Santa Clara, to highlight its Software Integrity Platform. Robert Vamosi, Synopsys, reports on some of the presentations at the event on the automotive industry.

Identifying excessive blocking in sequential programming as evil, Miro Samek, ARM, write a spirited and interesting blog on real-time design strategy and the need to keep it flexible, from the earliest stages.

Santa Clara also hosted the Embedded Vision Summit, and Chris Longstaff, Imagination Technologies, writes about deep learning on mobile devices. He notes that Cadence Design Systems highlighted the increase in the number of sensors in devices today, and Google Brain’s Jeff Dean talked about the use of deep learning via GoogLeNet Inception architecture. The blog also includes examples of Convolutional Neural Networks (CNN) and how PowerVR mobile GPUs can process the complex algorithms.

This week, NXP FTF (Freescale Technology Forum), in Austin, Texas, is previewed by Ricardo Anguiano, Mentor Graphics. He looks at a demo from the company, where a simultaneous debug of a patient monitoring system runs Nucleus RTOS on the ARM Cortex-M4. He hints at what attendees can see using Sourcery CodeBench with ARM processors and a link to heterogeneous solutions from the company.

Caroline Hayes, Senior Editor

Blog Review – Monday, February 15, 2016

Monday, February 15th, 2016

Research converts contact lens to computer screens; What to see at Embedded World 2016; Remembering Professor Marvin Minsky; How fast is fast and will the IoT protect us?

The possibilities for wearable technology, where a polymer film coating can turn a contact lens into a computer screen are covered by Andrew Spence Nanontechnology University of South Australia’s Future Industries Institute. The lens can be used as a sensor to measure blood glucose levels to a pair of glasses acting as a computer screen.

If you are preparing your Embedded World 2016, Nuremberg, schedule, Philippe Bressy, ARM offers an overview of what will be at his favourite event. He covers the company’s offerings for IoT and connectivity, single board computing, software productivity, automotive and from ARM’s partners to be seen on the ARM booth (Hall 5, stand 338), as well as some of the technical conference’s sessions and classes.

Other temptations can be found at the Xilinx booth at Embedded World (Hall 1, stand 205). Steve Leibson, Xilinx explains how visitors can win a Digilent ARTY Dev Kit based on an Artix-7 A35T -1LI FPGA, with Xilinx Vivado HLx Design Edition.

Showing more of what can be done with the mbed IoT Device Platform, Liam Dillon, ARM, writes about the reference system for SoC design for IoT endpoints, and its latest proof-of-concept platform, Beetle.

How fast is fast, muses Richard Mitchell, Ansys. He focuses on the Ansys 17.0 and its increased speeds for structural analysis simulations and flags up a webinar about Ansys Mechanical using HPC on March 3.

If the IoT is going to be omnipresent, proposes Valerie C, Dassault, can we be sure that it can protect us and asks, what lies ahead.

A pioneer of artificial intelligence, Professor Marvin Minsky as died at the age of 88. Rambus fellow, Dr David G Stork, remembers the man, his career and his legacy on this field of technology.

I do enjoy Whiteboard Wednesdays, and Corrie Callenback, Cadence, has picked a great topic for this one – Sachin Dhingra’s look at automotive Ethernet.

Another thing I particularly enjoy is a party, and Hélène Thibiéroz, Synopsys reminds us that it is 35 years since HSPICE was introduced. (Note to other party-goers: fireworks to celebrate are nice, but cake is better!)

Caroline Hayes, European Editor

Blog Review – Monday, January 11, 2016

Monday, January 11th, 2016

In this week’s review, as one blog has predictions for what 2016 holds, another reviews 2015. Others cover an autonomous flight drone; a taster of DesignCon 2016 and a bionic leg development.

Insisting it’s not black magic or fortune telling but a retelling of notes from past press announcements, Dick James, Chipworks, thinks 2016 will be a year of mixed fortunes, with a low profile for leading edge processes and plenty of activity in memory and sensors as the sectors reap the rewards of developments being realized in the marketplace.

Looking back on 2015, Tom De Schutter, Synopsys, is convinced that the march of software continues and world domination is but a clock cycle away. His questions prompted some interesting feedback on challenges, benefits and working lives.

Looking ahead to autonomous drone flight, Steve Leibson, Xilinx, reports on the the beta release of Aerotenna’s OCPoC (Octagonal Pilot on Chip) ready-to-fly drone-control, based on a Zynq Z-7010 All Programmable SoC with integrated IMU (inertial measurement unit) sensors and GPS receiver.

Bigger isn’t always better, explains Doug Perry, Doulos, in a guest blog for Aldec. As well as outlining the issues facing those verifying larger FPGAs, he provides a comprehensive, and helpful, checklist to tackle this increasingly frequent problem, while throwing in a plug for two webinars on the subject.

Some people have barely unpacked from CES, and ANSYS is already preparing for DesignCon 2016. Margaret Schmitt previews the company’s plan for ‘designing without borders’ with previews of what, and who, can be seen there.

A fascinating case study is related by Karen Schulz, Gumstix, on the ARM Community blog site. The Rehabilitation Institute of Chicago has (RIC) has developed the first neural-controlled bionic leg, without using no nerve redirection surgery or implanted sensors. The revolution is powered by the Gumstix Overo Computer-on-Module.

Showing empathy for engineers struggling with timing closure, Joe Hupcey III, Mentor Graphics, has some sound advice and diagnoses CDC problems. It’s not as serious as it sounds, CDC, or clock domain crossing, can be addressed with IEEE 1801 low power standard. Just what the doctor ordered.

Caroline Hayes, Senior Editor

Blog Review – Monday, October 26, 2015

Monday, October 26th, 2015

Counting gates til the chickens come home to roost; Bio lab on a desk; Twin city goes digital; Back to the Future Day; Graphics SoC playground; Wearables get graphic

Something is troubling Michael Posner, Synopsys, when is a gate not a gate? He discusses the FPGA capacity of Xilinx’s UltraScale FPGAs and tries to find the answer. He also describes his Heath Robinson style light controlled chicken feeder he has installed in the chicken coop.

A desktop biolab sounds like something in a teenage boy’s room, but Amino is the ‘brainchild’ relates Atmel of Julie Legault. The Arduino-based bio-engineering system enables anyone to grow and take care of living cells. The mini lab allows the user to genetically transform an organism’s DNA through guided interactions. The Arduino-driven hardware monitors the resulting synthetic organism which needs to be fed nd kept warm. For those old enough to remember the Tamagotchi craze – it just moved up a gear.

3D computer models of buildings and cities take on a new role, demonstrated by Dassault Systèmes, whose 3DEXPERIENCity continuously generates the city as a digital twin city. Ingeborg Rocker explains how the IoT is used by the multi-dimensional data model which integrates population density, traffic density, weather, energy supply and recycling volumes data in real time to support city planners.

Recent acquisitions in the industry are analysed by Paul McLellan, Cadence Design Systems. Beginning with the acquisition of Carbon Design Systems by ARM, McLellan puts the deal in a market and engineering context. He moves on to the acquisition by Lam Research of KLA-Tencor and Western Digital which has bought SanDisk.

Putting the AMD R-Series through its paces, Christopher Hallinan, Mentor Graphics, delights in the versatility of the SoC, as discovered with Mentor Embedded Linux. He gives real-life examples of algorithms and how the visuals apply to industrial and scientific applications.

Celebrating a noteworthy date Back to the Future Day – October 21 2015 – Tobias Wilson-Bates, Georgia Tech, looks at how time travel has been portrayed in fiction. It gets philosophical: “One way to think about future speculations is to imagine that there are all these failed futures that co-exist with a present reality” but Marty would approve.

The acceptance of Mali-470 GPU to the wearables camp is complete. Dan Wilson, ARM, explains how the GPU is exploiting its OpenGL ES 2.0 graphics standard and power consumption for wearable and IoT applications.

Caroline Hayes, Senior Editor

Focus on France in Nuremberg

Friday, March 27th, 2015

Although the venue was the German city of Nuremberg, there was a distinctive coterie of French companies at Embedded World, writes Caroline Hayes, senior editor.

The market is not standing still, as evidenced by the acquisition of hardware companies in the PLDA Group by ReFLEX CES. The modified off the shelf and turnkey embedded systems company used Embedded World 2015 as a platform for its FPGA-based boards and System on Module (SoM) lines that were acquired in the sale of the sister companies, in January.

The acquisition brings the Accelize range, dedicated to the financial market, with FPGA accelerator boards, FPGA network processing boards, FPGA prototyping boards and SoMs alongside ReFLEX CES’ complex, high-speed and mezzanine FPGA boards based on PCIe, VPX and CompactPCI form factors.

“By uniting PLDA Group’s hardware solutions at ReFLEX CES, we strengthen our position as a leading provider of proven FPGA-based hardware for both COTS and MOTS FPGA solutions,” said Sylvain Neveu, ReFLEX CES and PLDA Group COO. He added that the diversification is expected to pave the way for a forecast growth rate of over 20% this year.

FPGA accelerator boards, network processing boards, and the XpressGX4, XpressGX5, XpressK7, XpressV7, XPressKUS prototyping boards as well as SoMs based on Xilinx and Altera FPGA devices took centre stage.

The company also launched FPGA boards based on Altera’s Arria10 FPGA at the show. The Arria10 GX FPGA board and an Arria10 SoC board target military and defense, communications, broadcast, high-performance computing, test and measurement and medical applications.

The Stimulus tool from Argosim saves rework time, says Argosim

Another Altera FPGA, Cyclone 5, was used in a GigE vision video demonstration board showing the company’s baseboard design, custom embedded design for system, board, firmware and software as well as manufacturing capabilities.

In another hall, Argosim was demonstrating a modelling and simulation tool that validates requirements before the design begins to help developers speed time to market.

The Stimulus modeling and simulation environment edits, debugs and tests design requirements so that system designers can verify the requirements before design begins.

The company estimates that around 40 to 60% of design bugs are caused by faulty requirements, so being able to verify them before beginning work reduces specification errors, process iteration and compliance costs for certification.

The tool’s high level modeling language formalizes natural language requirements, allowing the developer to express natural language requirements using formalized language templates, state machines, and block diagrams. These requirements can then be fully tested to identify errors before any design or coding takes place. A simulation engine generates and analyses executable traces to test requirements for real-time, safety-critical systems. The tool allows developers to define generic test scenarios and debug against inputs and generate test vectors for software-in-the-loop validation to reduce integration rework.

Fabien Gaucher, CEO, Argosim, explained that it is the ability to strip out some of the rework currently incurred that shortens time to market, yet the faults are often only found after coding and as a result of testing. One application example is the French electricity supplier, EDF. The utility company generates over 60GWe a year from over 50 nuclear reactors, and must comply with rigorous safety-critical standards. It uses Stimulus to validate functional system requirements early, and independently, from the design choices made by third-party sub-contractors.

It was a busy show for IP company, Cortus, with three software partners announced and two new cores.

The partners are Oryx Embedded, which has produced the CycloneTCP dual IP v4/v6 stack to support IPv6 which is the next-generation Internet Protocol, enabling more IP addresses, which can be connected in the Internet of Things. The second partner announcement is from Nabto, an integrated design environment (IDE), designed to offer licensees secure point-to-point connectivity from mobile devices, PCs and data systems for Nabto’s interfaces. Finally, the company announced that Blunk Microsystems’TargetTools is now interfaced to the Cortus toolchain as an IDE for TargetOS, the pre-emptive real-time operating system (RTOS) ported to the Cortus APS architecture.

The company has also announced design wins for some significant companies, such as Atmel’s WINC1500, the Cortus APS3-based, IEEE 802.11b/g/n IoT network controller, used in, among other WiFi applications, the Atmel Arduino WiFi shield 101. Microsemi has also integrated the Cortus APS1 in a family of smart sensor interface ICs, and StarChip, also based in France, has announced the third generation of Cortus-based SIM IC controllers.

I asked Roddy Urqhart, Vice President of Sales and Marketing, Cortus, about the ‘groundswell’ of companies from France at this year’s Embedded World. “Cortus is based near the University of Montpelier and other technology companies, so there is the local base, but also initiatives from the French Government, at local and national level,” he says “together with grants to promote R&D”. He also talked about the synergy of the south of France, with its strength in smartcards and SIM technology, such as Starchip which supplies controllers for cards up to and including LTE technology.

“The Cortus minimalist core makes it suitable for the cost-sensitive smartcard and SIM market,” he continues. “The minimal processor architecture can be used for any embedded application to save silicon, power and to add security,” he adds. The company reports a ramping up of licensees in the first half of this year in connected intelligent devices such as IoT network controllers, smart sensors, touchscreen controllers and next-generation SIM cards.

The company’s latest cores, the APS23 and APS25 were released in October 2014 and are based on the Cortus v2 instruction set.

By Caroline Hayes, senior editor.

Week in Review October 29

Tuesday, October 29th, 2013


Altera chooses quad-core 64bit ARM Cortex-A53 for Stratix 10 SoCs
At ARM TechCon, this week, Altera announced that its Stratix 10 SoC devices, manufactured on Intel’s 14nm Tri-Gate process, will incorporate the quad-core, 64bit ARM Cortex-A53 processor. It is the first 64bit processor used on an SoC FPGA system, says the company, which will roll out in May 2014, and will supersede the previous mid-range FPGA series, Stratix 5, says Chris Balough, senior director, SoC Products, Altera.

Spreadtrum signs ARM access license agreement
Fabless semiconductor company, Spreadtrum has signed a license agreement with ARM to supply Artisan physical IP for the IC foundry and 28nm processes, providing the Chinese company access to Artisan standard cells, next-generation memory compilers, including single- and dual-port SRAM compilers, on- and two-port register file compilers and ROM compilers, as well as POP IP for ARM Cortex processors and Mali GPUs.

IP Core interconnects mixed FPGAs
French design and manufacture company, Reflex CES, has released an FPGA Aurora-like 64B/66B IP core, to interconnect Xilinx and Altera high speed transceiver FPGAs for embedded military and telecommunications. It is based on Altera FPGAs and supports encoding and high-speed interfaces up to 14.4Gbit/s, enabling interoperability between the two competitors’ FPGAs, with an effective bandwidth of up to 97%, says the company.

Programmable SoCs use energy-friendly ARM technology
Multi-core microcontroller company, XMOS, has teamed up with Silicon Labs to form a technology partnership to integrate ARM technology into its xCORE multi-core microcontrollers to produce the next generation of programmable SoCs (system on chips). Silicon Labs will contribute the EFM32 Gecko, energy-efficient ARM Cortex-M3-based microcontrollers – the xCORE-XA (eXtended Architecture) family. The xCORE-XA technology was at ARM TechCon 2013

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