Diamonds are forever…or, at least, the effects of one particular diamond on quantum computing may be, according to a team that includes scientists from USC that built a quantum computer in a diamond.

The diamond is the first of its kind to include protection against decoherence—noise that prevents a computer from functioning properly. A demonstration of the technology showed the viability of solid-state quantum computers, which unlike earlier gas- and liquid-state systems, may represent the future of quantum computing because they can easily be scaled up in size. Comparatively, current quantum computers typically are very small but cannot yet compete with the speed of larger, traditional computers.

The multinational team included University of Southern California (USC) professor Daniel Lidar and USC postdoctoral researcher Zhihui Wang, as well as researchers from the Delft University of Technology in the Netherlands, Iowa State University and the University of California, Santa Barbara.

The diamond in the center measures 1 mm by 1 mm. (Source: Delft University of Technology/UC Santa Barbara)

The diamond quantum computer system featured two quantum bits, or qubits, made of subatomic particles. As opposed to traditional computer bits that can encode distinctly either a one or a zero, qubits can encode a one and a zero at the same time. This property, called superposition, along with the ability of quantum states to “tunnel” through energy barriers, some day will allow quantum computers to perform optimization calculations much faster than traditional computers, researchers said.

Solid-state computing systems have existed before but the team said this was the first to incorporate decoherence protection: using microwave pulses to continually switch the direction of the electron spin rotation. “It’s a little like time travel,” Lidar said, because switching the direction of rotation time-reverses the inconsistencies in motion as the qubits move back to their original position. The team demonstrated its diamond-encased system did indeed operate in a quantum fashion by seeing how closely it matched “Grover’s algorithm.”

Preventing Simulator Deadlock

With chips of the future likely to have hundreds or even thousands of cores, predicting how these massively multicore chips will behave is no easy task. While software simulations work up to a point more accurate simulations typically require hardware models: programmable chips that can be reconfigured to mimic the behavior of multicore chips.

Researchers from MIT’s Computer Science and Artificial Intelligence Laboratory (CSAIL) recently presented a new method to do just that: improve the efficiency of hardware simulations of multicore chips and guarantee that the simulator won’t go into “deadlock”—a state in which cores get stuck waiting for each other to relinquish system resources, such as memory.

This method is expected to make it easier for designers to develop simulations and for outside observers to understand what those simulations are intended to do.

Hardware simulations of multicore chips typically use FPGAs. However, chip architects using FPGAs to test multicore-chip designs must simulate the complex circuitry found in general-purpose microprocessors either by hooking together a lot of FPGAs but only modeling only a small portion of the whole chip design or by simulating the circuit behavior in stages, which is extremely slow.

Graduate students Asif Khan and Muralidaran Vijayaraghavan; their adviser, Arvind, the Charles W. and Jennifer C. Johnson Professor of Electrical Engineering and Computer Science; and Silas Boyd-Wickizer, a CSAIL graduate student in the Parallel and Distributed Operating Systems Group, adopted the second approach for a simulation system they’ve dubbed “Arete.” However, the system uses a circuit design they developed that allows the ratio between real clock cycles and simulated cycles to fluctuate as needed thereby allowing for faster simulations and more economical use of the FPGA circuitry.

One advantage of their system, the CSAIL researchers said, is that it makes it easier for outside observers—and even for chip designers themselves—to understand what a simulation is intended to do. With other researchers’ simulators, it’s often the case that “the cycle-level specification for the machine that they’re modeling is in their heads,” Khan says. “What we’re proposing is, instead of having this in your head, let’s start with a specification. Let’s write it down formally, but in a language that is at a very high level of abstraction so it does not require you to write a lot of details. And once you have this specification that clearly tells you how the entire multicore model is going to behave every cycle, you can transform this automatically into an efficient mapping on the FPGA.”

The researchers’ high-level language, which they dubbed StructuralSpec, builds on the BlueSpec hardware design language that Arvind’s group helped develop in the late 1990s and early 2000s. The StructuralSpec user gives a high-level specification of a multicore model, and software spits out the code that implements that model on an FPGA. Where a typical, hand-coded hardware model might have about 30,000 lines of code, Khan says, a similar model implemented on StructuralSpec might have only 8,000 lines of code.

–Ann Mutschler

By Ed Sperling
The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways.

It’s difficult to tell whether the trend is being driven more by the IP vendors or pulled through by chip developers looking to cut costs—or whether it builds upon the stamp of approval by foundries for certain pieces of IP. The net effect, however, is the creation of subsystems and partial platforms that are one step below reference platforms.

“A reference design suggests a complete solution,” said Eric Schorn, vice president of marketing for ARM’s processor division. “Customers don’t want us to go that far. But we are moving in a segment-oriented fashion. That’s the reason we bought a graphics processor company. We are making a processor along with a graphics socket for mobile phones and set-top boxes.”

The company isn’t alone in recognizing the opportunity for putting together more pieces of IP in very specific ways. Virage Logic’s recent acquisitions of ARC and NXP’s IP unit have positioned it to lead with integrated subsystems in markets such as high-performance audio and video.

“You have to have a reference platform these days,” said Yankin Tenurhan, vice president and general manager of Virage’s ARC business unit. “That’s not much different from the good old days of silicon, though, when you needed a complete solution and a full blown prototype. Philips, NXP, Texas Instruments and ST all have demonstrator chips for whatever you want on a cell phone. The same is happening in the IP world.”

Putting together the pieces
It’s not just the IP vendors that are putting together suites of IP. Two startups are focused on making IP easier to understand and integrate. Parallel Engines, which emerged from stealth mode this week, is focused on organizing IP by data mining pertinent information about everything from power requirements to the interfaces and interconnects.

“There are 12,000 pieces of IP out there, including 8,000 pieces of hard IP that are made by about 50 companies and about 4,000 pieces of soft IP,” said George Janac, CEO of Parallel Engines. “The hard IP is already in FPGAs from companies like Actel, Xilinx and Altera. You just need the soft IP to make it work.”

Somewhat conveniently, Janac’s brother, Charlie, is the CEO of Arteris, which makes network on chip technology that can be used to glue together these IP blocks.

“A company may have one or two pieces of IP that are the secret sauce and some software,” Charlie Janac said. “Why not drop those into an FPGA and connect up the other pieces of IP? Those two worlds are merging. We’re going to see much more custom logic on an FPGA.”

Another company involved in bringing IP together is Silicon IP, run by Kurt Wolf (formerly of TSMC), who said there’s a disconnect between chipmakers and IP vendors that still needs to be closed. “The chip guys distrust the IP industry,” Wolf said. “There’s more integration of IP, but there’s still a lack of confidence about how to choose, buy and license IP.”

Wolf’s company is focused more on bringing the two sides together with better information and connecting the pieces in an organized way.

The future
All of these efforts—by both large IP vendors and startups—are signs of just how important commercial IP has become in chip development. What began with embedded processors and standard memory designs has evolved into a huge market that actually gained momentum in the recent downturn.

Outsourcing is gaining ground at every level of business, even outside of the semiconductor world, but in the past most of the gains have been in areas where there was little value add. Outsourcing traditionally has been relegated to commodity services. What’s changing is that IP now includes areas that companies cannot do themselves in addition to those they don’t want to do, as well as the extremely tedious and time-consuming integration work that is necessary to create a final product.

When most analysts predicted a massive growth in IP at the beginning of the decade they were largely talking about small, relatively unsophisticated IP blocks pieces that can be put together by highly sophisticated companies. In the future, the differentiation may be less around the technology and more on getting very complex chips assembled and to market faster for specific market segments.

By The EEFocus Staff

FPGAs are booming in China. When Clement Cheung, director of marketing and applications at Xilinx Asia Pacific showed up to give a speech recently, he was worried not many people would come. He need not have worried.

The sales of all the major FPGA vendors show a significant bump in sales to the Asia/Pacific region. In Xilinx’s case, they exceed sales in North America, and there has been a huge increase in the number of FPGA engineers and engineers using FPGAs inside of China. This follows the shift of manufacturing to the Asia/Pacific region earlier this decade.

But Cheung said China is particularly important to FPGA vendors: “We pay more attention to the growth of Chinese enterprises because only they can truly influence the country.”

The proportion of FPGAs in communications and in the enterprise fell sharply following the 2001 downturn, but FPGA vendors managed to weather the latest downturn relatively intact by limiting their presence in communications to less than 50% and by hedging across multiple other markets.

“The main reason [for growth] is the 3G network deployment in countries like China,” said Clement Cheung. This was also one of the key reasons that the Asia/Pacific reason posted strong growth. Xilinx’s growth in China has been in the double digits, Cheung said.

FPGAs have been particularly popular because they lower the barrier of entry for design companies. It currently costs millions of dollars for an ASIC mask, but an FPGA is a much less expensive alternative. Huawei, which applied for the most patents inside of China in 2008, based a lot of its work on FPGAs.

“In China, FPGA engineers have a larger number and all of them stand on the same starting line,” Cheung said. “But FPGAs are more than a pure chip game. At present, most engineers need to consider signal integrity, layout, timing and other system-level issues.”

Xilinx CEO Moshe Gavrielov pointed out that the device functions had changed in the FPGA industry over the past 25 years, evolving from the simple circuit such as peripheral interface and glue logic to the main chip of whole system. “The concept of platform was not obvious because customers didn’t need too many application designs in the past. Today, the chip, software and whole design environment all need to be combined together for the project design.”

–EEFocus is the Chinese media partner of System-Level Design.

By John Blyler

A just completed EDA tools and technology survey of 140 engineers conducted over the past several weeks shows a strong push into full-custom devices and FPGAs. In fact, 32% of the ICs being designed by engineers using EDA tools were building full custom devices, and another 24% were building FPGAs. Only 9% were working on ASICs, although the ASICs tend to be large and extremely complex chips.

About 14% were designing analog arrays and another 11% were using gate arrays. Another 10% were building ASSPs.

If you think things are bad, be glad you’re not in the Taiwanese foundry business—where the pain level is strangely uniform.

TSMC’s sales dropped 59.5% in February compared to the same month last year, and 7.5% compared to January. How many ways can you spell ouch? 

UMC’s numbers are down 56.9 percent in February 2009 vs. the same period in 2008. That’s pretty close. In fact, it’s remarkably close.

This kind of information is only available in Taiwan. SMIC, based in Shanghai, and Chartered, based in Singapore, don’t report monthly sales numbers.

Nevertheless, there was at least some encouraging news out of Chartered. It said that sales seem to be stabilizing and wafer starts appear to be increasing for Q2. 

There is evidence of this showing up in other parts of the market. U.S. retail sales, excluding big-ticket items like cars, show modest increases in areas like clothes and consumer electronics. Numbers were up in January and February. It certainly wasn’t a robust gain, but it wasn’t negative, either. That will translate into new design starts sometime in the next few months, which barring any more major drops will start this whole cycle rolling again.

Design activity has to begin at least six months prior to any turnaround, which means that if the overall economy is expected to show growth in 2010,  electronic designs have to begin by mid-year—perhaps even sooner.

None of this is perfect, however. Why, for example, did National Semiconductor just announce plans to cut 26% of its workforce? At least part of that can be explained by closing of an assembly and test plant in China and a fab in Texas. Too much capacity is expensive, and we wouldn’t be surprised if National ultimately begins outsourcing some of its work to foundries. Yes, it’s analog, but is it still more efficient to run fabs yourself, even if they’re fully depreciated, when TSMC and UMC are begging for business?

Meanwhile, in the FPGA realm, chip design is getting so complex that EDA vendors are finally beginning to find inroads. This is a market previously owned by tools from the FPGA vendors, which they readily gave away to customers at little or even no cost. That worked fine before the industry got to 90nm, and at 45nm it’s tough enough even with the best of tools.

Mentor introduced its Precision Synthesis Tool family for Altera’s Stratix and Arria families. Our guess is that you can expect to see a lot of activity in this market in the near future, and not just from Mentor. Synopsys’ purchase of Synplicity gives it a vested interest in the FPGA market, as well.

–Ed Sperling

What can go wrong when you use commercial off-the-shelf parts in military applications? We asked Daren McClearnon, an ESL specialst at Agilent.

Chips continue to grow in complexity. This is nothing new. But even at the existing process nodes of 180nm and 130nm, complexity is increasing as designers attempt to squeeze in more feature sets while shrinking the power budget and chip size. This growing complexity, married with the shift to time sensitive consumer product markets has led to an increase in the use of prototypes to verify these chips prior to production.

But what do users really seek in prototyping tools? The report that follows contains the summary and analysis of a survey conducted with more than 270 qualified respondents in the ASIC and related markets. The results track well with similar surveys in this space, but the details present some surprising implications.

Application Markets

Most responders listed the communication market as their primary product area, followed closely by the Consumer, Computer and Other markets (see Figure 1). Most prevalent “Other” markets were Industrial, followed Mil/Aero, Automotive and Medical.

Figure 1

In the category of communications, most respondents listed wireless handsets and wireless and wired networking as their chief application areas, followed closely by wireless base station design, telephony/VOIP and wireless Metro Area Networks (MANs). A small percent listed research, remote controllers, CDMA networks, fixed networks, telemetry and military as other areas of focus within communication category.

In the consumer market most respondents list multimedia designs – involving both video and audio subsystem – as their primary area for developing ASIC prototypes. Multimedia design concerns will be reflected proportionately in other parts of this survey, i.e., processor types, interfaces, etc. Interestingly, several designers listed games as their chief concern. That’s a trend we will watch in future surveys.

Computer design issues were most closely tied to peripherals such as storage, printers and the like. PC and workstation systems came next, with others including prototyping systems, servers, data acquisition modules, and instrumentation and software/firmware design issues.

Job Function

Most of the respondents identified themselves as ASIC or ASSP designers, followed by engineering management, corporate management, verification engineers, system architects and software designers. A small percent of users listed their function as applications engineers, business development, academia and sales/marketing.

Figure 2

ASIC/ASSP/SOC Design Details

When asked to describe their current ASIC/ASSP/SoC design, more than half of the respondents indicated a design size of less than 5M gates, with that majority below 2M gates.

In terms of memory, most designers focus on SRAM memory, suggesting the strength of on-chip memory prototyping. Still, DDR and Flash memory account for about 22% each of memory usages.

Embedded processors usage is led by the MIPS processor, which matches up with the respondents’ applications markets. ARM, Tensilica and Intel comprised roughly 16% each of the remaining usage. Other processors used for ASIC prototyping ran the gamut from microcontrollers like the 8051, Microchip’s PIC and Xilinc’s MicroBlaze to proprietary cores. A large number of DSP cores also were cited, including Ceva Teak Lite, TI and in-house multimedia DSPs.

To the question concerning the types of external interfaces used in ASIC prototyping projects, the top three busses were PCI, USB and Ethernet. SPI, SATA, XAUI and HDMI finish up the lower quadrant. Though not listed in the survey, questions have arisen about the use of the PC-104 bus. Several experts believe PCI Express represents the path forward for PC-104. This projected growth will be the subject of a future survey.

The majority of users listed Serial RapidIO (sRIO) as the main external bus of choice under the “other interface” category. This is no surprise, since the sRIO interface is commonly used to connect multiprocessor designs, especially for DSPs. This tracks well with the use of DSPs highlight in the “Processor” usage category cited earlier. Other interfaces include I2C – a low-speed serial bus used to attached peripherals to a motherboard, embedded system, or cellphone; DVI, RS-232, parallel bus, CAN – automotive bus, DigRF – digital serial interface for 3G air standards; and even UART.

Re-spins

A little over half of the respondents indicated their previous design project required no re-spin. Of those acknowledging re-spins were necessary, 50 percent stated that only one re-spin was needed. About half as many reported by two re-spins were required and slightly less than 10 percent admitted to three re-spins.

The main reason for chip re-spins was the presence of logical and functional errors. This result tracks well with other recent studies that indicate more than 60 percent of re-spun ASICs fail due to logical/functional errors, not because of timing or power issues. This means that functional verification is now the most critical phase of the chip development cycle.

Figure 3

Verification Environments

When asked what type of verification was used for a current project and planned for future work, the largest groups of respondents selected Mentor’s ModelSim/Questa. This was followed by Cadence NC Simulator and Synopsys VCS.

Figure 4

Other software simulation environments consisted of tools from IBM, Altera’s QuartusII and Xilinx’s ISE, Synplicity’s Synplify, Dolphin’s SMASH and Catena’s Analog and Mixed Signal (AMS) Simulators, Aldec’s Active-HDL Simulator and homegrown systems.

In terms of emulators, most users listed Cadence systems, followed by Mentor and Eve. An interesting side note is that only Eve emulators saw a planned increase for future projects. Formal verification favorite was Formality, followed distantly by OneSpin, Real Intent and Certess. System Verilog lead the way in Assertion-based tools, followed by OVL and PSL.

Here’s where the results get interesting. When asked what type of virtual prototyping environments were currently being used, ARM was the favorite – but by a decreasing margin for future projects. Synopsys’s Virtio was the second most popular choice, showing projected growth along with CoWare, VaST and Virtutech. One should exercise caution when interpreting these results, since the slower pace in usage of ARM tools may simply reflect the growth of virtual prototypes in non-telecom related industries.

Figure 5

Looking at the other end of the prototyping spectrum revealed that Synplicity was used more often for ASIC prototyping with FGPA-based systems – at least in the market areas highlighted by this study. ProDesign followed second, then came Dini and Gidel. It must be noted, however, that 36 percent of respondents still used custom-built FPGA-based prototyping, though the percentage was on the decline for future projects. This marked decrease in custom-built systems may attest to the growing complexity of ASIC designs and hence the corresponding complexity of FPGA prototypes.

Conclusions

This survey points to the changing dynamics in ASIC prototyping tools and methodologies. Prototyping of specific blocks on an ASIC core now seems mandatory, especially since ASICs continue to increase in design complexity. This complexity is manifested by an increase in logical and functional errors in the chips, which has resulted in a need for more complete verification tools and methodologies.

But prototyping itself has taken on a new dimension with the advent of virtual prototypes – used more often by software designers – and FPGA-based prototypes used by chip hardware engineers.

These trends have been confirmed by other studies. For example, Aberdeen’s “Best in Class” study cites verification as one of the most prevalent concerns in chip companies. Chip Design Trends reports, which tracks ASIC pre-silicon architectural trends, confirms the growing complexity of ASIC chips – at all levels of design metrics. Contrasting this complexity with the continued decrease in ASIC starts suggest that ASICs may be getting larger in size though less numerous in unique projects. All of these trends support the growth of prototyping as a key element in future chip designs.

On the business side of the equation, one should note the shift away from corporate electronic expenditures to the rapid increase in consumer’s consumption of electronic products. The consumer world is outpacing the corporate world in the purchase of electronic goods, but there is a caveat: Consumer electronics have a shorter time to market, high product volume but lower cost per unit that corporate electronics. What does this mean to chip designer? It means that they must find a way to reduce ASIC re-spins, such as with ASIC prototyping.