By Ed Sperling
Mentor Graphics inked a preferred partner deal with Freescale to deliver a Vista-based virtual prototyping solution for its processors. The really interesting part of this one is that Mentor is now facing off against Synopsys and Cadence in the virtual prototyping market. Mentor also signed a deal with Ecrio to collaborate on Nucleus-based LTE IP Multimedia Subsystem platforms, and it acquired the Flowmaster Group for computational fluid dynamics simulation software. In the world of stacked die, this stuff will play an interesting role.

Tensilica introduced an audio DSP core that it claims improves performance more than 1.5 times for post-processing in smart phones and audio entertainment. Post processing is vital as the size of speakers continues to shrink. The smaller and flatter the device, the more complex algorithms that are required to reconstruct sound.

Cadence expanded its NAND flash IP lineup to include support for the Open NAND Flash Interface 3.0 spec. This spec is aimed at eliminating a bandwidth bottleneck in memory.

Arteris won a deal with Beijing Nufront for its network-on-chip interconnect IP and its shared memory technology. Beijing NuFront makes mobile phone SoCs.

By Ed Sperling
Altera is embedding Synopsys’ virtual prototyping technology in its ARM-based SoC FPGA products. Considering FPGA vendors have been giving away their tools for years, much to the chagrin of EDA vendors that have tried repeatedly to win a foothold in the FPGA tools market, this potentially is a big deal. And considering the existing market for virtual prototyping is still small and the FPGA opportunity is quite large…well, this gets very interesting.

On another front, Synopsys is collaborating with UMC to develop IP for the foundry’s 28nm HLP Poly SiON process.

Mentor Graphics is working with Freescale to accelerate automotive infotainment that relies on ARM A9-based processors. Mentor’s In-Vehicle Infotainment base platform is compliant with the requirements of the GENIVI Alliance, the association of automotive and consumer electronics companies.

Russia-based IntegrIT has ported its NatureDSP Math Library to Tensilica’s baseband DSPs. The traditional emphasis on science and math is still alive and well in Russia—and expanding into some new markets. IntegrIT develops signal-processing routines for DSP functions.

By Ed Sperling
The semiconductor industry is used to looking at changes every couple of years, based upon the progression of Moore’s Law. But look out further, over the next five years when the most advanced process node is somewhere between 14nm and 16nm, and the job of designing and manufacturing an SoC will look very different.

At the center of this change are three very significant trends:

1. Cost increases. It will cost way too much to develop custom SoCs using current methodologies, tools and strategies at 20nm and 14nm, both from an NRE and from a time-to-market perspective.
2. Software plus hardware. Software is becoming a huge part of the chip design, but while hardware design is getting more complex it’s still improving at a far faster rate than software development.
3. Time to vertical markets. Differentiation will be based on the ability to quickly cobble together chips that meet the needs of different markets—either for vertical markets or specific customers—at a reasonable price point.

Derivatives market
One of the biggest shifts will be in the integration of in-house and external IP blocks, subsystems, and ultimately full die into chips—and in being able to create far more derivatives out of those various pieces more quickly.

Freescale, for one, already has embarked on a plan to figure out where it can add the most value in its chip development, which is primarily multiprocessing cores and advanced interconnects. In the future it will buy much of the standardized I/O and memory technology that it built in the past to focus its efforts on core hardware components, software development and integration. Derivatives are a key part of that strategy, and it is emerging as one of the recurring themes across all SoC development at future nodes.

“The cost of all development will go up, so you have to get more efficient by developing simple derivatives,” said Lisa Su, Freescale’s senior vice president and general manager of networking and multimedia. “Silicon design has to become more modular. A lot of the differentiation will be in the software stack.”

She said the challenge is to find translators—people who understand how to bridge the gap between hardware and software. “To build really good hardware you have to understand how the software programming model works. Software drives the hardware.”

Freescale is hardly alone in recognizing this shift into derivatives. But derivatives for a large fabless company such as Freescale have a different meaning than derivatives for a midsized company, which will rely much more heavily on outside service providers such as Open-Silicon, eSilicon and Global Unichip to build these kinds of chips.

“What we’re talking about is not breaking new ground or creating major IP,” said Naveed Sherwani, president and CEO of Open-Silicon. “To really address the cost issue there will need to be derivatives outside of companies, and a lot more more companies doing derivatives. There will be a consolidation in design services, which will be fully integrated in derivative design. Derivatives keep the complexity contained.”

A complex SoC might cost $50 million to $70 million to design at advanced nodes, but 10 or more derivative chips might only cost $5 million to $7 million each. That makes them much more affordable and allows companies to put their dollars where they can best be used for differentiation.

Abstracting up
From a tools standpoint, there needs to be a giant step to another level of abstraction. There simply is too much detail and data to process in a complex SoC that today contains up to 100 million gates, and which in a couple process nodes could contain billions of gates.

“The existing way of doing things will break down,” said Ravi Varadarajan, fellow at Atrenta. “Design closure is still being done at the place and route level with power estimation. That needs to be raised by a level of abstraction. With a higher level of abstraction you can do more with less effort. This has been a long time coming. We need to elevate this process from the gate level and RTL so we can put together a system. I was speaking with one customer that put together a complex SoC. It took them 1-1/2 to 2 years to close the chip. They were going back and forth over whose problem it was.”

He added that will become particularly important in 2.5D stacking, where integration will have to occur at the subsystem level. But whether a high-speed bus or a low-speed bus is used to connect those subsystems, all of that should be transparent to the designer. Similarly, exploration at the SoC level should allow changes in memories that are used to connect to multicore processors that are reflected in other parts of the chip architecture.

There is almost universal agreement about the need to raise the level of abstraction. The question is when, by whom, and whether that abstraction level will include enough details to be useful—particularly when making architectural tradeoffs about such things as different memory configurations, power measurements that are useful, and how that will work with an increasing amount of third-party IP. Block re-use is expected to increase to more than 70% of an SoC design in 2015.

“One of the main technology challenges is block design and re-use,” said Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. “The main issue there is integration. From the technology side we need to figure out connectivity. We can take care of the registers at all locations, and then you’ve got companies like Arteris, Sonics and ARM that are addressing how you put it all together. But you’ve got lots of blocks and assembly of blocks.”

Those blocks increasingly are being assembled into full subsystems, too, which are beginning to show up on the market complete with software drivers.

Software first, software last, software everywhere
Software is a complicating factor, though, rather than a simple solution. While there has been lots of discussion around the challenge of getting hardware engineers to talk with software engineers, there has been far less discussion about just what each piece of software code should do in designs.

One of the reasons is that there is no simple answer. It all depends—on the market, the device, and what is the motivation of the companies developing the chips. Are they looking to maximize performance, minimize power, or simply build lots of derivative chips that can function using the same basic hardware.

“There are different ecosystems forming,” said Jack Browne, senior vice president of sales and marketing at Sonics. “Before you might partner with Wind River and Monte Vista. Now you partner with the application developers.”

What this means for chip designers is that it’s no longer a closed world. In the past most chips were written to specs that focused on performance, process technology, power budgets or some other well-defined set of rules that were largely hardware-specific. In the future those boundaries will be far less well defined and they will need to be modified quickly based upon individual markets. Software is one way of doing that, providing the hardware can take advantage of the software.

There has been a fair amount of discussion already about devices being software-first or hardware-first, with some engineers and companies taking a middle position saying there needs to be a better bridge. In the future the decision of how software is written may include everything from popular applications, use models, vertical and regional markets—as well as all the old rules.

“In the mobile world, where you have Google TV and Android running on high-performance platforms like MIPS and ARM, that’s where application-specificity comes in,” said Synopsys’ Schirrmeister. “In the automotive world there’s AUTOSAR (automotive open system architecture), which separates the software from the hardware so you can control the whole stack from the hardware to the software. The challenge is which version you’re on. Then you’ve got the semiconductor manufacturers and IP providers doing things like Linaro on the Linux side to make sure the right platforms are supported. “

Business effects
While the technology and process changes are significant, they are at least better understood than how that technology will intersect with business. Chips will still be built. More components and services will be outsourced. The price will be more affordable to some, less affordable to others. And software will have to be written more quickly and verified more easily than it is today.

Where things get fuzzy, though, involves who is best positioned to take advantage of these changes and who will reap the lion’s share of the rewards for getting the formula right.

Sonics’ Browne says the market has split into small chipmakers that want to push the leading edge of performance and/or low power, those that are looking for a unique volume play in the consumer electronics/smart phone market, and those looking to break into new markets such as portable medical devices once the price point drops low enough.

“The question is how quickly you can do derivatives, or whether you can compete with the old superchip approach,” noted Browne.

Freescale’s Su has a similar take on the market. She said the goal is to start with a platform that can bridge many end markets, then customize it for specific uses. “We’ve been working on ARM-based products that can be used in auto infotainment as well as industrial and medical markets. You start with a general processor as a test chip and then branch off from there.”

But who wins from those designs, and who ultimately loses is unknown at this point, and while design and development will be built on years of evolutionary changes, the business ramifications of those changes are far less obvious.

By Ed Sperling
System-Level Design sat down with Kathy Werner, IP strategy and business manager inside of Freescale’s Design Technology Organization, to discuss tagging of soft IP. What follows are excerpts of that conversation.

SLD: How new is the concept of IP tagging?
Werner: IP tagging has been around for a long time. VSI Alliance was one of the first standards organizations that looked at IP tagging. It started out as the Virtual Socket Interface Alliance. They had a number of initiatives they were addressing. One was the on-chip bus specification. They also did the quality IP specification, they started the encryption standard, looked at IP transfer, defined the list for standard deliverables. The goal was to facilitate IP re-use between design groups, between companies and between vendors and customers. Tagging was one of those efforts, and it really was intended to provide some security around IP. There were two aspects to this. One was a soft IP spec and the other was a hard IP spec.

SLD: How far did it get?
Werner: The hard IP spec is in wide use. TSMC was an early adopter. It really is a text string put on the text layer of a GDS. Any back-end tool that can read the GDS can read the back-end field and determine where this IP came from.

SLD: While IP may adhere to standards, a lot of it isn’t characterized effectively. Will this help?
Werner: Not initially. The tagging tries to define the ownership and the origin. There are additional fields for the size and there are user-defined fields where you can put the process. It’s not going to be complete, but for the hard IP this information travels with it. There isn’t anything about interference or cross-coupling.

SLD: How about for the soft tagging?
Werner: The intent was to track the IP that went through the design flow. You have RTL here. It went through synthesis on this date, for example, using this company’s tool. That really depended on all the EDA tools that touched the tag. If one tool didn’t do that you lost all your tags, so needless to say soft tagging never got going. That left a huge gap. Whenever a vendor delivers IP you lose all control of it. It can be copied and used someplace else and you don’t know. Being able to tie it to the source, to where it’s used, and to the royalties constitute a first step.

SLD: So no matter where IP comes from or where it gets used—whether it’s in the United States or China or Taiwan or some other country—at least we know where it’s from, right?
Werner: Yes, right up front.

SLD: But what’s missing is still other information, such as how it reacts to physical effects. Will that be provided in the future?
Werner: That gets into the hard-tagging spec, and should we revisit issues that are more relevant now than they were five to eight years ago? Probably, but it’s not being considered right now.

SLD: Who would drive that effort?
Werner: When the VSI Alliance folded, it donated its tagging specs to Accellera. They are in the public domain and they’re freely available to anyone who wants to use them. But with any standard effort, it will be the pull of the users.

SLD: How about IP-XACT? Is that comprehending the tagging?
Werner: We’re proposing that now. Nothing has been finalized.

SLD: What is the next big challenge in tagging?
Werner: From my viewpoint, the big issue is figuring out the tagging for soft IP. That’s what we’re trying to drive forward. It’s becoming a bigger issue and a lot of people have a lot of different views on this. For example, the FPGA companies are moving more and more into IP. Historically, they have given away IP to sell silicon. But the IP is getting so complex and expensive that it’s no longer a sustainable model. Now they need to know who’s using their IP so they can collect royalties.

SLD: Who’s backing this move?
Werner: Any vendor with an IP royalty model should be all over this.

SLD: How do the tags work?
Werner: Here’s one implementation: If you end up with text on GDS, it supports and enables honest users. It can be deleted, so you’re assuming people want to do the right thing. But if the tag is in the GDS, you can still get the information about ownership.

SLD: Is that robust enough?
Werner: That’s something we’ve been discussing. Should the tag be a watermark or should it be encrypted? We’re still looking for industry input on that.

SLD: Doesn’t it also protect the company that uses the IP from liability issues?
Werner: Yes, absolutely. And having some way of identifying the version of IP helps with bugs. You know which products are going to be affected. If you tape out version 1.0 and you have a derivative design that uses a later version of IP, you know which version is going to be affected.

SLD: Where are we now with this effort?
Werner: Accellera has been working on this for several months. An IP provider is going to have a different view than a semiconductor company like Freescale, which is going to have a different view than an FPGA vendor. We’re trying to get all these inputs to really scope out what needs to be done.

SLD: Why is Freescale involved?
Werner: We have been using the hard-tagging specs internally. We tag our libraries. But like any company we’re using more and more third-party IP. We want to make sure we’re legally compliant and have a data-driven approach to tracking that IP. Now there are spreadsheets and bills of materials, but anything with that much human intervention is prone to errors.

By Ed Sperling
Mentor Graphics added embedded Linux platform support for Freescale’s QorIQ 64-bit multicore processors. Included is a jointly developed workflow methodology for embedded Linux development, which will help reduce software development time.

Freescale also cut a deal with Wind River—the RTOS maker that was bought by Intel—to collaborate on software for QorIQ and PowerQUICC chips. The deal formalizes collaboration that has been under way for some time.

Semico Research predicts a short slowdown in the semi market in the second half of this year and at least early 2012 due to excess inventory in tablets, PCs and smart phones. The research house expects growth to resume in the second half of 2012.

But there are certainly more chips and bigger markets opening up for companies that have diversified. MarketsandMarkets predicts that automotive chips will account for $35 billion in sales by 2014, up from a high of $20 billion in 2007. Nice jump.

By Pallab Chatterjee
The push toward mobility in consumer devices is having an impact on the entire component flow.

Mobile devices are dominated by two key factors—an overriding power constraint and very high data bandwidth. The power constraints are on the mobile device side and on the cloud-based support server side. The high data bandwidth issues are due to the limited processing power available and the need to switch between functions, rather than keeping a common memory load and multiprocessing of the data.

The power side for the mobile devices has been discussed in depth. The impact on the rest of the system is less well known. Because mobile devices have to process data on a limited power budget, the support for these devices—the carrier and connection network, and the computing cloud that the device is connected to—has to pick up the slack on the processing front. New custom chipsets and processor architectures are being created to address some high-volume connection tasks such as display view transcoding, security processing and authentication, and sensor/imaging data processing. These chips are making their way into the network connectivity side with multicore being the dominant format for network processors. Also on the networking side, the addition of dedicated, power-optimized AES encryption/decryption blocks allow for secure data traffic on a per block basis with mobile devices.

Also on the power side is the change to high-bandwidth interfaces such as 10G, 40G (organized as 4 lanes of 10G), and 100G (organized as 4 lanes of 25G). While it would appear these interfaces consume more power, the reality is that when implemented in pairs, the lower duty cycle and larger packet size enable low power. For the 100G interfaces, the ability to implement the 25-28G lanes with 32nm and below CMOS offers huge power savings, as the PHY/MAC pairs actually consume less dynamic and active power than 10G lanes implemented in 40nm processes.

The data bandwidth is one of the keys behind the multicore architectures of both mobile devices and server designs. To optimally process data, database access, still images, video content, audio content, gaming graphics, and sensor data (touch screen, gyroscope, GPS, etc.), separate processing engines are usually employed. This is a key driver for multicore where the task base can be continually loaded, and only the data sets get changed. In order to handle the diversity and volume of data sets to be processed, wide- and high-bandwidth data paths are needed. Servers have moved to deep memories architectures to support the cloud computing from smartphones and tablets.

Similarly, the data bandwidth of broadband and wireless are increasing. For broadband, there is a need to put more data per channel on existing lines. This is being done with new wide data architectures that support multiple lanes of SerDes driving the network. To handle the large variety of data that is being presented, new cross-point switch architectures as well as multicore internal bus architectures are changing. These new buses are both externally expandable and support individualized power and data management for each core on the bus.

These different architectures are responsible for the division in use model of the various available cores. Tensilica cores tend to be used in audio processing applications, MIPS and Freescale cores are used in network transaction and security processing, ARM cores are used a generalized CPUs for mobile devices, x86 architectures dominate the main server side and specialty DSPs abound on sensor processing. As the data consumption systems moves to being more mobile-centric, the whole ecosystem from servers to delivery is now shifting to a true ultra-thin client computing model.

By Ed Sperling
Mentor Graphics rolled out emulation solutions for 100Gbit Ethernet products, combining its Veloce emulation with iSolve to verify multi-port Ethernet-based designs. This kind of combination is unusual at the emulation level. We expect to see more of these kinds of combinations in the future, particularly for vertical markets.

Cadence struck a deal with CERN, the European nuclear research group, to create and maintain design environments. Cadence will develop and manage the analog/mixed signal flow and provide support and training. This is an interesting application of chip design technology and professional services.

Synopsys rolled out its next-gen data converter IP, which uses 50% less power in a smaller footprint. The IP includes analog-to-digital and digital-to-analog converters for broadband wireless communications. Synopsys also struck deals with Freescale and Wilocity. Freescale has licensed Synopsys’ DesignWare IP portfolio of interface and analog IP. Wilocity is licensing IP and obtaining professional services.

By Ed Sperling
What’s in a name? Apparently not enough. Cadence’s Tom Anderson looks at some alternative suggestions for DVCon.

Mentor’s Thomas Bollaert cites some really interesting verification stats, which were presented at DVCon by Mentor CEO Wally Rhines.

Synopsys’ David Hsu examines high performance computing in a cloud and what effect that could have on EDA. The impact on chipmakers’ operating expenses could be significant, but only if they’re actually willing to move data into the cloud.

Harry Gries, aka The ASIC Guy, talks about the blurred lines between winners and losers in sports and in EDA. In EDA there’s certainly good reason for being civil to the competition, though. You never know who’s going to be your next hire or your next boss.

John Cooley’s DeepChip features an anonymous but positive report of a speech by VC Jim Hogan on SoCs, IP, design management and verification. In Hogan’s opinion, the future is all about SoCs and IP.  DeepChip also ran the results of a Mentor survey on high-level synthesis from Shawn McCloud. What’s particularly interesting are the advantages for cycle-accurate implementations of control logic using HLS and the split between untimed, partially timed and cycle accurate on algorithm implementation.

Cadence’s Richard Goering drills down on the Open SystemC Initiative with a video interview of its chairman—Intel’s Eric Lish. Goering asks all the important questions.

Mentor’s Mike Jensen compares fast cars to simulation. That assumes, of course, your simulation actually runs fast.

Synopsys’ Navraj Nandra looks at a new standard, G.hn., which unifies the physical layer and data link layer over multiple wire types in the home. The next step is unifying wired and wireless, which should have interesting ramifications for all sorts of consumer and business electronics.

Speaking of converged communications, Semico’s Tony Massimini takes the covers off Thunderbolt, the new and much faster interconnect technology developed by Intel that made its debut in Apple’s new MacBook Pros. The big question is how fast it will be adopted—and by whom.

Cadence’s Joe Hupcey rolls out another video, this one for assertion-based verification involving a paper from Freescale and Cadence. Considering formal verification’s continued growth, this is an area that everyone will need to get comfortable with.

Mentor’s Dave Rich offers up some inside knowledge for using UVM 1.0 with Questa. If you work in this environment, this stuff should come in handy.

Also deep in the weeds of verification, check out the blog by Verilabs’ Asif Jafri in Synopsys’ VMM Central.

And on a broader note, Cadence’s Sharon Rosenberg looks at TLM 2.0, UVM 1.0 and what they mean to verification. At 28nm, quite a bit.

By Pallab Chatterjee
In the enterprise it’s all about speed and power—as in more speed and less power—and those changes are forcing shifts in the chip architectures as well as the processes used to develop those chips.

At the Linley Data Center Conference the next generation of network control chips were discussed. The keys for the new networks are 10G data lanes to be used with 10G/40G and 100G applications. For 100G the alternate configuration from 10 lanes of 10G was 4 lanes of 25Gb/s also being designed with 40nm.

The 40nm processes give the advantage of the data speed that was needed, plus power savings that are required to keep the reliability of the die and package. The trend is that these high-speed switches need to be available not as single PHYs, but as duals and quads. The 40nm node allows for target power at about 3W for these parts, which will enable 24- and 48-channel switch products.

The PHY that is being provided by most of the vendors can, with the 40nm process, support security data processing. The architecture for many of the high-throughput data systems includes local data analysis, decryption, policy and authentication testing off the early data bus just after the transceivers. These application processors can be on the same die or separate die from the PHY.

In applications where there are separate server processor chips, the trend is toward 32nm processes with multicore configurations. Intel is offering 6- and 10-core products under the Westmere architecture. For the upcoming Sandy Bridge architectures, they are featuring 8 and 12 cores using the 32nm process. On the server processor side, there also are 32nm products from AMD using the new “Bulldozer” architecture. Rounding out the server side there are also new cores from ARM with the Cortex A-15.

For dedicated application processors, a number of multicore processors are now available using 40nm processes. These include the 16-core Octeon from Cavium Networks, the 8-core QorIQ from Freescale, the 4-core ACP3448 from LSI, and the 8-core XLP family of processors from Netlogic Micro. Also in this space is the Netronome NFP-3240, which is a 40-core 40Gbps flow processor that is a co-processor to the Xeon main processor for network traffic handling.

One of the power/performance drivers is the security aspects of the networks. The Federal Information Processing Standards (FIPS) 140 is focused on cryptography and security systems, not on items such as firewalls, Web filters, spam and virus protection, or content and flow control. The cryptographic modules are constantly increasing in complexity of their algorithms and degree of touch of the data.

By Ed Sperling
Just because a smart phone is sold by Verizon or AT&T mobile no longer means that it will be used primarily as a phone.

That distinction may sound trivial, but it has deep implications for the components that are used inside of these devices, how they’re used, and who wins the designs. Shifts such as this can also lead to broad changes in who buys the tools to develop the components, which tools they buy, and what sorts of flows they create with those tools.

There are several fundamental reasons why this shift is occurring, and all of them intersect and support the others.

Generation, geography and culture
First, there is a huge generational and geographical gap between what’s important in phones. For older users, voice conversations are the most important feature. For younger users, texting and games are key. And for business people on the go, the most useful features are a combination of voice and e-mail.

“This trend began in China, where a phone is not considered a voice device,” said Charlie Cheng, CEO of Kilopass. “It’s very textual and graphical. You use it for text, Facebook and browsing. Young people all use it that way, too. My kids think it’s a novelty when I call them on the phone.”

The tablet has blurred the lines even further. While most of the comparisons have been between tablets and personal computers, the real volume market overlap will be between smart phones and tablets. Both are capable of texting, videoconferencing and e-mail, and each can go places and do things that the other cannot. A tablet has huge possibilities in the business world and in places such as hospitals, where a touchscreen is preferable to a keyboard because it can be wiped clean. It’s also better for making presentations. But while it fits in a briefcase, it doesn’t fit in a pocket—something that may change as flexible screens begin production.

“A phone is no longer a phone,” said Vishal Kapoor, vice president of product management for SoC realization at Cadence. “The three most important issues are security, management of data—including how much of that is local information—and the video or graphics. Even bandwidth is no longer a problem technologically, although not all of the phones can take advantage of 4G yet.”

Power and performance
The second major change is in performance and power. While the two typically are tradeoffs on the same SoC, they’re not necessarily tradeoffs in the same package.

For the past couple of generations, smart phones have been able to hold their own as full-fledged number-crunching and computing devices. They can be used to surf the Web, do e-mail, download documents and photos, and even update those documents. While the form factor is limiting, the tradeoff in portability may suffice for executives or salespeople on the road.

But the real opportunity is less in conventional desktop or notebook computing than a raft of new applications. Apple reportedly is working with Visa, for example, on “swipe and go” technology, where a smart phone is used as a checkout device that can replace credit cards using near-field communication technology. Phones already are being used as boarding passes on many airlines, particularly in Europe.

These features are a sign of just how far performance has increased on these devices. Apple, MIPS, Freescale, ARM and Synopsys (through its ARC acquisition) all have developed very powerful multicore processors that draw very low power when used in conjunction with such approaches as power islands and power gating.

“What’s changing is that you’re starting to put a lot of personal information into these devices,” said Cheng. “There’s a lot of money involved in this and there’s a lot at stake.”

The Android effect
A third factor that is contributing to this shift is Android. The operating system developed by Google is spawning a revolution in how devices such as smart phones are used—and who wins the designs.

MIPS, which was one of the first adherents of the Android platform, is experiencing huge growth—much of it because of Android. The company’s revenues grew 44% in Q2 of 2010 vs.Q2 of 2009.

“The playing field is wide open,” said Art Swift, vice president of marketing and business development at MIPS. “What’s changed is those companies that were the leaders in the past in mobile will not necessarily be the leaders in the future. That’s especially true with tablets. Part of the market driver here was Android, and it’s wide open. There’s a whole cast of new players.”

Not all of it is happening in the usual places, either. John Koeter, vice president of marketing for IP and systems at Synopsys, says Android is opening up other markets that didn’t exist in the past.

“We’re not going to play in the shootout between MIPS and ARM,” said Koeter. “But we are seeing new markets for things like picture frames that can be interconnected and run applications. There are all sorts of new and interesting applications.”

Samsung's new Android-based Galaxy tablet.

Design challenges and opportunities
The challenge for chip companies working in these transitional technology markets is figuring out where the volume adoption will be, how to best utilize the technology to serve multiple markets, and how to add in enough flexibility so that certain features can be given priority where necessary.

In some cases this may utilize a system-in-package approach with an interposer technology or a network-on-chip architecture for improving signal traffic flow. In some cases it may be multiple cores within a complex SoC that serve the same purpose. And in the future, it will likely be multiple chips on a 3D stack, where different functions can be developed and then manufactured as needed for different markets.

What will have to change, however, will be the pace of tool adoption and development. One of the big complaints among system-level tools vendors is that not everything can be integrated into a flow because high-level tools don’t necessarily work perfectly with older tools that utilize lower levels of abstraction. That has stymied the growth of high-level synthesis and software prototyping, for example.

But these kind of changes may bring new players into the market, raising the competitive stakes to develop chips more quickly, more efficiently and with more flexibility. That means newer tools will be required, and it can quickly force a competitive upgrade among existing companies and spur growth in areas that have been slow to develop, particularly in the ESL space.

Conclusions
So what will be the most important features on a phone in the future? That will depend to a large extent on the applications and what’s important to users and companies that buy these devices. A phone will still have to be able to make phone calls, but that may be just a lesser feature on these increasingly complex devices.

“A phone will have to be reliable and clear,” said Koeter. “But once it meets that standard, then it’s all about a whole new experience.”