By Ed Sperling
Mentor’s Robin Bornoff does what any good engineer would do when the corporate beer fridge goes on the fritz. He figures out not only how to de-fritz it, but to improve it. But there are two things that stand out as suspicious here. First, non-Brits always assumed British beer is best served at room temperature, so why is the beer in a refrigerator in the first place? And second, it’s rather odd that no one has ever drunk it considering the British reputation for beer. We’re waiting for the WikiLeak.

Cadence’s Jack Erickson is in a self-described evolution mode. Even his wife has commented on it (his words, not ours). Finally, a family member who recognizes the importance of what we do in this industry. This may be real evolution.

Mentor’s Colin Walls pulls out the crystal ball from the closet and lays bare four consistent themes surrounding Android, multiple cores, power consumption and the growing functionality of graphical displays. The future is upon us.

ARM’s Ed Plowman expounds on when a pixel is not a pixel. This sounds like a magic trick. Now you see it, now you don’t.

Speaking of ARM, Daniel Nenni takes a look at Intel vs. ARM, and concludes the really interesting development is Linaro—an open source initiative that includes IBM, Samsung, TI, Freescale, ST-Ericsson. So far it only supports ARM processors, but given the amount of business these companies conduct with Intel don’t count on it to stay that way.

Si2′s Steve Schulz looks at how standards will support the industry’s five-year challenges in the first of what what promises to be many parts. Where were you five years ago?

Cadence’s Richard Goering reports on a presentation by STMicroelectronics’ Romain Feuillette about using the SKILL language to code parameterized cells. Hearing what companies like ST are doing in the real world is always interesting, and this one is very good.

Doulos’ John Aynsley, writing in Synopsys’ VMM Central, digs into transaction-level communication in VMM and which options are best. If you’re involved in verification, particularly on the VMM side, this is required reading.

By Ann Steffora Mutschler
With the typical cost of software accounting for 40% to 60% of an SoC, semiconductor OEMs are under more pressure than ever to meet margins. As a result, they are drawing on their ecosystem partners to provide a more complete foundation including hardware, software, FPGA prototypes, verification IP and virtual models, as well as an increasing demand for open source software support for their SoCs.

To be sure, software acquired through an open source model can allow faster time to market by leveraging publicly available technology. But the biggest limitation is lack of support, unless the software comes from a commercial provider.

How does this play outside in the hardware world? “Software is something you can change relatively easily, whereas hardware IP, once it’s in silicon you’re stuck with it,” said Simon Davidmann, president and CEO of Imperas and founding director of Open Virtual Platforms (OVP). “Another big difference between hardware and software is that there are very few people designing hardware compared to people writing software. If there are 100,000 apps for an iPhone then there must be 300,000 or 400,000 people trying to write them. In the hardware world, there are only about 100,000 hardware engineers globally, and yet there are many times that just developing software for the iPhone.”

Clearly, then, the software scale is completely different from the hardware scale, and this has an important effect on open-source ideas.

“With the GNU tools they can apply to tens of thousands of people easily, but in the EDA world that’s not really the case,” said Davidmann. “The closer you get to the hardware, the less appropriate an open source community is. Open source is good from a, ‘Let’s have a compiler that you can use for free,’ but no user fiddles with the open source bits of GCC (GNU Compiler Collection) or GDB (GNU Project Debugger) that doesn’t fiddle with Linux. It’s very useful for the hardware guy to make use of, but then they tend to have to pay people to do it.”

Where it works best
One of the biggest challenges companies face in implementing a design is in the verification phase, which is why it consumes the largest chunk of the non-recurring engineering expenses in any design. Prasad Subramaniam, vice president of eSilicon’s design technology, said this is exactly where open source can help.

First, open source software could be of help in the actual verification of the IP that is being stitched together as part of the SoC, especially for IP that is standards-based like a USB interface or a PCI Express interfac. “Because it is in the public domain, you can develop verification IP in an open source manner. That’s one of the advantages. People who do verification today license this kind of IP from various IP providers, and it will be significantly helpful for them if such verification IP is available in the open-source model as it will make it easier to access, allow them to do what-if analysis, experiments and so on before they go on and purchase something that is industrial class,” Subramaniam said.

Second, open source software support can be helpful in system-level verification. “Once you have designed your SoC, you want to try and run system-level testbenches, for example. If you build an ARM-based subsystem, you want to try and emulate it in an FPGA type of environment. You can get a board that contains an ARM chip with an FPGA and you can implement your logic, and this has an interface to your PC and you can control the software from your PC but the actual software will be running on the ARM test board and the FPGA,” Subramaniam said.

Similarly, John Koeter, vice president of marketing for Synopsys’ IP and Systems Division, said the use of virtual prototyping at the system level has allowed a fair share of the top 10 global semiconductor companies to pull the time to ramp into production by as much as six months earlier than with older approaches.

“Today many companies still use what I call a waterfall model where they develop the hardware, they get to the golden RTL or even the chip and then that’s when they’ll start developing the software on the physical prototype itself or maybe on an FPGA-based prototype of the chip,” he said. “That process is done in a serial or waterfall manner, and obviously that pushes out the entire development schedule significantly. We are really working with the semiconductor companies to pull in the start of the software design much earlier using virtual prototyping. In a fast moving market, ramping to silicon six months or even three months your competition easily yields 10% to 15% revenue through additional early wins.”

Models Are Key
The key to virtual prototyping involves the models, and while not disclosing any plans, Koeter noted that Synopsys intends to enable a significant effort within the open source community for creating models. He said plans are in development. Also, with its recent acquisition of Virage Logic, Synopsys gained the ARC cores, and is fully supporting the various software stacks that run on an ARC core, including variants of Linux, etc.

On the surface, it appears that Synopsys may be finding out what Imperas did, namely that people want control over the simulation models. They didn’t want to get into the insides of the simulator. But they do want a commercial company to professionally service and support the tools, and they want control over the IP and the models, Davidmann said. “The great thing about open source is that it allows you to see what’s going on, modify it and use it, and then that way it gives you freedom and can take things further.”

Imperas has a closed-source commercial simulator and open-source models (developed from published documentation and in such a way that the user can extend them). “This is very different from the SystemC approach of an open-source simulator—developed and funded by the big EDA companies, but which isn’t really open because you have to be part of their club and paying to be able to enhance it and redistribute it,” he said. “What this means is that it is about three or four years old. It’s a commercial ploy in that Cadence, Mentor, Synopsys have their own tools and simulators that use SystemC as proprietary professional solutions and the OSCI simulator is the poor cousin so it is several versions of a standard behind.”

Imperas also uses an Apache License, which Davidmann noted is good for commercial organizations and does not have the same requirements as the GNU license.

“For a silicon vendor that makes them very nervous. If [they] download a bit of IP and put it in [their] chip, the rules aren’t very clear yet because open source is all about software, it’s not really about hardware. Hardware tends to be covered by patents and software by copyright. In software if you use a GNU public license, if you link it to any other pieces of software, all of that software has to be covered by it so it really promotes the spirit of ‘free to use.’ You are allowed to access the source, and if you use it you’ve got to make your source available so it furthers the usage of it. Whereas in a commercial organization, there’s no way you would want to include a piece of hardware on your chip if you had to give away your hardware design. You want to protect that and hide it because it’s all your tricks and magic. In the hardware world people are much more nervous about the licensing of open source.” Davidmann said.

A new approach to open source for ARM-based SoCs
There is another approach that ARM, IBM, TI, Samsung, ST-Ericsson and Freescale have come together on to address OEMs that demand the best open source support. “They want the latest kernels, they want the latest tools, they’ve got to be stable. It’s more than just throwing them a BSP and hoping it is good enough. They want more than that, and that’s what Linaro was born to do,” to make it easier for ARM partners to deploy the latest, optimized technology into Linux based products, explained Rob Combs, head of global alliances at Linaro, a not-for-profit open-source software engineering company that launched in June.

Linaro stemmed from conversations with OEMs about the difficulties of developing open source—the need for great tools, the latest kernel, not having to rewrite BSPs from silicon partners, he said. “They want more of that support in the upstream trunk rather than less and they want more investment so we can fix any problems that crop up. That’s more than any one company can deliver individually. There needed to be a collaboration vehicle to deliver this for the ARM partnership. Linaro was born to make it easier and quicker to develop complex open source products based on these new whizzy SoCs that are coming out.”

Linaro does essential engineering relevant to multiple verticals markets and to multiple distributions. At the application framework level, the organization aims to helps distribution creators get a better base to start from, which is enabled on multiple ARM platforms for more commonality, and less fragmentation. In terms of development tools, Linaro believes it can provide better tools to build optimal software, which is are used at all levels of the OS, and which is crucial to achieving the best PPA. All of this is part of the move toward a common kernel and is enabled on multiple silicon platforms, Linaro said.

In the process of ramping from 20 to 80 engineers, the organization will deliver every six months a harvest of all of the latest, freshest code, Combs said. Linaro’s next step is to show proof points at upcoming Linux conferences.

By David Lammers
Multicore processors are being readied for embedded applications but software developers will need to get prepared if they expect to wring the maximum benefits from them.

Rob Oshana, director of software R&D at Freescale Semiconductor’s networking and multimedia group, said software developers increasingly are asking if their code will easily port to multicore CPUs. “We as an industry are coming out of the trough of disillusionment after a period of hype” regarding multicore solutions, Oshana said at the Real-time and Embedded Computer Conference in Austin, Texas. “While many development teams have learned how to code heterogeneous multicore SoCs—most often a DSP and ARM combination—relatively few have braved the homogenous multicore and many-core products, which are expected to have from 8 to 32 cores on board eventually.

These multi-core platforms offer real cost advantages, providing the programming challenges can be met. “How to get the maximum performance out of multicore devices is challenging, and varies by application,” he said. Some applications can be met by symmetric solutions, in which a single operating system is implemented on multiple cores. But often, asymmetric solutions are required, in which a Linux OS is used on the cores dedicated to control functions, while a real-time operating system (RTOS) or library executes on other cores. Many customers seek to run a legacy operating system, such as VxWorks, on one or more cores—all without an onerous porting overhead.

“These days, the operating system really is the platform” that programmers target, Oshana said in the keynote speech. While the backend tools are fairly good now, developers need better tools to divide up tasks on the different cores. And while the Multicore Association is working the problem, Oshana said standardization is needed for creation of the virtualization layers that sits inside the operating system. “We are trying to catch up” with the standards needed to manage partitioning of a system, including the partitioning rules.

Debug, needless to say, is a major challenge with multicore CPUs. “We can put a debugger on a core, but that doesn’t look at the code from a system perspective. Multicore requires tools that can do system-level visualization. It is worth the effort, as these multicore processors can really reduce costs,” said Oshana, who joined Freescale several years ago after working at Texas Instruments.

About 100 software engineers attended the one-day conference and exhibition, where 31 companies presented their software tools.

By Ed Sperling
Mentor’s Colin Walls looks at the uses of asymmetric vs. symmetric multiprocessing and where each gets the most traction. Better get used to this stuff. If chip design goes 3D there’s going to be a lot of the asymmetric stuff to contend with.

Synopsys’ Karen Bartleson has a schedule of old media, new media and non-media speakers to be held at Conversation Central at DAC, and posted forever afterward. And just in case you’ve missed that, check out Rick Jamison’s blog. He has a copy of the same schedule attached to his blog.

So whom can you believe? Old media? New media? Non-media? Cadence’s Tom Anderson takes a stab at that question and what makes a professional blogger…well…professional. There’s no clear answer, but a lot of people get quite emotional over this subject. It’s sort of like talking about politics or religion at Thanksgiving dinner. More turkey, anyone?

Daniel Nenni sheds light on TSMC’s new analog/mixed signal flow, version 1.0. You’ve got to start somewhere, but most software companies now start products at version 3.0 so it doesn’t look like it’s the first version. Apparently that logic doesn’t apply in foundry reference flows. Still, this is a big step in the right direction.

Rumors are flying that Synopsys is on the hunt for more acquisitions. You don’t have to go very far to confirm that, of course. Ask any top exec at Synopsys and they’ll gladly offer up that acquisitions are part of the growth strategy. Scratch the surface a little deeper and you find the company has $1.08 billion in cash. Which begs the question, who’s on the short list? John Cooley’s DeepChip offers some ideas.

If you’re looking for a succinct definition of clock-gating retention latches, check out the entry from Synopsys’ Godwin Maben.

What’s behind Lenaro, the open-source consortium of companies that includes ARM, TI, Freescale, ST-Ericsson and IBM? ARM’s Kerry McGuire takes a look under the covers.

Mentor’s Ping Yeung is bucking the trend on static verification. He’s a fan.

Finally, Si2’s Steve Schulz reveals what the group is doing at DAC next week. It’s a serious effort to add standardization into semiconductor engineering, but the location may cast a different tone on the overall proceedings. Anaheim is the only city that can give a different meaning to “Mickey Mouse design.”

By Ed Sperling
System-Level Design sat down with Glen Daves, director for packaging solutions development at Freescale Semiconductor; Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics, Rajiv Maheshwary, senior director of customer marketing at Synopsys and head of the company’s 3D initiative; Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion.

SLD: What are the advantages of 3D, both from a business and technology standpoint?
DeLaCruz: There are two sides of the spectrum. On one side are cell phones, where you have very limited area. On the other side there are pizza-box boards. Both of these can save on space and increase performance. But once you start going 3D your main avenue for getting the heat out disappears.
Daves: You do it because it allows you to create cool stuff. That stuff is differentiating, either from a miniaturization standpoint because you can reduce the size of the chip or the board, or from performance. Eventually there is a promise of cost savings, but that’s not the initial driver. In the emerging technology where you build the package around the chip, you’re saving on laminates. And if you have multi-chip integration, you’re saving there, too. But if you’re moving to the lunatic fringe of TSVs, cost is not the goal. It’s performance or integration.
Maheshwary: From a mass-market adoption point of view, the only limiter is cost. That’s why people do die size reduction, and it’s why people are looking at what kinds of technology can be used. ‘Via last’ is cheaper to assemble, there are much larger pitches for vias, and you can assemble these chips and get a good cost saving. Where EDA will play is in the tools around heterogeneous devices. The big driver there will be performance. Performance and power go together. There are stacked devices, or stacked devices with interposers, or side-by-side devices. What gets used depends on the application. One other dynamic is that for some of the consumer applications the desire is to get a more PCB-driven flow where the form factors are determined from the outset. It becomes an I/O optimization problem. It’s a PCB form factor driving a package pin-out driving the chip. That’s where some of our customers are trying to take us.
Robertson: There is significant appeal on the design side. We’ll truly expand what we’re doing in re-use, which gets back to the cost issue. Do designers really want to re-design their analog block that works fine at 65nm, and have to do it over again at 40nm and 28nm, when the only reason is to be able to fit on a 28nm die? It’s very painful to do that. To be able to design at the node that makes the most sense for that particular block is good for designers. Then they can use it in different applications and not have to do so much porting. But the economics have to make sense, too. There are a significant number of technical hurdles and the ROI needs to be resolved.

SLD: Where are we now in the process? There was a mention of 2D, 2.5D and 3D.
Maheshwary: There is a set of tools now moving from 2D to 2.5D. You can do stack extraction and verification working with known good dies. You may not be able to do all the floor planning and have all the capabilities for partitioning, but that’s 2.5D. When you get to the point where you can move logic from chip A to chip B, that’s truly 3D. Time will tell whether that will happen. There are lots of unknowns. Partitioning logic between chips is 3D.
Daves: There’s already horizontal integration, which has been around for 30 or 40 years, where you have two die side by side in a package. There are various forms of 3D integration for shrinking the die size. But 2.5D in the physical sense might be an interposer with horizontal die on both sides. You can imagine chip stacks growing from there.
Maheshwary: Interposers are a good example. Companies are using via-last. You have the logic through a TSV and the glass substrate. When you start putting USB on that it will be 3D, and that will happen in the next year.

SLD: When we go to 3D do we have more derivative chips or fewer?
DeLaCruz: You certainly have more opportunities for derivatives because you’re able to use the chips that already exist and you don’t have to worry about different chips with the same technologies. You already have one that works well, and you can stay at 130nm. A lot of the package-in-package and system-in-package are based on the ability to use an older chip that had a pin-out made a certain way. It’s just realigning your bond pads so it will work with the next-generation chip, even though that same chip on the inside is identical.
Daves: The promise of in-pad integration, whether or not that’s 3D, is big. Multi-die integration in package probably results in fewer silicon derivatives, but more product derivatives. You can re-use the same chip in many products.

SLD: What happens on the total cost of a chip? Does it stay the same, go up, or even go down?
DeLaCruz: If you’re able to shrink the die and use some of the older technology for a controller chip, for example, and only use the high-end of an existing chip, you shrink your cost. If you only use the advanced node for certain things, you can drop the cost. One of the difficulties, though, is there are so many flavors of integration. TSVs will drive up the initial cost. If you have examples of a newer die with an older ASIC, you have significant opportunity for cost savings.
Maheshwary: We’ve seen that. One of our customers had a set-top box with analog IP at an older technology and PHYs and a silicon interposer with the logic of the newer technology. Their cost was the same as doing a new SoC. What they expected, though, was that with the time-to-market gain it would provide huge cost savings for additional products.

SLD: Does this make node skipping easier?
Robertson: There is always a demand for new technology.
Maheshwary: The reason to move down the Moore’s Law curve if you have a 3D TSV is less and people will stay with the older nodes. There will be certain applications—processors, leading FPGAs and memory—where it makes sense to go to the next node. But it’s also very costly to get to 16nm. Stacking is an alternative. There will be a mix of customers. The mainstream will take advantage of the older nodes if this works out.
Robertson: It will be easier to move to new nodes. Some of our mixed signal customers, as they move to the newest nodes that have been pioneered by the memories and FPGAs and microprocessors, they’ve only implemented a third or a quarter of the devices those mixed signal customers want to implement. While that node may be somewhat stable, the analog guys now need to come in and qualify new inductors and three to four times the devices. They may not need that technology for the analog parts. They need that technology for the memory portions or logic portions of the design.
DeLaCruz: Something that may seem counterintuitive is that when heat builds up in 2D devices it’s a very concentrated area and it’s difficult to get the heat out. In an older node chip you have a huge technological advantage for lowering heat. In a package the best thermal conductor is the silicon. It has a huge first-order effect on how you can dissipate that heat, so using an older node as an integration layer can be a huge competitive advantage.

SLD: What happens to the software stack in a 3D chip? Does it become harder to develop?
Maheshwary: It’s a good question but we don’t know the answer.
Robertson: It’s too early to answer that. We have not done enough on the implementation side to know.

By Ed Sperling
System-Level Design sat down with Glen Daves, director for packaging solutions development at Freescale Semiconductor; Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics, Rajiv Maheshwary, senior director of customer marketing at Synopsys and head of the company’s 3D initiative; Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion.

SLD: Given all the considerations in SoC design today—thermal issues, placement, routing, power—does that all get in the way of how you manage the flow in 3D?
Robertson: Yes and no. It’s easier to look at the design intent and what needs to be addressed in a flow rather than allowing all degrees of freedom and architecting tools to respond to a particular scenario. You’ve got to prioritize. Here is a particular problem we’re going to solve with TSV implementations. Maybe it’s thermal, maybe it’s something else. If we narrow the focus, we can do a good job. This lends itself to a best practices approach. For example, ‘Here’s what TSV is going to address.’
Daves: A lot of the leaders in this technology—those who are the farthest ahead—are holding their cards close to their chest. There are applications out there where people know the first step and the second step, but no one is talking about it until it comes to market. That places the EDA community at a disadvantage.
Maheshwary: It’s both yes and no. Yes, because this is an emerging area and so much is in flux. And no when we look at some of these initial applications. We have one customer that has all these memories in a stack and all these TSVs in the middle of the die. They’ve got 500 TSVs in the middle of the die, but you can’t route metal 2, metal 3 or metal 4 on it. Is this a product application? No, it’s a test chip. Three months later, they say they can use level 3. All of this has to be done in collaboration with a customer. You have to work the design methodology accordingly. We need insights into these things, and restrictive designs will come into play. Foundries will emphasize it. We will need rules and over time we can relax the rules because of all the unknowns.
DeLaCruz: You have the luxury of waiting until customers develop the specific application only if you can react very quickly. If you can’t react quickly, you have to predict what will be done and put those tools out there. If the tools and teams are in place, then you could wait until you have specific examples. The applications for TSVs are very diverse. There are fingerprint sensors where you need to interface with the silicon. On the face of the CMOS you also need an interconnect, so you can avoid having an air cavity. You put the glass lens directly on the surface of the silicon. A lot of these developers need to make sure they have an infrastructure in place. The cost is unknown. And there are a lot of reliability issues. But if we’re going to wait for one or two customers to drive this, it’s not going to happen.
Maheshwary: I agree that we shouldn’t wait. But we all do need to partner to get clarity in terms of what it is we’re trying to build. If you look at the EDA community it’s now via middle, not via early or via last. It’s die-to-wafer bonding. That’s great. But you’ve got to define these things in terms of a pragmatic approach. Then you say, ‘What’s the methodology to make this work?’

SLD: At advanced nodes, the bulk of the cost is in the verification. Does that change with 3D? And does it move from a linear to a concurrent flow where multiple things have to be done at once?
Robertson: As much as possible, we’re trying to fit into the paradigm that exists today in terms of bottom-up as you build up these components. But there also is back-and-forth between the various dies and how they behave in silicon. I don’t know if it’s going to change the cost structure. But in terms of how customers respond to this, it is going to change their methodologies and their methodologies for modeling, as well as how they go back in to fix certain parts of the design that aren’t performing as well as they expect. There are well-established methodologies for fixing things now. Fixing things in a multi-die infrastructure is going to be very problematic and quite a big challenge. I think methodologies will have to change.
Maheshwary: If you put the boundary conditions on what you are trying to build, there will be some tasks that will be done in parallel. You can do LVS or timing models of stacked die. Test is an interesting area. You will probably do intra-die testing, and then testing between die using JTAG or whatever standard evolves. This is an evolutionary change for EDA. When you’re looking at a heterogeneous device that includes logic and memory or logic and analog, when you have logic on logic and you’re moving structures from this die to this die—that’s the real power of 3D, but it’s going to take some rethinking about what we do and the tools we use. I see that happening five years from now.
DeLaCruz: If you’re designing an ASIC that’s going to be used for a high level of integration, it would be crazy to have all of your test pins come out of each die and go into the package. Test compression on one ASIC is going to drive the test for all the other devices. It can test all the connectivity for all the other chips and send out a ‘pass’ or ‘no pass.’ To have a die in isolation wouldn’t work.

SLD: Does bulk CMOS and existing packaging work?
Daves: Most of the effort today revolves around using standard CMOS processes to deliver the TSV. That’s going to prove to be a solvable problem. On the packaging front, assembly is a challenge. As the I/O pitch goes down, it gets more challenging. But wafer-to-wafer is going to end up being a small number of applications. As we move to die to wafer, it’s hard to envision putting too many chips in the die-to-wafer configuration unless the sizes work out just right. So I think we’re looking at die-to-die. There’s certainly a lot of work on all three of those. I think we’ll be in the realm of standard packaging materials. The challenge is assembly.
DeLaCruz: I agree. Even though you do all this integration, the main ASIC will be a typical device and that will use more traditional technology. That ASIC will have TSVs connecting to the next device. There are a lot of other 3D formats that are not TSVs where you build a package right on the die rather than putting the die in a package. That is an emerging technology. There you will have some very advanced 2D integration.

System-Level Design sat down with Glen Daves, director for packaging solutions development at Freescale Semiconductor; Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics, Rajiv Maheshwary, senior director of customer marketing at Synopsys and head of the company’s 3D initiative; Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion.

SLD: Is 3D really going to happen?
Robertson: Based on what our customers are saying, it definitely is real. It’s applicable to certain designs such as memory already. And we’re starting to create multiple cores with memories on top. That’s driving a lot of tools effort. We’re definitely seeing the investment. We’re not ready to predict it will be ubiquitous, but it’s beyond test-development.
Maheshwary: It is real, but it’s going to take some time. We are hearing three major reasons why people are looking at 3D, and there is proof in each in terms of demonstrator chips. The first reason is form factor, and the proof there is CMOS image sensors, which have been in production since 2009. Along the same lines, people are looking at the tradeoffs in memory stacking. That will go into production late this year. The second reason is heterogeneous integration. That’s performance-and power-driven. Memory bandwidth is a big issue, especially with logic and multicore processors. The timeline for that is probably around 2012. The third reason is that customers are experimenting with the IP, time-to-market and cost of mixed-signal SoCs. If you can separate the analog functionality and move it to another chip, so you can have the analog functionality at 130nm and a digital chip at 65nm or 45nm, then you can get an advantage in time to market.
Daves: The key question is what kind of 3D we’re talking about. Chip stacks are already in production, and we’re seeing dual-sided packages, mostly driven by miniaturization. But as we move into 3D with TSVs (through-silicon vias), it’s all about performance. You can build a device with TSV technology you can’t build any other way. For massive bandwidth, how do you get 10,000 or 100,000 connections between two chips? And there are certain high-speed applications where TSV technology is a real enabler. The technology is real and we’re absolutely pursuing it.
DeLaCruz: Companies need some form of differentiation for their products. That can come down to cost, miniaturization, speed, performance, or a number of things, and 3D is one avenue to get down to that path. Wire-bonded 3D has been around for years, and it has primarily been driven by space. Up until about a year ago, it was more expensive to put two die in one package than to package them separately and put them on the same board. Once we crossed that point, assuming you’re in the same technology it now makes sense.

SLD: What’s the technical hurdle we have to solve?
DeLaCruz: In stacking wire-bond die, it’s pretty straightforward. You use the same architecture. You have buffers on the edge of your die, wires bonding to each other, and it works well. TSVs are completely different. There are a lot of advantages of using two die next to each other, but there’s no reason to drive memory from one die to another using 1.8 volts or 2.5 volts. There is very little resistance, much lower parasitics to running them off the same core voltage. The IP doesn’t exist. If we were able to do that, we would be able to get to very low power. You don’t need all that voltage to drive a chip.
Maheshwary: There are some business issues and there are some technical issues. From the business side, it’s a bit of a mess. People have so many choices and flavors. We need to be quite pragmatic about what really works. Over the last year we’ve been researching this and injecting some sanity into it. There were all the fab flavors—via early, via middle, via last. There also were all the bound-up flavors of chip to chip, die to wafer and wafer to wafer. The number of choices we’ve given engineers is enormous. We’ve got to be more pragmatic in terms of what it is that you really want to build. That’s why larger companies, which have proven this technology—companies like IBM and Intel—don’t have the right applications to launch it. There are technical challenges, as well. If you look the reliability and the stress analysis of TSVs, we don’t have a lot of data. What are the rules when you have a TSV vs. an active device? Can you keep it within 5 microns? Can you keep it within 20 microns? How is it going to impact the device performance. We are doing a lot of research in that area. Another issue is around test. What test do you use? Do you use JTAG for die level or package level? What about stack testing?
Robertson: It’s a question of, ‘Can we collect industry best practices?’ There are different technologies on the manufacturing side with different via technologies. There are also different design methodologies. Are we going to put memories above cores and strictly look at the design techniques, putting analog in one place and digital in another? That makes it nice to partition the design, but then there are others who want to do path analysis across these dies. Are there portions of functionality now spanning multiple dies? There are specific design methodology issues. And if we’re talking about TSVs, we’ve been wrestling with stress on the silicon for several generations now. These TSVs use thinner wafers, so the stress for individual MOSFETS is different. We also have to think about thermal and how we’re going to dissipate heat now that we’ve stacked up all these chips. And for many designers, these TSV components are inductive. They’re going to have a profound effect on the magnetic fields within a die and surrounding die. Not many designers are considering inductive effects even within their own chip. Now we have the potential for noise issues between chips. There are significant modeling challenges ahead.
Daves: There’s also ESD (electrostatic discharge association) protection. When you have a bunch of I/Os and TSVs, there isn’t enough space to put ESD protection on every I/O. The other challenge is that in the design realm, when you have a circuit that is cutting across pieces of silicon—and a 3D circuit is really the end goal—we have a long way to go before we have tools that can support that structure and lay it out.

SLD: One of the big advantages of 3D stacking is the ability to run different technologies on a chip. Sometimes it involves different voltages, sometimes it’s completely different protocols. How do you solve the integration?
DeLaCruz: Years ago you could design your die with complete isolation from downstream processes. As you get to higher levels of integration, especially when you have multiple chips, you have to design from the system down to your chip. That could be a backward flow. Knowing what you need to connect to, at what speed, and then even before you do floor planning for the chips, how they are going to connect to each other are critical. Right now memory is cheap, but they’re bonded along the middle of the die because that’s how they’re packaged. To put them in another device you will either need extremely long wire bonds, which causes cross-talk, or you will have to put them side by side and the pads will need to match from the very beginning. You really can’t design these die in isolation. If you’re doing die-to-die connections with TSVs, you need a physical design tool to do that and you add a lot of your own customization. But if the connection requires some assembly—putting two die on opposite sides of the package, then it becomes the packaging tool’s responsibility. A lot of these EDA tools still have the old mentality of, ‘It’s a die problem, it’s a package problem, or it’s a board-level problem.’ This is a problem that includes all of them.
Daves: There are many applications shipping today with integration of dissimilar technologies in a single package. At Freescale we make tire-pressure monitor sensors. There’s an analog chip, an RF chip, a pressure sensor and a microcontroller. Those are four completely different technologies in a single package. Depending on the level of integration and the complexity of the problem, integrating dissimilar technologies isn’t necessarily a giant challenge. Today, there’s the traditional wire-bond integration. We’re seeing TSVs in simpler applications. We’re also seeing embedded chip packages where you can embed multiple die into a matrix and then connect them using more traditional chip back-end technologies. Then we see, on the horizon, this full-blown 3D chip with massive integration. The design tools are important, but I don’t think integration of dissimilar dies is the hardest part.
Maheshwary: EDA is the third problem to be solved. If you look the fabless market, the issue’s they’re looking at are whether the foundry is ready, what’s the right product, what’s the right cost? Is it cheaper to do a wire-bond design? What is the right application? IDMs do the entire chip, including packaging. They look at the cost and whether they have the yield and test issues solved. After that, it’s EDA. So EDA does need work, but we need to be extremely pragmatic about what we’re going to do. You have to use known, good die and solve problems based on them. If you’re going to do back-side routing, who’s going to do it and what’s it going to cost? Robertson: When it comes to integration, the tools aren’t going to solve the problem. Designers are integrating various pieces of IP across multiple power domains today. We validate, verify, analyze and simulate the analog vs. the digital block differently. As we go to verification of different IP across different die, there’s going to be an extension. But it’s going to be in response to what problem we’re trying to solve. Is it an integration problem, a data problem, or are we trying to do critical patch analysis across multiple die. The tools will respond, but it’s up to the customers as to which problems they want to solve first.

By Ed Sperling

The acquisitions continue. Mentor Graphics acquired Freescale‘s Virtual Garage optimization and analysis technology, expanding its reach into automotive electronic design. Consider this an interesting way for Mentor to leverage its design expertise in adjacent markets.

Synopsys reported revenue of $330.2 million in fiscal Q1, down about $9.6 million from the same quarter in 2009. Profit was $132.8 million, but that included an extraordinary one-time gain of $91.6 million from a tax settlement with the IRS. Still, the company surpassed analyst expectations, and numbers are expected to be as good or better in the current fiscal Q2.

Mentor announced it was making its embedded Inflexion user interface available for the Android mobile platform using TI’s OMAP environment. Mentor made the announcement at Mobile World Congress in Barcelona, Spain.

Virage Logic teamed up with Open-Silicon to create an ultra low-power design that combines Virage’s low-power memories with Open-Silicon’s back-biasing technology.

Arasan signed onto Atrenta’s clean IP program, aka SpyLinks, which is yet another link in the chain of providing IP that actually works. This has become critical ever since the major foundries, TSMC and the Common Platform group began rating IP to make sure it works and can be manufactured.

By Ed Sperling

Every now and then a new trend comes along in the semiconductor design world, often because an old tool doesn’t work well anymore or because a new one is achieving critical mass. Lithography moved to immersion when the wavelength couldn’t be refracted far enough anymore. Designers at the advanced end of Moore’s Law began using tools like high-level synthesis and Transaction-Level Modeling 2.0 to help sort out the complexities of multicore, multi-voltage, multi-power island designs.

What’s changing at 32nm and beyond is the number of different directions the industry is heading. In the past, each new node brought new changes. At 130nm, the changes were considered extremely difficult because manufacturing moved from 200mm to 300mm wafers, added copper interconnects and low-k dielectrics for insulation. Most developers and chipmakers heaved a sigh of relief when that transition was over. But in retrospect, that was relatively tame.

Interviews with dozens of engineers, vendors, scientists, researchers and business managers over the past six months show that what’s ahead cannot be bounded into just one or two shifts. The change under way now is geographically global. It’s moving to a higher and higher level of abstraction, from semiconductor to system to device. And it is as much driven by business as technology. Moreover, taken in total these changes will completely alter the basic fabric of the design community in ways that have never been seen before.

Business
Behind many of the changes afoot in the market there is always a business case. In the past, technology trumped business. Those with steely nerve and enough backing could often carve out a space for themselves in markets, and even if they weren’t entirely successful they could minimize their losses.

Three things changed over the past decade to alter this approach. Business now trumps technology in almost all cases. First, the venture community has grown more cautious about the rate of return in hardware and EDA tools ever since the dot-com bubble burst in 2001. It’s not possible to return to the tap anymore without a real product and a real business model.

Second, the cost of failure has gone up. It now costs $4 billion to $5 billion to build a state-of-the-art fab. Consortiums of very large companies and governments are now involved in this business. And it can cost upwards of $100 million to build a very complex SoC at the latest process node. Stalwart adherents to Moore’s Law such as Freescale, which made the leap to the next process node without hesitation until 90nm, have begun skipping nodes on certain products.

Third, chips are now so complicated that it takes too long to build everything from scratch. That means chipmakers must buy IP from third parties. Even Intel doesn’t make everything itself anymore. And all but a very few companies now use a fabless or fab-lite model for at least the digital portion of their chips, which forces them to adhere to design rules and process technology developed by the foundries.

Put these together and the result is that business issues are forcing a handoff of some of the most basic parts of semiconductor engineering—defining a unique architecture, tinkering with the layout, refining the process, and balancing all of these pieces together at tape-out. Fast yield, time to market and standardized interconnects and IP are no longer just goals. They are requirements. Some companies have handed off the building of chips entirely to a new class of value-chain producers like eSilicon, Global Unichip and Open-Silicon.

Globalization
For the first 50 years of its existence, the semiconductor industry defined global as North America, Europe and Japan. Taiwan was a latecomer to the part, and TSMC’s vision of a foundry model was considered revolutionary well into the 1990s. Companies like Texas Instruments and AMD said they had no intention of letting go of their own fabs.

Fast forward through two downturns and 10 process nodes and the situation now looks much different. Software is increasingly a part of the design process, heavily automated foundries can be located anywhere in the world where tax breaks and the cost of power are lowest, and massive education programs are under way in multiple countries that see semiconductor and computer engineering as a fast way to economic health.

While many lament that the semiconductor industry is declining or not showing growth, the opposite is happening. It’s expanding significantly. In 1977, the Semiconductor Industry Association reported total semiconductor sales of $2.88 billion, with about $1.92 billion of that in the Americas and only $182 million in Asia/Pacific (not including Japan). In the first 11 months of 2009, sales were $196 billion worldwide, with $102 billion in Asia/Pacific and $33 billion in the Americas.

By any standard this represents an enormous increase in sales, but the profits are now far more dispersed around the globe. Moreover, IP for chips is being developed in places like Eastern Europe and former Soviet republics, and in the future that kind of work will accelerate in other parts of the world because the barrier to entry into this market is one of the lowest—you don’t need to build full systems—while the return on investment is one of the highest. Virage Logic, ARM and Synopsys have been snapping up these kinds of operations around the globe over the past couple years.

Technology
Most of these changes are being driven by the technology itself. There are fewer design starts for ASICs these days, but the problems being solved are far more numerous on each chip than in the past. The tradeoffs of area, power and performance have been relatively balanced over decades of development. When lithography became an issue, there was enough slack in power and performance to tide chip designers over until the next node.

At 90nm that began to change. Classical scaling ended, lithography stalled at 193nm, defect density increased as irregularities in silicon and process technology became evident. Power forced even companies like Intel to begin adding more cores onto a chip rather than continuing to turn up the clock speed, creating problems about what to do with more and more cores.

At 22/20 nm—the next node for companies that live on the edge of Moore’s Law—things get even more interesting. Both Synopsys and Mentor Graphics predict that FinFETS will start showing up on chips—3D transistor structures that will wreak havoc on parasitic extraction because of the amount of data that will now need to be analyzed and synthesized. IBM has talked about potentially reducing the functionality on chips at future nodes to be able to get chips out the door that fit into the power budget.

All major chip companies are now looking at heterogeneous cores instead of homogeneous cores and matching software and core size for a specific function. IBM and Mentor are experimenting with computational scaling to compensate for the limits of 193nm lithography. And power techniques that used to be considered exotic and extraneous are suddenly becoming necessary.

Even substrates are changing. Intel, which examined and then rejected partially depleted silicon on insulator (SOI) is looking seriously at fully depleted SOI for future nodes. And work is under way to sidestep much of this entirely with 3D stacking of chips, which have many problems such as heat dissipation and parasitic issues still not fully understood.

Abstraction
Perhaps even more daunting in this whole process is a complete shift in control within the design flow. The number of computations necessary at advanced nodes, coupled with business pressures and time to market issues are forcing engineers to rely on models. For many, this is like black-box technology. You put requirements in one side and the software adds a lot of the things in between.

For engineers who learned to solve problems the hard way–that is, without software models–this is perhaps the toughest change of all. RTL engineers who work at big chipmakers say there is enough work at the moment to stick with their core competencies. The problem is the amount of data they are dealing with is going up, and over the next few years it will skyrocket into the stratosphere.

Japan has been particularly accepting of tools like TLM 2.0, high-level synthesis from companies like Mentor, Forte Design Systems and Synopsys, and network-on-chip technology from companies like Arteris and Sonics. The acceptance level in Europe is lower, and it has been lower still in North America. But that is likely to change at future process nodes as business pressures take root, something that is already becoming evident with the rapid proliferation of DFM tools and automated test suites.

Tools vendors characterize these changes as a shift from design engineer to systems engineer. But there’s far more to it than that. In the future, a systems architect will have to understand how the software will behave in the system they’re designing and how all pieces of the verification can be matched to the progress in the design. The next phase of systems engineering will be concurrency in multiple pieces of the design, with real-time feedback across the flow to make a series of modifications and more modifications until tape-out.

This is already evident in the number of tools players around the fringes that are trying to solve unusual problems–companies like Atrenta, Jasper, Oasys, CoWare, and a slew of others that have made inroads and will continue to make inroads.

Conclusion
Taken as a whole, the confluence of a variety of factors ranging from technology to tools to business is coming to a head. Each node from here gets tougher not because one problem has to be solved, but because more and more problems have to be solved simultaneously at each successive node.

Moore’s Law will continue, but not in the form in which it was originally conceived. A FinFET is not a classic transistor, and 3D stacking moves things into a different plane. Moreover, the tools to create these new devices will continue to change, the way they are manufactured will change, and the skills necessary to create these structures will change.

Perhaps even more important, all of these changes will begin showing up over the next couple of process nodes. We are all living and working in interesting times, but whether it’s a blessing or a curse may depend on each engineer’s role, their training, their ability to accept change and possibly even where they’re located

System-Level Design sat down with Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia, to talk about changes in the communications sector and how that’s affecting design. What follows are excerpts of that conversation.

By Ed Sperling
SLD: Where does multicore fit into the Freescale world?
Lisa Su: The difference between us and an AMD and Intel and IBM is they’re focused on multicore for the compute market. Freescale is focused on multicore for the networking market. Our focus is wireless infrastructure and network routers. Multicore is certainly prevalent in our world. We have an 8-core device running at 1.5GHz on each core. We’re also in the DSP space with multicore, because of all the parallelism there. We have a six-core DSP.

SLD: What’s changing as a result?
Su: With all of the competing standards in base stations, network equipment providers are looking at how to re-use their hardware equipment investment and operators are looking at how to maximize their CapEx investment. The trend is to go to common platforms that allow you to run multiple standards on a single platform. If you think about 3G, wideband CDMA is where a lot of the CapEx investment is going on the operator side. But LTE is right on the horizon and there is a great desire to be able to use the same common platform in 3G and LTE and in some cases WiMax. You need to get the performance of LTE and satisfy the cost points for 3G. Multicore is our strategy for doing that.

SLD: But don’t you still have the same challenges as the multicore computing world, such as parallelization of applications?
Su: We do have similar challenges and the results are mixed. On the signal processing side we’re able to take advantage of the parallelism. On the general-purpose processing side there is the challenge of fully using the processing capability. If you have an 8-core processor, you want 8 times the performance. There is a lot of work going on in tools, though. From a tooling standpoint, we’re getting better. Virtualization is a key piece, as well—being able to put applications on different slices of the chip. Multicore is taking off in communications right now. There is a lot of work by the OEMs to be able to convert their code.

SLD: Frequencies seem to be climbing again on individual cores. When do we blow the power budget?
Su: The frequency will go up, but not tremendously fast. You can put more cores on the chip. We built a data path infrastructure that manages the data across the cores. We believe you can scale up to 32 cores, if you want to. The real challenge is whether to use all those cores, or whether it’s better to improve performance in each of the cores—which is what we’re hearing from our customers. They can’t evolve their software that fast.

SLD: Is part of the strategy also to use cores for acceleration of processing?
Su: Yes, we can run an asymmetric processing mode where you have a master core and some others. What’s interesting here is not only do we have eight cores, but we have special acceleration engines like security accelerators on the chip. You can operate on the general processor or these specialty engines.

SLD: Are the cores homogeneous?
Su: When we call the devices 8-core, those are homogeneous. But there are additional acceleration devices. My view is that heterogeneous will become more popular as the applications become more specific.

SLD: That’s a much harder design problem though, isn’t it?
Su: Yes, but when you have high-volume applications it makes sense to do it that way because it’s the most optimized solution. When you’re in the infancy of a market, homogeneous is much easier.

SLD: Multicore also makes it harder to schedule shared resources on a chip. What’s new there?
Su: We have a hardware scheduling function. The key in multicore is to eliminate the contention between the cores to maximize the performance output. There are things we can do in hardware and software to schedule who gets access to resources.

SLD: Does this also affect the various states of applications and cores?
Su: Yes, there’s a lot of power management. Our world is 8 cores in less than 30 watts. It’s a tight power window. That’s our challenge—getting all that processing power in that power envelope.

SLD: Does this come down into the mobile device space?
Su: Yes. That’s the other part of our business. In our multimedia business, you’re seeing multicore devices. They’re going from single core to dual core. When you talk about mobile form factors it’s a slower progression, but it’s the same concept—how do you do more with less or within the same power envelope. It’s power and price point. There’s a consumer space, the low end of the enterprise, the midrange and then there’s the high end of the enterprise. At the low end it’s going from 1 to 2 cores, in the midrange it’s from 2 to 4 cores, and at the high end it’s 4 to 8 cores.

SLD: What process node are you at?
Su: 45nm.

SLD: Are you pushing to 32nm and beyond?
Su: Yes, the next node for us will be 32nm.

SLD: The foundries are beginning to talk about restrictive design rules at future nodes. How will that affect Freescale?
Su: That’s more of a style of design. I consider restrictive design rules like DFM on steroids. But it does require more design resources to migrate from one generation to the next.

SLD: Last time we talked, you mentioned that DFM tools weren’t all there. What’s missing?
Su: The challenge is still the interoperability with the tools. All the DFM tools need to be calibrated to a given foundry or fab, and that needs to come back to us. Ensuring that flow is seamless requires work. But I do have to say that since I made that statement all the EDA vendors have been calling to say they’ve solved the problem. I’ve been very popular with the EDA vendors. But the net of it is DFM is not optional and it’s important that when we use multiple foundries, the tools have to work well across the entire tool suite. It’s not something we can do as a post-processing thing anymore.

SLD: Is it a matter of chip developers choosing best in class from a variety of vendors and not having interoperability?
Su: Yes, that’s correct. Although we are going to primary EDA vendors, we’re not going to a single EDA vendor.

SLD: So having standards is vital?
Su: Yes.

SLD: How often do you increase cores? Is it the same node or the next node?
Su: It’s next node, because we want to keep a fixed power envelope. It’s not that you can’t add more cores, but you need to stay within the power envelope the application requires.

SLD: How about vertical stacking?
Su: It’s an option that can be used as the technology becomes more mature.

SLD: How far down does your road map extend?
Su: In the product business, we’re looking at 32nm and 22nm. The evolution of the technology has a lot to do with how fast we use it.

SLD: Is there a possibility that after that you don’t go further?
Su: I won’t say that yet. People have said that at every node and it hasn’t come true. But the product adoption rate may be different. There fundamentally still is improvement in technology. As long as there is improvement in density and performance, we will continue to look at new nodes.