By Ed Sperling
Japan’s SoC market, which has been a big market for advanced EDA tools, may be headed for a major consolidation. Renesas, Fujitsu and Panasonic are in talks to combine portions of their business in conjunction with the Japanese government’s Innovation Network Corp., according to numerous news reports. One particularly interesting addition to these changes in Japan: GlobalFoundries may buy Elpida Memory’s Hiroshima fab. Whether all of these changes create a larger and much stronger market for tools and services, or whether it actually shrinks, is a big question mark.

Cadence is collaborating with Samsung for 32, 28 and 20nm DFM flows. Key to the deal are pattern classification and search, CMP prediction, and both litho and yield analysis.

Synopsys won a deal with CSR for its Galaxy implementation platform. CSR makes everything from low-energy Bluetooth chips to GPS ICs.

eSilicon expanded its SerDes licensing deal with Avago. Under the terms of the deal, eSilicon will be able to include Avago’s SerDes cores—from 28nm to 90nm—in chips for the communications and storage markets. http://www.esilicon.com/press-releases/195-esilicon-expands-serdes-ip-licensing-agreement-with-avago-technologies-

Methodics rolled out a new release of its IP version-control product, aka Subversion, boosting performance and improving the distributed use model. As IP use and re-use grows, keeping track of IP in complex designs is turning out

By Ed Sperling
Mentor Graphics introduced an integrated component-to-system thermal characterization and analysis solution that combines hardware test with its FloTherm software. This is a particularly interesting more for the LED and IC packaging arenas, given the focus on leakage and heat.

Cadence won a deal with Panasonic for its Palladium XP platform, which combines simulation, acceleration and emulation. The tools will be used in a variety of digital consumer electronics.

HiSilicon has licensed eSilicon’s 40nm ternary content-addressable memory macros for its networking chips.

Blu-Wireless has licensed Sonics’ on-chip communications IP for its wireless communications processors aimed at the unlicensed 60 GHz market. Blu-Wireless will use the IP for a new generation of multi-gigabit communications for consumer electronics.

Synopsys claimed a share of the victory in GlobalFoundries first complex 20nm tapeout, complete with double patterning. A number of Synopsys tools were used to achieve silicon success.

By Ed Sperling
System-Level Design sat down to discuss the future of stacked die with Riko Radojcic, director of engineering at Qualcomm; Prasad Subramaniam, vice president of design technology at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that conversation.

SLD: Where are we with 2.5D and 3D?
Radojcic: I think 2.5D was a misnomer, because that implies they are sequential. It’s clear that what we call 2.5D and 3D are going to co-exist for a long time. Some things make sense with an interposer and some make sense to be 3D.
Reiter: I agree—2.5D is a parallel effort to 3D. Lots of things will not use 3D because it’s too expensive. In 2.5D we will see production this year. With 3D it will take until next year for the first ones. I would guess computing or networking would be the first.
Radojcic: I would think those guys will pursue 2.5D.
Subramaniam: Memory makers are already offering 3D solutions today. If you look at just the memory chip, to increase the size of the memory rather than the die they’re stacking it vertically. That kind of 3D is already in production. It’s the question of co-mingling logic and memory that will take time. The advantage of 2.5D is that it allows afterthought. It allows you to take an existing design and to create a new set of I/Os and put in a 3D type of application.
Radojcic: I see no value in doing that. You’re creating an expensive solution to something you can do more cheaply. If you add the 3D interposer you’re adding another wafer. That’s cost. We can solve that problem with a flip chip. It’s cheaper.
Subramaniam: I disagree. We’ve done the analysis. It allows us to take an existing design, like an ARM subsystem in 28nm, even though surrounding logic doesn’t have to be at that 28nm process node. It can be 40nm or 65nm. Rather than building a new chip at 28nm, I can take my existing design, use it as one component of my 3D IC, and build a second chip in a cheaper, older technology.
Radojcic: Yes, as long as you’ve architected your chip like that, such that you can partition it.
Subramaniam: You can’t take any design, no. There has to be some partitioning in the architecture and some forethought. It’s not 100% an afterthought, but there is still some afterthought there.
Radojcic: You have to architect for it. If you haven’t done that, taking an existing chip will just cost you more. If you have done that, of course there is an avenue to doing things better and more flexibly.
Subramaniam: There is enough flexibility in designs that allow you to partition it in some manner.
Radojcic: True, but before 3D came along most of us wouldn’t have partitioned. We wouldn’t have architected it that way. To be able to leverage that value proposition, you must have 3D in mind.
Gianfagna: That’s true. It’s a premeditated act. If you don’t think it through way up front it doesn’t work.
Subramaniam: Because the SoC has a well-defined architecture, it lends itself to this type of application.
Radojcic: But only if you plan for it ahead of time.

SLD: Is this true in all cases?
Reiter: That’s the view of a high-volume supplier. I see low-volume solutions where they use an existing die, put it face down on an interposer, and connect memory to it. So for low to medium volume, 2.5D works. You call it an afterthought. I call it a customized solution.
Radojcic: Why wouldn’t you do that in a traditional multichip package?
Subramaniam: Because you don’t get the interconnectivity. The advantage of a silicon interposer is that you get thousands of interconnects.
Radojcic: But you have to design it sufficiently so you can leverage the interconnects from die to die. If you had designed for a traditional design, though, you would say, ‘I can’t have thousands of interconnects so I’m going to make a serial interface with 100 pins.’ If you take that design for a 100-pin interconnect and stick in an interposer it’s an expensive way of doing things.
Subramaniam: You may be able to take some internal signals out, which you are not able to do with a traditional MCM (multi-chip module) approach.

SLD: Let’s do a reality check. How far along are we toward stacking?
Gianfagna: Last year we had a hot-wired 3D system that was 2D with a bunch of scripts and manual effort. The customer base had strange, contrived designs and they were trying to see what they could and couldn’t do, and the foundries didn’t know what they wanted to do. A year later we have native 3D planning capability, the customer base has specific designs for implementation this year and next, and the foundries have a laser-sharp focus on process learning, mostly around 2.5D initially. If that’s a metric, things are clearer this year than last year. From an EDA perspective, I still think the market is two years away. But we still think this is big.
Reiter: If you look at the Atom chip with the FPGA from Altera, that’s basically a 2.5D solution. The FPGA is for customizing things. The Atom chip was not designed for this application.
Radojcic: But why use an interposer? Why not use a substrate and a multichip package?
Reiter: You could do that.

SLD: What’s missing from the tools side to make all this work?
Reiter: The ability to demonstrate what this technology can do is the most important capability. If you look at big corporations, top management is still hesitant to invest in this technology. If we could demonstrate in a credible way what it can do, people will be more successful in getting money to start programs using this technology.
Gianfagna: The way that happens is the early adopters blaze the trail, everyone tries to follow and the market heats up. What’s needed are commercial drivers. The tools aren’t there, but they’re close enough.
Subramaniam: The tools are not the issue. The development needed to support 3D is incremental. It can be done with the existing infrastructure. It’s really the end application.
Radojcic: Other than path-finding, which is hard to do with traditional tools. And the analysis.
Gianfagna: The complexity is higher. We’ve discovered that, too. RTL prototyping for a single chip has a certain set of challenges. When you go to 3D the modeling requirements are much greater, the constraint generation is more complicated. And we need standards. We can generate all the constraints, but we don’t know where to put them and how to express them because there is no agreed upon way to do that.

SLD: Do the standards organizations know where to start with all of this?
Radojcic: Standards are on a good track. We’ve worked with Si2 and Sematech to propose initials blasts for standards so we can feed them into Si2 and the EDA community and accelerate the process. The bits and pieces are moving, and we are on track to have a set of design exchange format standards by early next year.
Reiter: And Wide I/O.
Radojcic: Yes. The standards are channeled and the engine is revving.
Reiter: We have a bunch of players in a 3D enablement center participating. There are 15 companies listed, including Intel, IBM, TSMC, GlobalFoundries, and so on.
Radojcic: The way this was set up was Sematech said we are going to start a 3D enablement center initiative driven by the SIA. All the members of Sematech were mapped into this. Then a number of companies like Qualcomm, LSI and ASE joined.

By Ed Sperling
The semiconductor industry continues to chug along, despite global economic uncertainty, standoffs in the Eurozone, and slowdowns in Brazil and China.

eSilicon won a deal with Ikanos Communications for manufacturing operations and logistics. This isn’t the first deal of this type eSilicon has won, and it says something about how companies are coping with a disaggregated supply chain.

Mentor Graphics won a deal with China-based ZTE Mobile Telecom, which licensed Mentor’s Inflexion technology for 3D smartphone user interfaces.

GlobalFoundries certified Synopsys’ IC Validator for physical verification at 28nm, 40nm and 65nm. The goal with this stuff is to avoid last-minute surprises. In the design world, surprises are almost always bad.

Apache Design won a deal with Fujitsu Semiconductor, which adopted its Totem Software for power noise and reliability analysis. This kind of analysis is interesting at advanced nodes, but it will be critical in stacked die.

By Mark LaPedus
There may be a new hitch in moving to 2.5D stacked die—there aren’t enough suppliers of leading-edge, fine-pitch interposers.

That has put a crimp in supplies and raised prices significantly. A single interposer is reportedly selling for twice the price of a leading-edge 300mm wafer from a foundry today.

TSMC is one of the few vendors that can provide fine-pitch interposers for leading-edge designs. GlobalFoundries and UMC are readying their own offerings, but they have yet to to officially announce their technologies, according to E. Jan Vardaman, president and founder of TechSearch International, a research firm.

For some time, there has been a school of thought that the 3D chip market would evolve in two steps. First, vendors would develop 2.5D devices using silicon interposers, followed by the evolution of true 3D devices based on through-silicon vias (TSVs). But now, many experts believe that 2.5D chips using interposers will have a life of their own and will become a significant market.

Silicon interposers, at least in the initial iteration, are passive components that provide an intermediate layer between the substrate and the active device. The connections between the interposer and active device is handled through microbumps. And the connection between the interposer and packaged substrate is done via solder balls and TSVs.

“Silicon interposers are the new multi-chip modules,” said Subramanian Iyer, an IBM Fellow and chief technologist for the Microelectronics Division at IBM Corp. “They are potentially cheaper. So they are the first and very useful step in the 3D progression and will likely be adequate for a great many applications.”

At last count, there are 11 companies that supply silicon interposers, although most are not supplying fine-pitch components for leading-edge designs. Many offer larger-pitch interposers for MEMS, RF and other applications. Today’s interposer suppliers include Allvia, ASE, DNP, EPWorks, IBM, IMT, IPDiA, Silex, SPIL, STATS ChipPAC and TSMC, according to TechSearch. Others are in the planning or R&D stage, including Ibiden, Samsung Electro-Mechnical, Shinko and WLCSP, according to the firm.

The lack of supply for fine-pitch interposers is causing these components to be sold at a premium. Manish Ranjan, vice president of advanced packaging at Ultratech Inc., said the cost for a 300-mm, 28-nm wafer at a foundry is around $5,000 today. In comparison, there are reports that the interposer itself is about $10,000 alone, Ranjan said. “There are few people” that can make fine-pitch interposers, he said.

By Ed Sperling
Sonics filed suit against Arteris for infringing on network on chip patents, while Arteris rebuffed the claims. Things must be really heating up in the NoC space. http://chipdesignmag.com/sld/blog/2011/11/03/sonics-sues-arteris/

Tower Jazz’s qualified Cadence’s mixed-signal solution and PDK for its 180nm and 350nm reference flow 2.0 using bipolar CMOS-DMOS (BCD) process technologies.

ARM acquired Prolific, a startup hat develops tools for optimizing power, performance and area.

Also on the IP front, Methodics entered the Japanese market with its SoC design data and IP management platforms. Japan is one of the leading adopters of advanced EDA tools and IP.

GlobalFoundries named a new CEO, Ajit Manocha, which is rather anticlimactic. He had been serving on an interim basis since June.

And TSMC reported its Q3 numbers. Revenue decreased 4.5% sequentially from Q2, but it was up 4% from the same period in 2010. What’s particularly interesting is the breakdown. The company said 40nm and 28nm accounted for 27% of total revenues, while 65nm accounted for another 27%.

By Ed Sperling
Synopsys completed the acquisition of Extreme DA. Synopsys said the acquisition will extend its push into static timing analysis and multicore software development. Synopsys also said its USB 3.0 IP has more than 40 design wins. Sounds like we’re going to start seeing this stuff in real products soon.

eSilicon and MIPS have taped out a 28nm 1.5GHz three-processor cluster using GlobalFoundries’ 28nm SLP process. MIPS provided the RTL for its Coherent Processing System, while eSilicon performed the synthesis, timing-driven layout and optimization.

Sonics teamed up with Munich-based Lantiq to create the next-generation network for the digital home. This stuff is certainly getting easier and much, much faster. Remember what it was like to set up a home network 10 years ago?

X-FAB, the analog/mixed signal foundry, qualified Cadence’s physical verification system for all process nodes. The foundry works on geometries ranging 1 micron to 0.18 micron.

By Ann Steffora Mutschler
Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a thing of the past for most SoC design teams, and so will portability between designs.

Specifically, the ability to randomly add in new IP or substitute IP will be severely limited because the DP coloring constraints have a lot of interaction problems between cells, explained David Abercrombie, program manager for advanced physical verification methodologies at Mentor Graphics. “If the cells don’t follow the same methodology in regard to coloring boundary conditions in something as simple as an IP library of standard cells, and they know the cells are going to butt each other (share the power and ground), then because they have to be colored you can’t allow the power rail in one cell to be on mask zero and the power rail on the next cell to be on mask one. They have to end up on the same mask. So you need to enforce that all the powers have a certain coloring and all the grounds have a certain coloring.”

That all works fine in theory until someone else designs an IP library and make all of theirs zeroes. The two of those cannot be combined together. And as with all new processes, the design rules and process details are not clear.

“I’ve heard two schools of thought,” said Manoj Chacko, product marketing director at Cadence. “One school says everything will be decomposed from a cellblock IP level and designers will have to work with decomposed layouts. There is another school of thought saying, ‘Meet our rules, don’t worry about decomposing it, go through your traditional flow but you have to meet all these additional double patterning rules in addition to the traditional design rules. When you come to the end there are qualified double-patterning decomposition tools/engines that all the EDA vendors have. They can decompose it, and then there is a small iterative cycle just to ensure that you have no issues and conflicts and that this is all compliant with what the foundry has.”

But this hasn’t just happened overnight. Hans Bouwmeester, director of IP engineering at Open-Silicon, said that at 40nm, we started seeing limitations on what we could do related to the memories. “In 28nm you see more of those limitations requiring a single poly direction for the entire chip. Portability of IP becomes more and more a concern especially when it concerns analog IP. It doesn’t scale well so you don’t get the area benefits going to the deeper submicron process. So it is definitely a factor that comes more and more into play as we go into deep submicron processes.”

Since 65nm, Jean-Marie Brunet, marketing director for DFM products at Mentor Graphics, has observed a fundamental shift with respect to IP design. In the past, IP designers used to create their IP without regard to where it was going to be used and in what context. Now, with DFM lithography proximity effects, IP vendors have to design their IP knowing it will be used in context No. 1 with one chip and context No. 2 with a different chip. “Unfortunately with advanced nodes, optical radius and OPC effects, the context started to severely affect the intrinsic behavior of the IP. And that is a fundamental shift. They have to make the IP very context free, which is very difficult.”

These contextual issues call for examination of the lithography context to an IP, such as CMP effects, and analysis of contextual problems. The contextual issues get more intense the smaller the node.

Due to contextual issues and other challenges, IP re-use at 20nm with double-patterning will be very complicated. “There’s no question that at 20nm and below those are going to be very different nodes. Design flow, design methodology that we are working on right now, as well as other competitors, is going to be very difficult. I’m not too sure yet if the industry has found an easy way to do IP re-use with double-patterning. We are all going through test chips right now, validation vehicles for reference flows, and re-use of blocks. And each time we are struggling,” Brunet said.

“Solutions are being put together, but I will not say this is a done deal. We will go through issues with double-patterning. Unfortunately, it is going to be very high in cost–not only in mask and silicon, but in design flows as well. I think we’re going toward actually having severe limitations on the type of design styles and rules just because of the nature of double-patterning,” he added.

With each more advanced manufacturing node, the problem will be significantly more painful for tier-two and tier-three SoC developers, as industry players discuss in this video.

Open-Silicon’s Bouwmeester is a bit more optimistic about IP portability in the future. “I’m not completely sure whether it is going to be completely a thing of the past, but I would certainly agree that the expenses IP vendors have to take in order to port IP between foundries are going up. There is more work involved for them to bring a piece of IP they may have for example in a TSMC 28nm process to Global Foundries, and that is expected to continue or become worse as we go to more deep submicron processes. I guess there also may be more business considerations in that TSMC being the lead foundry is getting more and more protective to prevent other foundries from copying parts of their process. In other words, TSMC has a business interest in making it harder to support portability between foundries.

But Abercrombie insisted, “Even though IP vendors would sell you a library for one foundry versus a library for another foundry, honestly, we all know under the hood they built one library and it took the least common denominator. The rules were close enough that just being a little bit intelligent you could make a set that would run on either one. At 20nm and below, no. We talk to these guys and they have to build completely different, from-scratch libraries. There’s no possible way to make one. It says portability is out the window.”

It’s not all bad news, though. Navraj Nandra, senior director of marketing for analog/mixed-signal IP at Synopsys said, “If you are doing libraries and IP development you have to nowadays be early with the technology such that when customers are ready to work in these new nodes they see a bunch of IP available. We see some of these stresses early on. Some of the customers I’m speaking to at the moment are scoping out their 20 nm options—for the ones that are considering 20 nm.”

While he recognizes that IP development complications with 20nm are at least twice the complications of 28nm, he pointed out, “That’s my problem but it’s not my customer’s problem. My customers don’t care. All they care about is making sure schedules and performances are met.”

Walter Ng, vice president of GlobalFoundries’ IP ecosystem, acknowledged there is fear surrounding IP portability at 20nm. “We do see a good amount of concern among the design community with regard to the impact of double patterning on each of them and what it will mean to them and how much it will increase the complexity and difficulty of their task. We are always sensitive to that. In this case, as we go down the technology curve, it’s going to be more and more challenging to achieve the entitlement that maybe over many of the technology nodes previously has just been an expectation.”

“Double-patterning is the only way at this point that we or anybody else can achieve the 2X density that is expected. And we certainly are trying to minimize the requirement because it goes back to balance. We understand the economics of this in addition to the technical challenges, and we are trying to minimize the double-patterning requirements such that it can stay an economically viable technology node both from a processing cost as well as a design cost,” he continued.

As such, GlobalFoundries does real-time collaboration with the top EDA companies, as well as major IP providers.

On top of double patterning, Ng agreed that from an IP portability standpoint 20nm brings another challenge. “The reality among the design community is that even at 28nm, its been very challenging with regard to wanting to preserve portability where it wasn’t intended from the outset.”

“If you want to achieve optimal IP implementation, even if you wanted to try to look at a superset approach and be satisfied with ‘fat’ IP, it hasn’t been easy,” he said. “We have whittled away at the ability to easily port unless it is by design. When it comes to double-patterning and 20nm it certainly ups the bar, and it does make IP portability across random manufacturers a nearly impossible task because of certain aspects of the process definitions as well as the decomposition rules themselves. It’s not going to be the same. With the level of detail, unless it is planned for up front by design, it will be virtually impossible.”

However, he concluded, “It starts subtracting from the value statement of moving to that next technology node. If you’re going to do that superset where you’re not taking advantage of optimizing your IP and optimizing your design for a specific technology node, then you really should be considering whether you should be moving to that node because you’re just leaving so much on the table.”

It was a good week for GlobalFoundries, whose Global Technology Conference spawned a slew of announcements. Mentor Graphics teamed up with GlobalFoundries to improve yield analysis, based on Mentor’s Tessent test and Calibre DFM platforms. GlobalFoundries has been using DFM-aware yield analysis to separate design- and process-related yield limitations.

Cadence also inked a deal with GlobalFoundries to speed up DFM signoff at 28nm, integrating Cadence’s “in-design” DFM technology with GlobalFoundries’ DRC+ methodology.

Kawasaki Microelectronics, aka K-micro, licensed Sonics’ Network for AMBA Protocol (SNAP) solution for passive optical networks. SNAP is used to optimize on-chip network designs. K-micro, meanwhile, develops ASICs for delay-sensitive voice and video.

European foundry Altis Semiconductor, meanwhile, is working with Cadence to migrate and enhance its 130nm PDKs to support Cadence’s Virtuoso IC design tools.

Synopsys inked a multi-year renewal of its synthesis partnership with Achronix Semiconductor, which makes high-density FPGAs. Under the terms of the deal, Synopsys’ FPGA logic synthesis technology will be expanded to support Achronix’s 22nm chips.

By Ed Sperling
GlobalFoundries is working with Mentor Graphics on the third-generation of DFM to tie together more pieces of the design process to reduce manufacturing variability, which is a significant problem at advanced process nodes. The collaboration ties together GlobalFoundries’ manufacturing analysis and scoring methodology and Mentor’s Calibre critical feature analysis, as well as LFD kits for 28nm and 20nm, better CMP models for 28nm, and better interaction with place and route tools.

Apple, which a big driver of innovative designs and tools, has a new leader. Steve Jobs, whose iconic status makes it hard to judge the impact of his exit on the company in the short term, will be succeeded by right-hand man Tim Cook. While Apple will continue investing in its current products, the question is whether it can really dazzle the market with new products as it did with the iPod, iPhone and iPad. Time will tell. But in the meantime, there will be no shortage of speculation throughout the business press—and certainly lots of discussion about this topic inside competitor companies.