By Ann Steffora Mutschler
Yield. Just the word can make many engineers cringe and hide in their cubicles—especially with manufacturing problems and excessive power during test increasing causing failures. But the combination of physical data with diagnostics engines may be the light at the end of the tunnel, allowing for easier pinpointing of defects.

There are many reasons why a chip fails on the tester, and most fall under two areas. One area includes manufacturing problems, explained Bassilios Petrakis, director of product marketing for front-end products at Cadence. “You can think of a case where the wires are not manufactured ideally, so sometimes they might touch because of a short. Or sometimes the wires are thinner than they should be, which causes more resistive type behavior in the wire or they get disconnected. There are tons of defects that are either known, or new ones that come up with new processes.”

Another class of problems is due to excessive power when the chip is tested. “What tends to happen is people design a chip for tolerances when it’s being used in the normal function—in a cell phone or whatever it is—but you also have to consider what happens when you test the chip. We’ve seen failures on the tester. Customers tell us that. And after some work, most people tend to think they are manufacturing defects. A lot of them actually occur because there’s way too much switching activity on the chip that wouldn’t happen in functional mode,” he said, which can cause a chip to fail the test, or even damage the chip itself.

These issues traditionally have been addressed by the diagnostics tools associated with ATPG, but thinking in this area has expanded. Robert Ruiz, senior product line manager for test automation at Synopsys noted that diagnostics has been around for as long as ATPG because they are correlated technologies, but efforts have been underway to improve the accuracy of layout-aware/physical diagnostics tools by pulling in physical information to cut down the search base. “Older diagnostic technology looks at a wire as one node. Everything is connected to it and it can’t pinpoint out. Using physical diagnostics understands that this is not one, single continuous wire but it fans out—there are branches on it. When I think of branches, I think about a defect on that tree. You narrow that tree down among several trees, but if you have more physical information about the tree you know if a defect is along one branch.”

Physical diagnostics use is on the rise due to the accuracy it promises. Connected to this is the need for the infrastructure to support it, which prompted Synopsys to add the ability to read in LEF DEF so it can become layout-aware and run diagnostics, he said.

Alongside traditional diagnosis is volume diagnostics, which brings in another dimension of data into the diagnostic tools. “What’s driving this is the fundamental trend of moving away from individual test engineers diagnosing a fairly small number of failing parts to a much more systematic process,” explained Cy Hay, product marketing manager for ATPG and diagnostics at Synopsys. “It’s not really changing the traditional application. It’s an expansion beyond using diagnostics in an almost offline manner, where there is a test engineer sitting in a lab on a tester with a few failing parts that maybe came back as returned merchandise, to a much more systematic application of diagnostics to improve yield. Especially with the types of yield limiters that customers see today, combined with the pressure to not only bring up a new process node but new designs manufactured in very high volumes, very quickly—there’s clearly a lot of pressure there. The traditional techniques that the fabs have used to improve yield don’t always apply or don’t work as efficiently on some of the more advanced process nodes, especially the aggressive and large designs that are being thrown at a new process node.”

New technology, new challenges
With all of this great new technology, there are challenges too. Geir Eide, DFT product marketing manager at Mentor Graphics, pointed out that part of the challenge now is getting people to talk together. “People who don’t even know the other guys exist—basically connecting product engineers, failure analysis engineers, test engineers, physical design and library designers—you’re basically giving these guys some technical capabilities that allow them to communicate.”

The problem is that they’re not used to talking to each other even though there is much to be gained by opening up this kind of conversation.

“You’re dealing with the fact that something that is beneficial for the product engineers, that will make his job easier, for him to be able to use these capabilities he needs the DFT engineers and the test engineers to enable that,” Eide said. For instance, for diagnosis to work, the data collected on the tester is needed, which means that the test engineer needs to facilitate that. While that doesn’t necessarily makes his job harder, it’s just something that he needs to do to help someone else’s job easier. This means there is a lot more interplay across different organizations and sometimes even across companies where test is outsourced, failure analysis might also be outsourced.

“Part of the beauty of these types of tools is we make it possible for multiple organizations to do the analysis so you don’t need to sit in the fab to do the analysis. You don’t need all the fab data to do this. From that point of view, the challenging piece here is that you have to share data across organizations that normally wasn’t shared, and you have to store the data and make it accessible. On the other hand, you can use software to do a lot of work that previously required you to take a lot of physical devices and slice and dice them and kind of do a lot of expensive, time-consuming analysis,” Eide added.

“The test guys don’t usually give a rip about the physical design—it’s just there. What we are trying to do is being able to make it so that they don’t have to know all the rules and things that they are looking for,” stressed Jeff Wilson, Calibre product marketing manager at Mentor Graphics.

During Mentor’s recent User2User conference, Global Foundries discussed combining diagnosis results that originate from test results and using real silicon data to help validate and identify the yield-limiting design features which ties into DFM tools.

There are a lot of ways things can go wrong. Whether it is a lithography problem, a fill problem, or other issue, being able to determine the root cause of that that problem and being able to fix it is the area that probably is going to bring the biggest benefit to the designers because the test guy shouldn’t have to know all the stuff about the physical design to make things work, he concluded.

By Ed Sperling
Cadence rolled out new LPDDR3 memory IP, upgrading the bandwidth management engine to improve performance while lowering power consumption. The company also expanded its Shanghai office for R&D, as well as sales and technical support.

Synopsys rolled out verification IP for Non-Volatile Memory Express (NVMe), which allows solid state drives to connect directly to PCI Express. Synopsys also announced its VDK family of products for ARM Cortex processors, including big.LITTLE.

Altera has jointly developed its own 3D IC test vehicle using TSMC’s chip-on-wafer-on-substrate integration process. This puts Altera head to head with Xilinx on stacked die.

And GlobalFoundries shipped its 250,000th 32nm high-k/metal gate wafer, thereby ending speculation about whether HKMG will ever go mainstream. The 28nm node uses the same technology.

By Ed Sperling
Mentor Graphics introduced a new Calibre DFM flow for GlobalFoundries 45/40nm and 32/28nm processes, which it claims can significantly boost yield and improve turnaround time for full-chip designs. Also on the DFM side, Mentor rolled out the next version of its PADS suite for PCB design through manufacturing, adding the ability to link high-speed associated nets and assign constraints.

Cadence introduced its Encounter RTL-to-GDSII flow for high-performance and giga-scale designs down to 20nm. What’s especially interesting here is support for double-patterning, one of the big issues with progressing down Moore’s Law because foundries have unique ways for doing this. Cadence also launched a business incubation program in Australia to boost entrepreneurship in this market. Nice design, mate.

Arteris inked a deal with Carbon Design Systems to enable NoC interconnect IP to be generated, managed and distributed using Carbon’s IP Exchange portal.

Atrenta announced that 10 IP providers have qualified soft IP for TSMC’s 9000 IP library using Atrenta’s IP Handoff Kit. The tool checks for syntactical and semantic correctness, power consumption and clock domain issues, among other things.

By Ed Sperling
The push to “smaller, faster and cheaper” hasn’t changed since ICs were first introduced, but the context for those requirements is beginning to shift—with enormous consequences.

What was once done on multiple chips continue to migrate to a single chip or package because of cost, but in some cases the decisions about goes where go well beyond an individual device to include a network of systems. Power and heat have forced some of those decisions. Others are being driven by shorter market windows that affect business decisions about exactly when to move to smaller, faster and cheaper, and whether to keep a design in two dimensions or move to three. In some cases, it even has evolved into a tradeoff about sharing resources to make up for additional costs elsewhere in a design.

“Form factor is everything in a lot of these cases, and you’re being forced to make tradeoffs involving a lot of different pieces,” said Mike Gianfagna, vice president of marketing at Atrenta. “But that requires you to know exactly what you’re doing. A lot of times you don’t. What happens when you reduce the number of layers? Do you know the impact on the system? You may not. But competitive pressure is also forcing you to rethink everything.”

Rethinking designs
Some of these changes are as fundamental as where the processing gets done. While the concept of cloud computing has been around since the days of time sharing on mainframe computers in the 1960s, the ability to offload processing and storage on the fly—and to load balance across compute farms around the globe—adds a modern twist to it all.

The result is a handheld device with the performance capabilities of a compute farm—but with the design focused far less on local processing and storage and more on communication and battery life.

This is evident with a number of upcoming communications schemes and protocols in the handheld market. LTE Advanced, for example, which is expected to find its way into smart phones and base stations over the next four years, focuses on reducing power while increasing performance. One of the best ways to do that is by shifting what processing is done where.

“One of the key decisions is how much processing and intelligence is in the cell phone versus the cloud,” said Graham Wilson, a product marketing manager at Tensilica. “You also have to understand deeply what cores are being used for. There is no room for fat. We’re also going to see a big shift in infrastructure from homogeneous to heterogeneous.”

That means rather than a giant cell tower on the highest hill or building, smaller boxes will be mounted on houses and strung together in a mesh network. “Every house will have its own femto cell or pico cell box so they’re less reliant on the macro cell and they work off each other,” Wilson said.

That changes what resources can be committed within a design to processing, to communication, to storage, and where it can be done best—whether it’s a central processing unit or lots of smaller processors for individual uses. It also boosts the ability to cut some costs in different places than just by shrinking the process geometries in a design.

The Low-Latency Interface working group of the MIPI alliance, for example, is currently working on a new standard that allows DRAM memory to be shared between two chips. NoC technology vendors, in particular, have seen this push because it requires a highly efficient network-on-chip infrastructure.

“The big advantage is that it allows you to get rid of an entire memory chip,” said Kurt Shuler, vice president of marketing at Arteris. “The modem and the application processor are sharing the same memory. You also reduce the number of pins, which is important because it allows you to use those pins for other things.”

He notes there is a very slight performance hit. But the ability to eliminate an entire memory chip can save a couple dollars in a design. Multiply that times millions of units and the savings are huge—far greater than just shrinking the features on a die.

Rethinking packaging
Stacking die offers another alternative to improving performance and time to market, but the tradeoff will be in cost unless additional components can be eliminated. Adding an interposer layer or TSVs will be expensive—at least initially—even though 2.5D and full 3D stacking hold the promise of dramatically improving performance through shorter distances, bigger pipes for data, and lower power because signals will not have to be driven as far.

While this packaging approach is still under development, foundries report that chips are rolling out using this approach. “This is already happening,” said Luigi Capodieci, R&D Fellow at GlobalFoundries. “It’s mostly a decision of which design processes to use in the chip, and that decision will have to be made by the chip designers.”

Stacked die also allow IP developed at older nodes—particularly analog—to be attached through Wide I/O to other chips developed at more advanced processes. That, at least in theory, substantially reduces the time it takes to design a chip because much of it can be based on what has been previously developed.

“Re-use leads to a reduction in time to market,” said Shrikrishna Gokhale, COO and managing director of Open-Silicon’s India unit. “This opens up the lifecycle of different IP and puts the emphasis on packaging and re-use.”

It also puts greater emphasis on software-hardware co-design, he said, and requires more emphasis on defining partitioning earlier in the architecture phase. In addition, it requires a rethinking of what gets done where. Some portions of the design that used to be in separate locations now have to be co-located in the same place because of the constant need to update models and data for both hardware and software teams.

“The logic front-end design needs to be done at the same location as the software,” he said. “That’s less important at the back end, which is the physical implementation.”

Other tradeoffs are less obvious, though, particularly to design engineers. One involves weight.

“Half the weight of a tablet is the battery,” said Drew Wingard, CTO of Sonics. “You can’t afford to add a bigger battery so you have to do an increasing amount of computation with lower power. That means you look at more efficient ways of doing that computing. One is using the GPU as a general-purpose CPU, which allows you to get a lot of performance at low energy.”

He noted that utilizing the GPU requires it to be easily accessible to software developers. And it requires much better management of clock domains, voltages and on-off functionality within an acceptable power budget. And to be really energy-efficient, users need to be able to easily input their own usage models.

Rethinking manufacturing
Some of the changes that are under way are forcing a major shift in manufacturing, too. Staying on the Moore’s Law road map has always been a given for high-volume digital designs, but with double patterning required at 14nm and the delay in extreme ultraviolet lithography, alternatives are being considered that could have ramifications throughout IC design.

“Double patterning is the biggest issue we’re dealing with right now,” said Jean-Marie Brunet, director of product marketing for model-based DFM and place and route integration at Mentor Graphics. “We’re even looking at triple patterning, but there is no way to have density balance between the layers when you do that.”

Lars Liebman, an IBM distinguished engineer, said his company has been working on commercializing self-assembly for finFETs because even multi-patterning isn’t sufficient beyond 14nm. That has implications throughout the design chain. For one thing, it can increase the density on existing process nodes. For another, many of the tools for automating design, particularly on the DFM side, will need to be rewritten.

Conclusion
Area, power and performance have always been the standard metrics for tradeoff in any IC design. What’s changing significantly is why those tradeoffs are being made and where the benefits will show up. Changes targeted at an individual chip in the past, or even a block or subsystem, may now be aimed at a much broader level.

The good news is that infrastructure changes—everything from manufacturing approaches to communications networks—evolve much more slowly and deliberately than those made in the individual device or chip. The bad news is that sometimes that moves so slowly that it can affect what’s done elsewhere in this much broader system. But some change is underway at every level, and managing that change—and the tradeoffs it will demand—will be much more challenging in the future.

By Ed Sperling
Japan’s SoC market, which has been a big market for advanced EDA tools, may be headed for a major consolidation. Renesas, Fujitsu and Panasonic are in talks to combine portions of their business in conjunction with the Japanese government’s Innovation Network Corp., according to numerous news reports. One particularly interesting addition to these changes in Japan: GlobalFoundries may buy Elpida Memory’s Hiroshima fab. Whether all of these changes create a larger and much stronger market for tools and services, or whether it actually shrinks, is a big question mark.

Cadence is collaborating with Samsung for 32, 28 and 20nm DFM flows. Key to the deal are pattern classification and search, CMP prediction, and both litho and yield analysis.

Synopsys won a deal with CSR for its Galaxy implementation platform. CSR makes everything from low-energy Bluetooth chips to GPS ICs.

eSilicon expanded its SerDes licensing deal with Avago. Under the terms of the deal, eSilicon will be able to include Avago’s SerDes cores—from 28nm to 90nm—in chips for the communications and storage markets. http://www.esilicon.com/press-releases/195-esilicon-expands-serdes-ip-licensing-agreement-with-avago-technologies-

Methodics rolled out a new release of its IP version-control product, aka Subversion, boosting performance and improving the distributed use model. As IP use and re-use grows, keeping track of IP in complex designs is turning out

By Ed Sperling
Mentor Graphics introduced an integrated component-to-system thermal characterization and analysis solution that combines hardware test with its FloTherm software. This is a particularly interesting more for the LED and IC packaging arenas, given the focus on leakage and heat.

Cadence won a deal with Panasonic for its Palladium XP platform, which combines simulation, acceleration and emulation. The tools will be used in a variety of digital consumer electronics.

HiSilicon has licensed eSilicon’s 40nm ternary content-addressable memory macros for its networking chips.

Blu-Wireless has licensed Sonics’ on-chip communications IP for its wireless communications processors aimed at the unlicensed 60 GHz market. Blu-Wireless will use the IP for a new generation of multi-gigabit communications for consumer electronics.

Synopsys claimed a share of the victory in GlobalFoundries first complex 20nm tapeout, complete with double patterning. A number of Synopsys tools were used to achieve silicon success.

By Ed Sperling
System-Level Design sat down to discuss the future of stacked die with Riko Radojcic, director of engineering at Qualcomm; Prasad Subramaniam, vice president of design technology at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that conversation.

SLD: Where are we with 2.5D and 3D?
Radojcic: I think 2.5D was a misnomer, because that implies they are sequential. It’s clear that what we call 2.5D and 3D are going to co-exist for a long time. Some things make sense with an interposer and some make sense to be 3D.
Reiter: I agree—2.5D is a parallel effort to 3D. Lots of things will not use 3D because it’s too expensive. In 2.5D we will see production this year. With 3D it will take until next year for the first ones. I would guess computing or networking would be the first.
Radojcic: I would think those guys will pursue 2.5D.
Subramaniam: Memory makers are already offering 3D solutions today. If you look at just the memory chip, to increase the size of the memory rather than the die they’re stacking it vertically. That kind of 3D is already in production. It’s the question of co-mingling logic and memory that will take time. The advantage of 2.5D is that it allows afterthought. It allows you to take an existing design and to create a new set of I/Os and put in a 3D type of application.
Radojcic: I see no value in doing that. You’re creating an expensive solution to something you can do more cheaply. If you add the 3D interposer you’re adding another wafer. That’s cost. We can solve that problem with a flip chip. It’s cheaper.
Subramaniam: I disagree. We’ve done the analysis. It allows us to take an existing design, like an ARM subsystem in 28nm, even though surrounding logic doesn’t have to be at that 28nm process node. It can be 40nm or 65nm. Rather than building a new chip at 28nm, I can take my existing design, use it as one component of my 3D IC, and build a second chip in a cheaper, older technology.
Radojcic: Yes, as long as you’ve architected your chip like that, such that you can partition it.
Subramaniam: You can’t take any design, no. There has to be some partitioning in the architecture and some forethought. It’s not 100% an afterthought, but there is still some afterthought there.
Radojcic: You have to architect for it. If you haven’t done that, taking an existing chip will just cost you more. If you have done that, of course there is an avenue to doing things better and more flexibly.
Subramaniam: There is enough flexibility in designs that allow you to partition it in some manner.
Radojcic: True, but before 3D came along most of us wouldn’t have partitioned. We wouldn’t have architected it that way. To be able to leverage that value proposition, you must have 3D in mind.
Gianfagna: That’s true. It’s a premeditated act. If you don’t think it through way up front it doesn’t work.
Subramaniam: Because the SoC has a well-defined architecture, it lends itself to this type of application.
Radojcic: But only if you plan for it ahead of time.

SLD: Is this true in all cases?
Reiter: That’s the view of a high-volume supplier. I see low-volume solutions where they use an existing die, put it face down on an interposer, and connect memory to it. So for low to medium volume, 2.5D works. You call it an afterthought. I call it a customized solution.
Radojcic: Why wouldn’t you do that in a traditional multichip package?
Subramaniam: Because you don’t get the interconnectivity. The advantage of a silicon interposer is that you get thousands of interconnects.
Radojcic: But you have to design it sufficiently so you can leverage the interconnects from die to die. If you had designed for a traditional design, though, you would say, ‘I can’t have thousands of interconnects so I’m going to make a serial interface with 100 pins.’ If you take that design for a 100-pin interconnect and stick in an interposer it’s an expensive way of doing things.
Subramaniam: You may be able to take some internal signals out, which you are not able to do with a traditional MCM (multi-chip module) approach.

SLD: Let’s do a reality check. How far along are we toward stacking?
Gianfagna: Last year we had a hot-wired 3D system that was 2D with a bunch of scripts and manual effort. The customer base had strange, contrived designs and they were trying to see what they could and couldn’t do, and the foundries didn’t know what they wanted to do. A year later we have native 3D planning capability, the customer base has specific designs for implementation this year and next, and the foundries have a laser-sharp focus on process learning, mostly around 2.5D initially. If that’s a metric, things are clearer this year than last year. From an EDA perspective, I still think the market is two years away. But we still think this is big.
Reiter: If you look at the Atom chip with the FPGA from Altera, that’s basically a 2.5D solution. The FPGA is for customizing things. The Atom chip was not designed for this application.
Radojcic: But why use an interposer? Why not use a substrate and a multichip package?
Reiter: You could do that.

SLD: What’s missing from the tools side to make all this work?
Reiter: The ability to demonstrate what this technology can do is the most important capability. If you look at big corporations, top management is still hesitant to invest in this technology. If we could demonstrate in a credible way what it can do, people will be more successful in getting money to start programs using this technology.
Gianfagna: The way that happens is the early adopters blaze the trail, everyone tries to follow and the market heats up. What’s needed are commercial drivers. The tools aren’t there, but they’re close enough.
Subramaniam: The tools are not the issue. The development needed to support 3D is incremental. It can be done with the existing infrastructure. It’s really the end application.
Radojcic: Other than path-finding, which is hard to do with traditional tools. And the analysis.
Gianfagna: The complexity is higher. We’ve discovered that, too. RTL prototyping for a single chip has a certain set of challenges. When you go to 3D the modeling requirements are much greater, the constraint generation is more complicated. And we need standards. We can generate all the constraints, but we don’t know where to put them and how to express them because there is no agreed upon way to do that.

SLD: Do the standards organizations know where to start with all of this?
Radojcic: Standards are on a good track. We’ve worked with Si2 and Sematech to propose initials blasts for standards so we can feed them into Si2 and the EDA community and accelerate the process. The bits and pieces are moving, and we are on track to have a set of design exchange format standards by early next year.
Reiter: And Wide I/O.
Radojcic: Yes. The standards are channeled and the engine is revving.
Reiter: We have a bunch of players in a 3D enablement center participating. There are 15 companies listed, including Intel, IBM, TSMC, GlobalFoundries, and so on.
Radojcic: The way this was set up was Sematech said we are going to start a 3D enablement center initiative driven by the SIA. All the members of Sematech were mapped into this. Then a number of companies like Qualcomm, LSI and ASE joined.

By Ed Sperling
The semiconductor industry continues to chug along, despite global economic uncertainty, standoffs in the Eurozone, and slowdowns in Brazil and China.

eSilicon won a deal with Ikanos Communications for manufacturing operations and logistics. This isn’t the first deal of this type eSilicon has won, and it says something about how companies are coping with a disaggregated supply chain.

Mentor Graphics won a deal with China-based ZTE Mobile Telecom, which licensed Mentor’s Inflexion technology for 3D smartphone user interfaces.

GlobalFoundries certified Synopsys’ IC Validator for physical verification at 28nm, 40nm and 65nm. The goal with this stuff is to avoid last-minute surprises. In the design world, surprises are almost always bad.

Apache Design won a deal with Fujitsu Semiconductor, which adopted its Totem Software for power noise and reliability analysis. This kind of analysis is interesting at advanced nodes, but it will be critical in stacked die.

By Mark LaPedus
There may be a new hitch in moving to 2.5D stacked die—there aren’t enough suppliers of leading-edge, fine-pitch interposers.

That has put a crimp in supplies and raised prices significantly. A single interposer is reportedly selling for twice the price of a leading-edge 300mm wafer from a foundry today.

TSMC is one of the few vendors that can provide fine-pitch interposers for leading-edge designs. GlobalFoundries and UMC are readying their own offerings, but they have yet to to officially announce their technologies, according to E. Jan Vardaman, president and founder of TechSearch International, a research firm.

For some time, there has been a school of thought that the 3D chip market would evolve in two steps. First, vendors would develop 2.5D devices using silicon interposers, followed by the evolution of true 3D devices based on through-silicon vias (TSVs). But now, many experts believe that 2.5D chips using interposers will have a life of their own and will become a significant market.

Silicon interposers, at least in the initial iteration, are passive components that provide an intermediate layer between the substrate and the active device. The connections between the interposer and active device is handled through microbumps. And the connection between the interposer and packaged substrate is done via solder balls and TSVs.

“Silicon interposers are the new multi-chip modules,” said Subramanian Iyer, an IBM Fellow and chief technologist for the Microelectronics Division at IBM Corp. “They are potentially cheaper. So they are the first and very useful step in the 3D progression and will likely be adequate for a great many applications.”

At last count, there are 11 companies that supply silicon interposers, although most are not supplying fine-pitch components for leading-edge designs. Many offer larger-pitch interposers for MEMS, RF and other applications. Today’s interposer suppliers include Allvia, ASE, DNP, EPWorks, IBM, IMT, IPDiA, Silex, SPIL, STATS ChipPAC and TSMC, according to TechSearch. Others are in the planning or R&D stage, including Ibiden, Samsung Electro-Mechnical, Shinko and WLCSP, according to the firm.

The lack of supply for fine-pitch interposers is causing these components to be sold at a premium. Manish Ranjan, vice president of advanced packaging at Ultratech Inc., said the cost for a 300-mm, 28-nm wafer at a foundry is around $5,000 today. In comparison, there are reports that the interposer itself is about $10,000 alone, Ranjan said. “There are few people” that can make fine-pitch interposers, he said.

By Ed Sperling
Sonics filed suit against Arteris for infringing on network on chip patents, while Arteris rebuffed the claims. Things must be really heating up in the NoC space. http://chipdesignmag.com/sld/blog/2011/11/03/sonics-sues-arteris/

Tower Jazz’s qualified Cadence’s mixed-signal solution and PDK for its 180nm and 350nm reference flow 2.0 using bipolar CMOS-DMOS (BCD) process technologies.

ARM acquired Prolific, a startup hat develops tools for optimizing power, performance and area.

Also on the IP front, Methodics entered the Japanese market with its SoC design data and IP management platforms. Japan is one of the leading adopters of advanced EDA tools and IP.

GlobalFoundries named a new CEO, Ajit Manocha, which is rather anticlimactic. He had been serving on an interim basis since June.

And TSMC reported its Q3 numbers. Revenue decreased 4.5% sequentially from Q2, but it was up 4% from the same period in 2010. What’s particularly interesting is the breakdown. The company said 40nm and 28nm accounted for 27% of total revenues, while 65nm accounted for another 27%.