By Ed Sperling
Synopsys completed the acquisition of Extreme DA. Synopsys said the acquisition will extend its push into static timing analysis and multicore software development. Synopsys also said its USB 3.0 IP has more than 40 design wins. Sounds like we’re going to start seeing this stuff in real products soon.

eSilicon and MIPS have taped out a 28nm 1.5GHz three-processor cluster using GlobalFoundries’ 28nm SLP process. MIPS provided the RTL for its Coherent Processing System, while eSilicon performed the synthesis, timing-driven layout and optimization.

Sonics teamed up with Munich-based Lantiq to create the next-generation network for the digital home. This stuff is certainly getting easier and much, much faster. Remember what it was like to set up a home network 10 years ago?

X-FAB, the analog/mixed signal foundry, qualified Cadence’s physical verification system for all process nodes. The foundry works on geometries ranging 1 micron to 0.18 micron.

By Ann Steffora Mutschler
Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a thing of the past for most SoC design teams, and so will portability between designs.

Specifically, the ability to randomly add in new IP or substitute IP will be severely limited because the DP coloring constraints have a lot of interaction problems between cells, explained David Abercrombie, program manager for advanced physical verification methodologies at Mentor Graphics. “If the cells don’t follow the same methodology in regard to coloring boundary conditions in something as simple as an IP library of standard cells, and they know the cells are going to butt each other (share the power and ground), then because they have to be colored you can’t allow the power rail in one cell to be on mask zero and the power rail on the next cell to be on mask one. They have to end up on the same mask. So you need to enforce that all the powers have a certain coloring and all the grounds have a certain coloring.”

That all works fine in theory until someone else designs an IP library and make all of theirs zeroes. The two of those cannot be combined together. And as with all new processes, the design rules and process details are not clear.

“I’ve heard two schools of thought,” said Manoj Chacko, product marketing director at Cadence. “One school says everything will be decomposed from a cellblock IP level and designers will have to work with decomposed layouts. There is another school of thought saying, ‘Meet our rules, don’t worry about decomposing it, go through your traditional flow but you have to meet all these additional double patterning rules in addition to the traditional design rules. When you come to the end there are qualified double-patterning decomposition tools/engines that all the EDA vendors have. They can decompose it, and then there is a small iterative cycle just to ensure that you have no issues and conflicts and that this is all compliant with what the foundry has.”

But this hasn’t just happened overnight. Hans Bouwmeester, director of IP engineering at Open-Silicon, said that at 40nm, we started seeing limitations on what we could do related to the memories. “In 28nm you see more of those limitations requiring a single poly direction for the entire chip. Portability of IP becomes more and more a concern especially when it concerns analog IP. It doesn’t scale well so you don’t get the area benefits going to the deeper submicron process. So it is definitely a factor that comes more and more into play as we go into deep submicron processes.”

Since 65nm, Jean-Marie Brunet, marketing director for DFM products at Mentor Graphics, has observed a fundamental shift with respect to IP design. In the past, IP designers used to create their IP without regard to where it was going to be used and in what context. Now, with DFM lithography proximity effects, IP vendors have to design their IP knowing it will be used in context No. 1 with one chip and context No. 2 with a different chip. “Unfortunately with advanced nodes, optical radius and OPC effects, the context started to severely affect the intrinsic behavior of the IP. And that is a fundamental shift. They have to make the IP very context free, which is very difficult.”

These contextual issues call for examination of the lithography context to an IP, such as CMP effects, and analysis of contextual problems. The contextual issues get more intense the smaller the node.

Due to contextual issues and other challenges, IP re-use at 20nm with double-patterning will be very complicated. “There’s no question that at 20nm and below those are going to be very different nodes. Design flow, design methodology that we are working on right now, as well as other competitors, is going to be very difficult. I’m not too sure yet if the industry has found an easy way to do IP re-use with double-patterning. We are all going through test chips right now, validation vehicles for reference flows, and re-use of blocks. And each time we are struggling,” Brunet said.

“Solutions are being put together, but I will not say this is a done deal. We will go through issues with double-patterning. Unfortunately, it is going to be very high in cost–not only in mask and silicon, but in design flows as well. I think we’re going toward actually having severe limitations on the type of design styles and rules just because of the nature of double-patterning,” he added.

With each more advanced manufacturing node, the problem will be significantly more painful for tier-two and tier-three SoC developers, as industry players discuss in this video.

Open-Silicon’s Bouwmeester is a bit more optimistic about IP portability in the future. “I’m not completely sure whether it is going to be completely a thing of the past, but I would certainly agree that the expenses IP vendors have to take in order to port IP between foundries are going up. There is more work involved for them to bring a piece of IP they may have for example in a TSMC 28nm process to Global Foundries, and that is expected to continue or become worse as we go to more deep submicron processes. I guess there also may be more business considerations in that TSMC being the lead foundry is getting more and more protective to prevent other foundries from copying parts of their process. In other words, TSMC has a business interest in making it harder to support portability between foundries.

But Abercrombie insisted, “Even though IP vendors would sell you a library for one foundry versus a library for another foundry, honestly, we all know under the hood they built one library and it took the least common denominator. The rules were close enough that just being a little bit intelligent you could make a set that would run on either one. At 20nm and below, no. We talk to these guys and they have to build completely different, from-scratch libraries. There’s no possible way to make one. It says portability is out the window.”

It’s not all bad news, though. Navraj Nandra, senior director of marketing for analog/mixed-signal IP at Synopsys said, “If you are doing libraries and IP development you have to nowadays be early with the technology such that when customers are ready to work in these new nodes they see a bunch of IP available. We see some of these stresses early on. Some of the customers I’m speaking to at the moment are scoping out their 20 nm options—for the ones that are considering 20 nm.”

While he recognizes that IP development complications with 20nm are at least twice the complications of 28nm, he pointed out, “That’s my problem but it’s not my customer’s problem. My customers don’t care. All they care about is making sure schedules and performances are met.”

Walter Ng, vice president of GlobalFoundries’ IP ecosystem, acknowledged there is fear surrounding IP portability at 20nm. “We do see a good amount of concern among the design community with regard to the impact of double patterning on each of them and what it will mean to them and how much it will increase the complexity and difficulty of their task. We are always sensitive to that. In this case, as we go down the technology curve, it’s going to be more and more challenging to achieve the entitlement that maybe over many of the technology nodes previously has just been an expectation.”

“Double-patterning is the only way at this point that we or anybody else can achieve the 2X density that is expected. And we certainly are trying to minimize the requirement because it goes back to balance. We understand the economics of this in addition to the technical challenges, and we are trying to minimize the double-patterning requirements such that it can stay an economically viable technology node both from a processing cost as well as a design cost,” he continued.

As such, GlobalFoundries does real-time collaboration with the top EDA companies, as well as major IP providers.

On top of double patterning, Ng agreed that from an IP portability standpoint 20nm brings another challenge. “The reality among the design community is that even at 28nm, its been very challenging with regard to wanting to preserve portability where it wasn’t intended from the outset.”

“If you want to achieve optimal IP implementation, even if you wanted to try to look at a superset approach and be satisfied with ‘fat’ IP, it hasn’t been easy,” he said. “We have whittled away at the ability to easily port unless it is by design. When it comes to double-patterning and 20nm it certainly ups the bar, and it does make IP portability across random manufacturers a nearly impossible task because of certain aspects of the process definitions as well as the decomposition rules themselves. It’s not going to be the same. With the level of detail, unless it is planned for up front by design, it will be virtually impossible.”

However, he concluded, “It starts subtracting from the value statement of moving to that next technology node. If you’re going to do that superset where you’re not taking advantage of optimizing your IP and optimizing your design for a specific technology node, then you really should be considering whether you should be moving to that node because you’re just leaving so much on the table.”

It was a good week for GlobalFoundries, whose Global Technology Conference spawned a slew of announcements. Mentor Graphics teamed up with GlobalFoundries to improve yield analysis, based on Mentor’s Tessent test and Calibre DFM platforms. GlobalFoundries has been using DFM-aware yield analysis to separate design- and process-related yield limitations.

Cadence also inked a deal with GlobalFoundries to speed up DFM signoff at 28nm, integrating Cadence’s “in-design” DFM technology with GlobalFoundries’ DRC+ methodology.

Kawasaki Microelectronics, aka K-micro, licensed Sonics’ Network for AMBA Protocol (SNAP) solution for passive optical networks. SNAP is used to optimize on-chip network designs. K-micro, meanwhile, develops ASICs for delay-sensitive voice and video.

European foundry Altis Semiconductor, meanwhile, is working with Cadence to migrate and enhance its 130nm PDKs to support Cadence’s Virtuoso IC design tools.

Synopsys inked a multi-year renewal of its synthesis partnership with Achronix Semiconductor, which makes high-density FPGAs. Under the terms of the deal, Synopsys’ FPGA logic synthesis technology will be expanded to support Achronix’s 22nm chips.

By Ed Sperling
GlobalFoundries is working with Mentor Graphics on the third-generation of DFM to tie together more pieces of the design process to reduce manufacturing variability, which is a significant problem at advanced process nodes. The collaboration ties together GlobalFoundries’ manufacturing analysis and scoring methodology and Mentor’s Calibre critical feature analysis, as well as LFD kits for 28nm and 20nm, better CMP models for 28nm, and better interaction with place and route tools.

Apple, which a big driver of innovative designs and tools, has a new leader. Steve Jobs, whose iconic status makes it hard to judge the impact of his exit on the company in the short term, will be succeeded by right-hand man Tim Cook. While Apple will continue investing in its current products, the question is whether it can really dazzle the market with new products as it did with the iPod, iPhone and iPad. Time will tell. But in the meantime, there will be no shortage of speculation throughout the business press—and certainly lots of discussion about this topic inside competitor companies.

By Ed Sperling
Cadence acquired Azuro, which develops tools for clock concurrent optimization, aka coopt. Azuro claims it can reduce clock-tree power by up to 30% and overall system power by 10%. Given the increasing number of clocks in SoC designs, this can only be a good thing. Terms of the deal were not disclosed, meaning it wasn’t significant enough as a percentage of Cadence’s revenue to actually report.

For anyone who’s been contemplating the future of double patterning, strain engineering and eventually stacking of die, this stuff is no longer just theoretical. Samsung used Cadence’s Encounter-based flow to tape out a 20nm test chip. Samsung also used Synopsys’ IC Compiler and IC validator for in-design physical verification to get that test chip out.

Synopsys also is working with GlobalFoundries to deliver interoperable process design kits later this year at advanced nodes. 65nm G and enhanced low power (LPe) kits are available now.

Cavium licensed Arteris’ FleNoC interconnect IP for its processors. Given the complex interconnect tradeoffs in an SoC, this is a recognition by a mainstream processor company of how to deal with trouble spots in the future, namely plan for them.

Germany’s Dream Chip Technology inked a deal to become a Tensilica design center, supporting Tensilica’s processor core IP. Dream Chip makes SoC, FPGA and embedded software designs.

TSMC’s net sales shrank 0.9% between May and June, but they were up 1.5% year over year for that period.

By Ann Steffora Mutschler
In the race to get products to market with shortening product cycles, steepening the ramp to yield is critical. The introductory phase of a product is the point at which margins are highest and market share can be most easily gained.

This is no surprise to chipmakers. What is surprising is just how much more difficult it has become to achieve acceptable yield quickly, particularly at advanced process nodes. And that’s true even with restrictive design rules, the most advanced tools and the best methodologies and engineers. Still, for most large chipmakers, not meeting early deadlines with sufficient yield isn’t an option.

“That’s the sweet spot for profitability,” said Joe Swenton, architect for Encounter Diagnostics at Cadence Design Systems. “The sooner you can ramp to volume is becoming more than just profitability. In some cases it’s becoming a business imperative. You’re not going to stay in business unless you learn how to do this.”

As a result, IDMs already have integrated diagnosis-driven yield analysis—also referred to as volume diagnostics—while fabless companies are in an earlier stage of adoption. The primary usage of volume diagnostics is for yield ramp: accelerating yield learning to decrease the time required to achieve nominal yields for high-volume devices. In that environment, users may be running thousands of failing die through diagnostics per day to identify systematic yield limiters that are becoming more prevalent in the smaller geometries.

Traditionally what people have done to address yield is look at a lot of data from a lot of different sources, primarily from the manufacturing end of the process, using technology such as in-line inspection where pictures are taken of the devices as they are in different stages of production, explained Geir Eide, product manager for yield analysis at Mentor Graphics.

After that, high-level test results are used to determine, for instance, if the logic passed but more of the memory is failing than is normal. “When there seem to be more types of a particular type of failure, then people would normally go into a process of failure analysis where you basically look at some individual parts—say, a handful of parts. And depending on what you think the problem is, you would use different types of microscopes and equipment, or very often, physically slice and dice the chip to de-layer it in order to get to the source of the problem, then take a picture of it,” he said.

The problem is that as chips get bigger, line widths get smaller, and everything is faster, there are some challenges in the failure analysis process. “You definitely want to find the defect, but even if you find a defect for that part you are looking at, do you know if that particular part represents a problem you can solve? In other words there’s always, and especially when you are ramping up there are usually many different problems happening at the same time,” Eide pointed out.

Diagnosis-driven yield analysis is about trying to find a better way to identify any systematic issue before failure analysis and select better devices for failure analysis.

Specifically, this is done by using diagnosis, which is a way to analyze production test results to find out what’s going on with each failing device. From there, the test team tries to learn from the test results where the defect is located and also what type of defect it is—whether it behaves like a bridge between two nets, or an opening, or whether it is a defect in an interconnect or internal to these different logic cells on the design.

Not new technology
This is hardly a new concept, of course. “People have been doing it since the beginning of our industry,” said Sagar Kekare, group manager for product marketing of manufacturing yield management at Synopsys. “As the complexity of yield-limiting failure mechanisms kept increasing, at some point, the tests that give you an idea into something that yields or something that doesn’t had to become more complex and you couldn’t use just the test data to say this is where the failure is. That’s where people started thinking about test slightly differently. They went from functional tests into structural tests—DFT and ATPG. Diagnosis is basically the key benefit on the yield front from the DFT and ATPG approach in addition to other benefits including coverage, the quality of test—all are high benefits of DFT and ATPG.”

From a yield analysts’ perspective, being able to diagnose the test data and triangulate the failure to a spot or a few candidate spots was a big advantage of a DFT/ATPG structural test approach. “People have been looking at diagnostics to do this job in yield learning for a few years now. It’s not something very new,” Kekare continued.

Diagnosis can reveal what happened to a single failing device, while yield, on the other hand, is a statistical distribution. What has happened in the last 2-1/2 to 3 years is that test teams needed to go beyond understanding what was happening to one chip that failed to determining why they were only getting 60% yield, for example. Going from diagnosing a single failed device to looking at it as an entry into statistical analysis is new.

Kekare believes the tipping point occurred when the 90nm/65nm nodes started getting more production usage. He pointed out that sub-100nm nodes have a very strange behavior in terms of manifesting design process interaction issues. “These design process interaction issues really are for yield analysis people an unhappy marriage of what was in the design to begin with, a marginal element or a marginal path, with whatever is the process marginality in the fab.”

These issues just increase going into the smaller nanometer node technologies but there is no clear indicator as to where they are. This was the impetus for test engineers started bringing data from wafer inspections together with diagnosis.

Cadence’s Swenton agreed. “Volume diagnostics has been a useful tool for a number of years but it’s really catching on as more of a requirement due in part to the shrinking geometries and the fact that traditional in-line inspection methods are becoming less useful because of the non-visual nature of defects. It’s critical to be able to run as many failing die as you can afford to. Obviously it needs to be a statistically significant sample size, and this is done for both logic diagnostics and chain diagnostics used in volume.”

Added Mentor’s Eide: “You know that of 100 defective devices you see, that 90 of them are diagnosed to have a defect in the same net. Then you know just from that location that most likely those 90 must have something in common.”

But if every device is diagnosed in a different location, by adding layout-aware diagnosis you can get the location as well as a better idea of the type of defect and what kind of physical features are part of that net segment where the defect is believed to be. If a particular type of via or logic gate is associated with each of these defects, even if they are in different locations, then you know what they have in common. That part is new. Also what is new is this second step in the process, which is to then provide more sophisticated way of analyzing these diagnosis results.

The analysis is done by combining a few things. Given that engineers by nature like to do what they have done before, it is about representing the more detailed information in the same way they are used to seeing it before. As such, wafer maps and Pareto diagrams are used, but with more data.

In a recent presentation, GlobalFoundries and Mentor showed a few case studies from some of their test chips:

Source: “Optimizing Yield and Performance in a Nanometer World”, Thomas Herrmann, GLOBALFOUNDRIES and Geir Eide, Mentor Graphics.

Fabless Adoption Starting to Rise
While adoption for diagnosis-driven yield analysis has been strong in the IDM space, fabless companies are just starting to put together yield-learning teams.

“The adoption rate among IDMs I would say is near 100%, and among the fabless entities, just like any other new thing that we ask fabless team to do, it starts with some of the top-level, marquee accounts—graphics processor guys, cell phone guys, and then it starts percolating down to others. We’ve seen the same kind of trend here also in adoption of volume diagnostics. Most of the IDMs already are doing volume diagnostics one way or another, either a commercial solution or they’ve built some solution in-house held together by scripts and things like that. But they are all doing it in one form or another. The big fabless companies are doing it, but the medium and smaller fabless are just beginning to hear about it and possibly try it out in one or two off situations,” according to Synopsys’ Kekare.

Yield hasn’t been a core competency of fabless companies because it was always something that the foundry would handle. The idea that the design team has to get more intimately involved in managing and improving yields is still a bit new.

This is why the technology is also referred to as design-centric yield analysis or design-centric volume diagnostics, because design teams need to get involved today in a different way than they did in the past. Today, design teams need to know if there are any strong effects that are limiting either the yield or the performance of the newly taped out device that are coming from design steps. They can originate in the use of design elements like standard cell libraries or via structures that are developed by the foundries, use of recommended rules from the foundries, or different teams are designing different blocks in the design and they use slightly different styles in designing those blocks.

“These are issues foundries cannot answer, and that’s why design teams are also seeing more and more need to get in, even though there is the hesitation because of this history of foundries taking care of yield issues. But there is also the realization that this requires use of a lot of design data and me as a fabless, I’m not comfortable giving all this data to the foundry,” he said.

Test approach needs adjustment
At the same time, you can’t really have a free lunch, Kekare reminded. “You want to be able to diagnose the dies, you need good data coming out of the testers to use for diagnosis and most often, the approach to testing has been stop on fail.”

But this approach is flawed, he argued. “What happens is that you save the time on the tester…but what you save on the tester utilization cost, you lose on your ability to trace the sources of this failure and figure it out quickly.”

The yield teams and the test teams need to agree that at least when ramping up the product, they will abandon the ‘stop on fail’ approach, and instead use a ‘continue on fail’ approach so that all the tests are completed. This means that even after the first test fails, the second and successive tests will be run. “All this data is really important to do the triangulation and localization of the failure. So what you lose in that test cost, you are going to gain multiple fold back in the ability to figure out where the failures are and solve them quickly. This is a conceptual decision that needs to be done by the teams early on,” Kekare added.

Leveraging Existing Structures, Patterns
Interestingly, the diagnosis-driven yield analysis process primarily leverages design for test (DFT) structures and the production test patterns that are already there and which serve as the foundation for this flow, Mentor’s Eide noted. “The basic principles are already there, but when it comes to practical implementation it’s mostly about data management—basically making sure that the actual files you need to run diagnosis are actually available when you want to do diagnosis.”

In theory, pretty much everybody has the data, he said, and it’s more about how to use it.

For instance, diagnosis happens when devices are actually manufactured and part of what is used for the process is the actual design description. “Part of the power here is that when we go through this process we have all the design information so we can find design-specific problems more so than, let’s say, the traditional methods that are more fab-centric. But then again, in the old days, once you had sent your design files to the foundry and it got manufactured, you could basically forget about the design files and put them on a tape somewhere. Now we need those files six months later,” Eide said.

It comes down to having the data available from design, and the test results from the tester as the basic infrastructure to enable it. In terms of the actual information it is pretty much already there; it’s about managing it.

By Ed Sperling
MIPS has positioned itself head-to-head with ARM in the Android world, adding yet another competitor. The other one is Intel’s Atom, of course. MIPS stake on this one involves a smartphone that passed the Android Compatibility Test Suite.

Moortec Semiconductor taped out its embedded temperature sensor IP using TSMC’s 40LP and 28HP processes and Synopsys’ custom design solution. Who says analog isn’t migrating down the process curve? Moortec is based in Plymouth, U.K. 8

TSMC’s net sales, which are a good indication of how the semiconductor industry is faring, were down 0.7% from April to May—basically flat—but they are still up 6.3% from last May, which was well into the recovery period. Revenue was up 12.2% in the same period compared with 2010.

GlobalFoundries, meanwhile, swapped out its top leadership team. Ajit Manocha will replace Doug Grose as acting CEO. James Norling will become executive chairman and Ibrahaim Ajami the vice chairman, while COO Chia Song Hwee—former CEO of Chartered Semiconductor, which was acquired by GlobalFoundries—will leave the company in August.

By Ed Sperling

Sonics rolled out a new rapid-configuration environment for network-on-chip technology called StudioXE. The new tool relies on a system-level design approach to simplify deployment and changes at any point in the flow.

Open-Silicon struck a deal with memory maker Micron to explore opportunities around Micron’s new Hybrid Memory Cube, focusing initially on data networks and high-performance computing.  Open-Silicon also is working with GlobalFoundries on 28nm super-low-power technology, which combines body biasing with high-k/metal gate technology.

Magma likewise struck a deal with GlobalFoundries for the same process, this one for its Talus signoff reference flow tools.

By Ed Sperling
A power shift is under way across the SoC world that ultimately determine who wins the business, who gets the biggest share and what technologies are ultimately used to get there.

Complexity has reached a point where being able to pull the necessary pieces from a disaggregated supply chain is becoming much more difficult. That helps explain why all three of the major EDA companies now offer IP in addition to a slew of adjacent services. It also explains why Intel acquired Wind River and why Apple is now re-aggregating into a vertically integrated device manufacturer.

This complexity began rearing its head at 65nm, when issues such as power, silicon stress and third-party IP integration became rampant. At 28nm there are other physical effects to consider, and at 20nm and into stacked die there are a slew of other issues ranging from packaging, power budgeting, modeling, more complicated test and complex IP integration—to name a few.

Normally this would force re-aggregation of a supply chain, and there are some examples of this happening, but the economics of reaggregation are unusual in an industry where building a state-of-the-art fab now costs upward of $5 billion and where a large 100 million-gate design can pass the nine-digit mark for the first time.

“Most industries would vertically integrate at this point,” said John Bruggeman, chief marketing officer at Cadence. “But in this industry the economics of the different segments are so dramatic that vertical integration will not solve the economic issues. It would solve the technology issues.”

Within that framework, much tighter groups will emerge—cabals is probably a more accurate term—of large companies with deep pockets sharing common interests. They also will share much more of their technological know-how with each other, something that they currently refrain from doing in the design world for fear of theft of corporate secrets. Bruggeman said this is only beginning in the design sector at 28nm, but at 20nm or 14nm it will become necessary for survival.

“You will see power battles emerge, but they won’t be effective groupings until they realize no one will be the general contractor. There will be two main ecosystems—star IP and foundries—and EDA will connect them together. Companies like ARM cannot connect to TSMC without EDA.”

Foundry battles
Much of what will unfold will mirror what has happened on the manufacturing side, where foundries have set up their own ecosystems. The most complex one is the Common Platform and the Fishkill Alliance, which were started by IBM largely as a way of spreading out the very expensive process development across a number of companies that had deep enough pockets or technological expertise to contribute something.

The core members of the Common Platform—GlobalFoundries, Samsung and IBM—have been building up their expertise for next-generation chip manufacturing since the 90nm process node. TSMC has formed its own smaller ecosystem for similar reasons, striking up strong relationships with EDA companies.

It remains to be seen how those collaborative efforts will fare, however, against Intel’s vertically integrated model. Intel’s announcement that it will introduce FinFETs at 22nm—probably later this year—has set the whole manufacturing sector abuzz about whether the technology will be manufacturable, whether it will offer promised gains in power savings and performance, and whether their own developments will be competitive. Intel’s FinFET rollout is about two process nodes ahead of schedule.

Stacking effects
The other kind of 3D—stacked die, whether using an interposer or a TSV—is likely to create new issues about who owns what. Two good die may equal one bad stacked die, which is a problem when they are being put together. Heat, thinner substrates and noise can all have disastrous effects on signal integrity and performance.

“There is an issue of who owns the problem,” said Sunil Patel, principal member of the technical staff at GlobalFoundries. “We have not productized any of this yet, so it will all be played out over time.”

He noted that a much closer collaboration will be necessary. “This is not the old model of a GDS-II file where you expect a fully functioning package. It may not work. We all have to work together on what is now a back-end process. That’s a different relationship between customers and foundries. We have to understand the key deliverables for every die.”

Software vs. hardware
There has been much talk about who’s going to be in control of designs, hardware or software engineering teams. The answer is probably both.

Bridging hardware and software design sounds logical enough on paper, but more than a decade after this idea first began receiving attention it has achieved only modest success. So what’s holding up the process?

The real challenges stem from a rather complex combination of technology and business. While there is plenty of reason to align hardware and software development much more closely from a system-level standpoint—it can certainly improve performance and boost energy efficiency, for example—some key pieces have been missing.

“The software guys are used to getting a static hardware model,” said Mike Gianfagna, vice president of marketing at Atrenta. “There needs to be a balancing of software and hardware, but some of the pieces still need to be developed. We need modeling and simulation for both. We don’t believe a hardware-centric world will be successful. The software guys need to help drive architectural decisions. That is a new opportunity for both sides.”

He noted that software engineers currently have no way to communicate their concerns back to the hardware team. “What if you could take a generated model and send back the list of what they did and didn’t like and 24 to 48 hours get a new design? That would make a big difference.”

It also would help ease some of the stress about who should be in charge and how communication will work across disciplines that don’t necessarily speak the same language.

Make vs. buy
The other piece of the puzzle in a control shift is what actually gets used in a design. With IDMs such as Intel and Apple, there’s no question about who owns the design and who makes the pieces. For the rest of the industry that isn’t the case.

“We’re seeing a value inversion,” said Jack Harding, chairman and CEO of eSilicon. “The best companies can’t understand what other companies are doing unless it’s their job to know. For most companies, do-it-yourself is dead. No one can make one 28nm chip a year and be successful at it. You may come up with a solution, but it very likely will be sub-optimized.”

What’s interesting about this model—one shared by companies such as eSilicon, Open-Silicon and Global Unichip—is that the expertise is shifting from companies that design the chips to companies that actually put them together. The designers don’t work closely enough with the assembly to understand the intricacies of the technology, and the cost of developing the IP and subsystems is too high.

Stacking of die potentially removes that level of understanding by an entire die, which ultimately will be bought and sold as a complete, integrated subsystem. In that case, the real value may be less about the individual pieces of the technology and more about the tradeoffs between business and technology. Companies that get this right may be the biggest beneficiaries, while companies that develop the technology in a crowded market may find their market position severely eroded.

Conclusion
The changes that will be wrought over previous process nodes were mostly about technology—putting more on a chip, using technology to add unbelievable complexity and push the limits of physics. The next wave of changes will be as much about the intersection of business and technology as about advancing Moore’s Law.

As these changes unfold, there will be winners and losers, and there will be some companies squeezed out while others gain a toehold, a foothold, or win market dominance. But as these worlds converge—hardware, software, manufacturing, merchant IP and the business of all of these the semiconductor design market will be redefined for the next phase of growth. In some respects this is a normal business cycle, but change is always unsettling, unexpected and not of equal benefit to everyone.

By Ed Sperling
Mentor Graphics inked a deal with GlobalFoundries to extend its computational lithography to 28nm. The technology helps bridge the gap between 193nm lithography and EUV, which still isn’t ready for prime time despite years of promises and hype. Mentor also rolled out the next generation of its Questa integration and verification platform.

Cadence extended its own verification IP catalog, which most chip companies now consider a vital technology for verifying third-party IP blocks. This will be an interesting move to watch over time because it simplifies the make vs. buy decision for chipmakers in the verification space. While many companies say they see value in VIP, in the past they have been reluctant to pay for it.

Synopsys introduced new IP for the final release of PCI Express 3.0, including a new DMA engine and support for a 256-bit datapath. The company also introduced Proteus LRC for lithography verification at 28nm and below.  And it pushed deeper into the FPGA space with a methodology manual for FPGA-based prototyping jointly developed with Xilinx, and the availability of its HAPS-600 prototyping solution.

Arteris teamed up with CEVA on multicore interconnect technology for CEVA’s DSP cores. CEVA also has licensed Arteris’ FlexNoC interconnect technology.