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Cadence Launches New Verification Solutions

Tuesday, March 14th, 2017

Gabe Moretti, Senior Editor

During this year’s DVCon U.S. Cadence introduced two new verification solutions: the Xcelium Parallel Simulator and the Protium S1 FPGA-Based Prototyping Platform, which incorporates innovative implementation algorithms to boost engineering productivity.

Xcelium Parallel Simulator

.The new simulation engine is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, internet of things (IoT) and automotive projects.

The Xcelium simulator offers the following benefits aimed at accelerating system development:

  • Multi-core simulation improves runtime while also reducing project schedules: The third generation Xcelium simulator is built on the technology acquired from Rocketick. It speeds runtime by an average of 3X for register-transfer level (RTL) design simulation, 5X for gate-level simulation and 10X for parallel design for test (DFT) simulation, potentially saving weeks to months on project schedules.
  • Broad applicability: The simulator supports modern design styles and IEEE standards, enabling engineers to realize performance gains without recoding.
  • Easy to use: The simulator’s compilation and elaboration flow assigns the design and verification testbench code to the ideal engines and automatically selects the optimal number of cores for fast execution speed.
  • Incorporates several new patent-pending technologies to improve productivity: New features that speed overall SoC verification time include SystemVerilog testbench coverage for faster verification closure and parallel multi-core build.

“Verification is often the primary cost and schedule challenge associated with getting new, high-quality products to market,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Xcelium simulator combined with JasperGold Apps, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform offer customers the strongest verification suite on the market”

The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Protium S1

The Protium S1 platform provides front-end congruency with the Cadence Palladium Z1 Enterprise Emulation Platform. BY using Xilinx Virtex UltraScale FPGA technology, the new Cadence platform features 6X higher design capacity and an average 2X performance improvement over the previous generation platform. The Protium S1 platform has already been deployed by early adopters in the networking, consumer and storage markets.

Protium S1 is fully compatible with the Palladium Z1 emulator

To increase designer productivity, the Protium S1 platform offers the following benefits:

  • Ultra-fast prototype bring-up: The platform’s advanced memory modeling and implementation capabilities allow designers to reduce prototype bring-up from months to days, thus enabling them to start firmware development much earlier.
  • Ease of use and adoption: The platform shares a common compile flow with the Palladium Z1 platform, which enables up to 80 percent re-use of the existing verification environment and provides front-end congruency between the two platforms.
  • Innovative software debug capabilities: The platform offers firmware and software productivity-enhancing features including memory backdoor access, waveforms across partitions, force and release, and runtime clock control.

“The rising need for early software development with reduced overall project schedules has been the key driver for the delivery of more advanced emulation and FPGA-based prototyping platforms,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Protium S1 platform offers software development teams the required hardware and software components, a fully integrated implementation flow with fast bring-up and advanced debug capabilities so they can deliver the most compelling end products, months earlier.”

The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Blog Review – Monday, September 26, 2016

Monday, September 26th, 2016

Robotic surgery reaches new levels, and ARM raises safety critical benchmarks with Cortex-R52, supported by Synopsys tools. There is a preview of Intel’s DVCon Europe’s presentation for virtual systems and DTF proves to be a classic rulebook.

Described as a ‘fairy tale’ by the grateful recipient, surgeon using a joystick to remove a membrane from the patient’s eye could sound like an Orwellian nightmare, but Tom Smithyman, ANSYS, has collected his favorite blogs, one of which is on the BBC website and explains how surgeons at the John Radcliffe Hospital performed robotic-assisted eye surgery.

You may have heard that ARM launched its Cortex-R52, ARMv8-R processor and hot on the heels of the announcement, Synopsys has announced design support for safety critical automotive, healthcare and industrial applications, reports Phil Dworsky, Synopsys.

Still with ARM, Rob Coombs, explains how mobile security architecture can be adapted for IoT applications, with copious graphics and an introduction to TrustZone for ARMv8-M on microcontrollers.

The more things change, the more they stay the same, can be the conclusion reading a blog by Stephen Pateras, Mentor Graphics, who shows that DFT-related rules hold true now, as they did in the 1980s.

Is a coup is in the offing at the IEEE? John Blyler Systems Design Engineering, makes sure of the facts by checking with the current President-Elect, Karen Bartleson about the proposed amendment to the IEEE constitution ahead of next month’s vote.

DVCon Europe 2016 takes place in the German city of Munich next month and Jakob Engblorn, Intel, will present a paper there based on integrating SystemC models into a virtual system. For those who can’t attend in person, his blog previews his technical and informative paper.

Caroline Hayes, Senior Editor

Blog Review – Monday, January 26 2015

Monday, January 26th, 2015

Finding fault tolerances with Cortex-R5; nanotechnology thinks big; Cadence, – always talking; mine’s an IEEE on ice; IP modeling

The inherent fault tolerance ARM’s Cortex-R5 processors is explored and expanded upon by Neil Werdmuller, ARM, in an informative blog. Reading this post, it is evident that it is as much about the tools and ecosystem as the processor technology.

Nanotechnology is a big subject, and Catherine Bolgar, Dassault Systemes, tackles this overview competently, with several, relevant links in the post itself.

Harking back to CES, Brian Fuller, Cadence, shares an interesting video from the show, where Ty Kingsmore, Realtek Semiconductor, talks the talk about always on voice applications and the power cost.

A special nod has to be given to Arthur Marris, Cadence, who travelled to Atlanta for the IEEE 802.3 meeting but managed to sightsee and includes a photo in his post of the vault that holds the recipe for coca cola. He also hints at the ‘secret formula’ for the 2.5 and 5G PHY and automotive proposals for the standard. (Another picture shows delegates’ tables but there were no iconic bottles to be seen anywhere – missed marketing opportunity?)

In conversation with leading figures in the world of EDA, Gabe Moretti, considers the different approaches to IP modeling in today’s SoC designs.

By Caroline Hayes, Senior Editor.

Accellera Systems Initiative Continues to Grow

Thursday, October 17th, 2013

By Gabe Moretti

The convergence of system, software and semiconductor design activities to meet the increasing challenges of creating complex system-on-chips (SoCs) has brought to the forefront the need for a single organization to create new EDA and IP standards.

As one of the founders of Accellera, and the one responsible for its name, it gives me great pleasure to see how the consortium has grown and widened its interests.  Through the mergers and acquisitions of the Open SystemC Initiative (OSCI), Virtual Sockets Interface Alliance (VSIA), The SPIRIT Consortium, and now assets of OCP-IP, Accellera is the leading standards organization that develops language-based standards used by system, semiconductor, IP and EDA companies.

As its original name implies, Accellera is Italian meaning accelerate, its activities target EDA tools and methods with the aim of fostering efficiency and portability.

Created to develop standards for design and verification languages and methods, Accellera has grown by merging or acquiring other consortia, expanding its role to Electronic System Level standards, and IP standards.  It now has forty one member companies from industries such as EDA, IP, semiconductors, and electronics systems.  As a result of its wider activities it even its name has grown and now is “Accellera Systems Initiative”.

In addition to the corporate members Accellera has formed three Users Communities, to educate engineers and increase the use of standards.  The Communities are: OCP, SystemC, and UVM.  The first one deals with IP standards and issues, the second supports the SystemC modeling and verification language, while the third one works on Unified Verification procedures.

Accellera has 17 active Technical Committees.  Their work to date has resulted in 7 IEEE standards.  Accellera sponsors a yearly conference DVCON held generally in February but also collaborates with engineering conferences in Europe and Japan.  With the growth of electronics activities in nations like India and China, Accellera is considering a more active presence in those countries as well.

Chip and System Reliability Experts Assemble

Tuesday, March 28th, 2017

The annual International Reliability Physics Symposium (IRPS) expands system reliability coverage to complement traditional microelectronics focus.

By John Blyler, Editor-in-Chief, Journal of Reliability, Maintainability and Supportability in Systems Engineering

Systems reliability continues to grow as an important subject at the 2017 IEEE International Reliability Physics Symposium (IRPS), which starts on April 2nd in Monterey, CA. The 54 year old symposium covers the range of reliability physics concerns for current technologies and “continues to explore the connection between transistor physics of failure and system reliability.” For the latter, this year’s topics will include discussions on functional clones, telemetry, COTS, physics- and data-driven models, and organizational impacts on reliability. Here’s a brief summary of each:

Today’s Functional Electronic Clones

“The most worrisome aspect of “made from scratch” fakes is their ability to easily pass current inspection processes and electrical testing to the manufacturer’s data sheet. Advanced counterfeiters today are performing both “reverse-engineering” and “functional-die-emulation” manufacturing processes.” — Tom Sharpe, SMT Corporation

Telemetry for Reliability

“Knowledge-based qualification (KBQ) of integrated circuit (IC) products includes predicting product failure in the field over time for failure mechanisms. Field failure depends on product usage, and more directly on the use conditions (UCs) associated with usage, such as time at voltage and temperature which are direct inputs to failure models. … One method to acquire UC data is to measure product UCs on a test system in a lab environment while executing benchmarks and workloads which represent user behavior. Another method is to acquire UC data from users in the field by telemetry using software-based collectors installed on the users’ systems.” — R. Kwasnick, et al, Intel

NASA Past, Present, and Future: The Use of COTS in Space

“NASA has a long history of using commercial grade electronics in space. In this submission, we will provide a brief history of NASA’s trends and approaches to commercial grade electronics focusing on processing and memory systems. This will include providing summary information on the space hazards to electronics as well as NASA mission trade space. We will also discuss developing recommendations for risk management approaches to Electronic and Electromechanical (EEE) parts usage in space.  Two examples will be provided focusing on a near-earth Polar-orbiting spacecraft as well as a mission to Mars. The final portion will discuss emerging trends impacting usage.” — Kenneth A. LaBel, Steven M. Guertin, NASA

Hybrid Physics Based-Data Driven Approach for Reliability Allocation of Early Stage Products

“This paper presents a novel approach for reliability demonstration of a product operating in dynamic time varying environment. The device is subjected to mechanical loads, humidity and temperature swings whose magnitude is uncertain a-priori. The primary goal of this paper is to extract mission profile from field data. A second goal is to design accelerated reliability tests that accurately represent field conditions.” — Amit A. Kale, Amit Marathe, Jiayuan Meng, Ajay Kamath, Matt Rogge, Ali-Reza Bahmandar, Google

[Editor’s note: For me, the keywords here are “physics and data based” modeling approaches. The data-based inputs add a degree of real-time variation to the traditional physics-base equations.]

Reflections on the risk of human space exploration – lessons learned from past failures

(First Keynote) “… Studying the lessons learned from the Challenger and Columbia accidents, as well as similarities in those two tragedies, provides a prospective of cultural, organizational, and management failures that can occur in any engineering organization managing extremely complex systems operated in high risk environments.” — Dr. Nancy Currie-Gregg NASA Astronaut; Principal Engineer, NASA Engineering and Safety Center

Apple vs Qualcomm. It Is More Than Money

Wednesday, February 1st, 2017

Gabe Moretti, Senior Editor

On the surface the various legal actions by the Korean and US governments as well as Apple against Qualcomm appear to be about money, or how to split revenue from product that uses a standard that Qualcomm helped to develop.  But there is more to the suit.

The Background

I t would be impossible to grow an industry without standards that make it possible for various portion of the industry to cooperate and allow tools and methods to work together.  To this end that are organizations that develop, distribute, and manage such standards.  The IEEE is the one most familiar in the US.  Qualcomm and Apple are both members of ETSI, an SSO based in Sofia Antipolis, France, which includes more than 800 members from countries across five continents. ETSI produces globally accepted standards for the telecommunications industry. For example, ETSI created or helped to create numerous telecommunication standards, including the 2G/GSM, 3G/UMTS, and4G/LTE cellular communication standards.

Developing a standard requires the contribution of Intellectual Property (IP) by entities, usually corporate entities, universities, or other research organizations.  Offering IP without restrictions would, almost always, hurt the offering entity financially, so a legal tool that protects it has been developed.    For patents that companies have declared “essential” to the standard, patent law is reinforced by contractual obligations to license such patents on Fair, Reasonable, And non-Discriminatory commitments.  The legal wording of the tool is called a FRAND (or RAND) commitment.  The entire issue revolves around the definition of the term “Reasonable”.  In a meeting on February 2015 the IEEE defined the term as follows:

“Reasonable Rate” shall mean appropriate compensation to the patent holder for the practice of an Essential Patent Claim excluding the value, if any, resulting from the inclusion of that Essential Patent Claim’s technology in the IEEE Standard. In addition, determination of such Reasonable Rates should include, but need not be limited to, the consideration of:

  • The value that the functionality of the claimed invention or inventive feature within the Essential Patent Claim contributes to the value of the relevant functionality of the smallest saleable Compliant Implementation that practices the Essential Patent Claim.
  • The value that the Essential Patent Claim contributes to the smallest saleable Compliant Implementation that practices that claim, in light of the value contributed by all Essential Patent Claims for the same IEEE Standard practiced in that Compliant Implementation.
  • Existing licenses covering use of the Essential Patent Claim, where such licenses were not obtained under the explicit or implicit threat of a Prohibitive Order, and where the circumstances and resulting licenses are otherwise sufficiently comparable to the circumstances of the contemplated license.

The licensing assurance shall be either:

  • a) A general disclaimer to the effect that the Submitter without conditions will not enforce any present or future Essential Patent Claims against any person or entity making, having made, using, selling, offering to sell, or importing any Compliant Implementation that practices the Essential Patent Claims for use in conforming with the IEEE Standard; or,
  • b) A statement that the Submitter will make available a license for Essential Patent Claims to an unrestricted number of Applicants on a worldwide basis without compensation or under Reasonable Rates, with other reasonable terms and conditions that are demonstrably free of any unfair discrimination to make, have made, use, sell, offer to sell, or import any Compliant Implementation that practices the Essential Patent Claims for use in conforming with the IEEE Standard. An Accepted LOA that contains such a statement signifies that reasonable terms and conditions, including without compensation or under Reasonable Rates, are sufficient compensation for a license to use those Essential Patent Claims and precludes seeking, or seeking to enforce, a Prohibitive Order except as provided in this policy.

The ETSI interpretation of “reasonable” is essentially the same as that of the IEEE.

The Apple Claim

Apple filed a claim in the US District Court in Southern California against Qualcomm.  The entire claim is exactly 100 pages long, so I am reporting only the key elements of it.  It is a fact that Qualcomm produces and licenses to semiconductor companies designs that implement connectivity between a device and the network that uses 3G or 4G standards.  Intellectual property of Qualcomm that is protected by patents was offered to ETSI in the development of both standards under the Essential Patent Claims and therefore it falls within the FRAND rules.  Apple’s claim states:

The description of the FRAND arrangement in the official claim is worth reading even if some of the terminology is slightly different from the usual ones used in our industry.

“Like other SSOs, ETSI requires participants to commit to abide by its Intellectual Property Rights (“IPR”) Policy, which sets forth the rights and obligations of its members. Pursuant to the IPR Policy, members are required to disclose standard-essential and potentially standard-essential patents and patent applications in a timely fashion. [ETSI Rules of Procedure, Annex 6, Clause 4.

The IPR Policy further requires that SEP owners submit a written commitment that they are prepared to grant irrevocable licenses on FRAND terms. If no FRAND commitment is made, the IPR Policy provides for ETSI to investigate alternative technology options for the standard to avoid the patent in question.

According to ETSI’s self-reporting portal, Qualcomm has declared over 30,000 global assets to be “ESSENTIAL IPR.” No objective party has tested the actual essentiality or validity of these assets.

Qualcomm has submitted IPR undertakings to ETSI with regard to each of the patents at issue in this matter. By submitting those declarations, Qualcomm promised that “[t]o the extent that the IPR(s) . . . are or become, and remain ESSENTIAL in respect of the ETSI Work Item, STANDARD and/or TECHNICALSPECIFICATION,” Qualcomm is “prepared to grant irrevocable licenses under this/these IPR(s) on terms and conditions which are in accordance with Clause 6.1of the ETSI IPR Policy.

Qualcomm, therefore, is contractually obligated to grant licenses on FRAND terms to these patents to Apple and other manufacturers of products that, through the baseband processor chipsets they use, conform to ETSI standards, as well as to third-party suppliers of baseband processor chipsets. Qualcomm made similar promises to other SSOs as well.

Because Apple is a third party that wishes, through the baseband processor chipsets it uses, to implement 3G/UMTS and 4G/LTE standard-compliant technology in the products it sells, Apple is a third-party beneficiary of the contracts between Qualcomm and ETSI.

Apple relied on Qualcomm’s promises to ETSI. Specifically, Apple and other wireless device manufacturers made a conscious choice to develop and sell products compatible with 3G/UMTS and 4G/LTE, relying on Qualcomm’s promise hat any third-party supplier of baseband processor chipsets or products using them could avoid patent litigation and obtain a license to any patents that Qualcomm has declared essential to the 3G/UMTS and 4G/LTE standards.

Qualcomm’s breach of its FRAND commitments, described insignificant detail below, is a foundation of its scheme to acquire and abuse monopoly power in the cellular industry.”

The claim also describes how the FRAND rule is to be implemented.

“FRAND royalties must start with the proper royalty base and a proper royalty rate, as required by the patent laws, but also must meet additional criteria designed to prevent misuse of the monopoly power conferred by adoption of a standard. In particular, FRAND royalties must be limited by the actual technical contribution of the patented technology to the standard, rather than (a) the “lock-in” value that arises from standardization of technologies, i.e., the value gained simply because companies are forced to use the technology mandated in the standard,(b) the value of all the technologies incorporated in an entire standard, or (c) the competing value of the many technologies, and many other standards that make up the actual device.”

Later the claim states:

“Qualcomm broke its promise and has breached its FRAND commitments. Qualcomm illegally double-dips by selling chipsets that allow mobile telephones to connect to cellular networks and then separately licensing (but never to competitors) the purportedly necessary intellectual property. By tying together the markets for chipsets and licenses to technology in cellular standards, Qualcomm illegally enhances and strengthens its monopoly in each market and eliminates competition. Then, Qualcomm leverages its market power to extract exorbitant royalties, later agreeing to reduce those somewhat only in exchange for additional anticompetitive advantages and restrictions on challenging Qualcomm’s power, further solidifying its stranglehold on the industry.”

Issues to Consider

The first thing to be realized is that this claim is about how to share revenue, not about standard making processes.  Apple wants a larger share of revenue from the sale of its product, while Qualcomm wants to protect what it gets right now by re-defining how royalties are computed.  Yet, there are other issues raised that may impact the electronics industry and EDA vendors.

Should royalties be fixed at a certain amount regardless of the sale price of the unit that use the licensed IP?  Or, as Qualcomm contends, should royalties be a percentage of the price charged to the customer?

I do not think that an IP more valuable when used to control the temperature in a passenger cabin of an airplane or in a home.

What is the intrinsic value of an IP?

The IP should have a value that is independent of the sale price of a system in which it is used.  The value of an IP, I think, is the result of three components: the cost of developing the IP, the profit margin desired by its implementer, and the market demand for it.  The IP has an intrinsic value that is independent of the value of the product in which it is used.

How many times can he owner of the IP charge for its use in the same system to the same customer?

Qualcomm charges a royalty for every chipset used in the system and another royalty for the use of the same IP as a functionality of the system.

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