By John Blyler and Ed Sperling
Next to computation, memory is the most important function in any electronic design. Both processor and memory devices must share the limited resources of power and performance. The relative weighting of these tightly coupled constraints varies depending upon the application.

At one extreme of the power-performance spectrum are applications that sacrifice performance to maintain the lowest possible power, e.g., a simple 8-bit microcontroller. For example, STMicroelectronics has recently introduced a 16-kbit EEPROM kit that can harvest enough energy from ambient radio-wave energy to run small, simple and battery-free electronic applications like RFIC tags. The growth of wireless power technology is an emerging field that includes other major players such as Intel and Texas Instruments. (see “Tesla’s Lost Lab Recalls Promise Of Wireless Power”)

Another example of an extremely low power-low performance memory application is in the emerging market of flexible, plastic electronics (see Figure 1). A team from the Korea Advanced Institute of Science and Technology (KAIST) recently reported such a device, i.e., a fully functional, flexible non-volatile resistive random access memory (RRAM).

Fig. 1: An image of flexible memory wrapped on a quartz rod. (Courtesy of KAIST)

The challenge with flexible, organic-based memory materials is that the devices have significant cell-to-cell interference due to limitations of the memory structures within the plastic material. One solution to this problem involves the integration of transistor switches into the memory elements. Unfortunately, transistors built on plastic substrates (organic/oxide transistors) have such poor performance that they were unusable. But the team at KAIST solved the cell-to-cell interference issue by, “integrating a memristor with a high-performance single-crystal silicon transistor on flexible substrates.” Similar breakthroughs have been reported at IMEC, (see, “Organic Processors Offer Microwatt Applications.”)

In addition to low power, memristor technology promised to provide significantly higher memory densities with a smaller footprint than today’s devices. A memristor is a two-terminal non-volatile memory technology that is seen by some as a potential replacement for flash and DRAM devices. Hewlett-Packard, the developer of memristor memory, recently announced a partnership with Hynix to fabricate memristor products by the end of 2013.

One anticipated growth market for memristor technology is in solid-state drives (SSDs), which are replacing traditional hard disk drives (HDDs) in mobile notebook applications. SSDs require less power and space than HDDs, which makes SSDs well suited for the rise of ultra-light and ultra-thin notebook computers. These ultra-“books” aim for at least 8 hours on a single battery charge. Among others, Intel recently heralded it entrance into the ultra-book market during the last Intel Developer Forum (see Figure 2). The company is shifting its focus away from traditional notebooks toward ultra-books to deal with competition from Apple’s MacBook Air and ARM processor-based tablet computers.

Figure 2: Intel’s Ultrabooks are planned to align with the release of low voltage Sandy Bridge, Ivy Bridge, and Haswell processor models.

One consequence of the rise of Ultrabook laptops is the further erosion of the DRAM growth market (see Figure 3). Mike Howard, principal analyst for DRAM and memory at HIS, noted that, “the single biggest reason for DRAM’s reduced growth outlook in notebooks during the next four years is the Ultrabook.” Howard believes that the emphasis on form factor with minimal size and weight in Ultrabook will lead to fewer DRAMs on average than traditional notebooks.

Figure 3: DRAM market faces many challenges. (Source: IHS iSuppli Research, November 2011)

Let’s look at the other extreme of the performance-power spectrum, i.e. high(er) power and high performance. Today, server-grade multicore processors are needed to support both ever-increasing network data bandwidths and increasing data-crunching analytics for context-aware applications. In sync with the need for more processors is the complementary need for more memory. For example, networking applications require the constant movement of massive amounts of data into and out of each processor in a multicore system.

Such high-performance processor applications may soon grind to a halt in what Linley Gwennap describes as, “the looming memory wall.” Others have echoed Gwennap’s concerns that the throughput needs of high performance multicore processors will not be met by today’s memory technology.

What can be done? Several solutions are possible, notes Gwennap:
> Increase L3 cache to help reduce traffic to external memory.
> Add more memory channels to tradition slow speed DRAM devices.
> Follow Intel’s lead on its Xeon processors by adding buffer-on-board (BoB) chips to convert traditional processor serial interfaces into standard parallel DRAM connections.
> Follow MoSys’s lead by implementing a standard high-speed serial interface directly to DRAM.
> Add Micron’s prototype Hybrid Memory Cube to re-engineer the memory subsystem.
(see, “Samsung, Micron Unveil 3D Stacked Memory And Logic.” )

Not everyone agrees with that approach, however. Sam Stewart, chief architect at eSilicon, says that off-chip memory could greatly improve performance over L3 cache and do it much more efficiently. “When you have L3 cache, you have 2 megabytes per CPU that’s shared,” said Stewart. “With a Hybrid Memory Cube you may have 17 die with 8 gigabytes versus a total of 12 megabytes. Plus it’s lower power because it’s closer and there’s high-bit bandwidth.”

Add to that custom memory, which is right sized to the specific function, specialty memories that can run at higher frequency, and the performance numbers go up even further. Put them in a stacked die package and they can go up still further. While stacked die exacerbates some issues, such as heat dissipation and electromigration, it eliminates another problem—the need for termination on signal paths. The close proximity of chips means there is insignificant reflection of electromagnetic waves as they travel through wires at the speed of light. That alone improves performance, said Stewart.

There are other technologies in the works, as well, including phase-change memory, STTRAM (spin-transfer torque RAM), and resistive RAM, according to Philip Wong, professor of electrical engineering at Stanford. He said the goal is to improve energy efficiency in all these types of memory while improving performance.

But with an estimated 50% of processing now tied up with memory and memory controllers, there is plenty of research underway to improve every aspect of memory. Not all of them will roll out in time for the next couple of designs, however, which means engineers will have to push existing boundaries a little bit further until they’re ready.

By John Blyler
It is easy to miss the connection between advances in transistor architectures and the relationship to the larger system. How do improvements in transistor development fit into the big picture?

This is not an esoteric question, since improved transistor designs are essential to meet ongoing system-level demands for lower power, higher performance, small size, and reduced cost. Higher level system constraints influence what transistor improvements will be pursued.

A major driver of today’s systems is the emergence of a tightly connected electronic ecosystem consisting of an infrastructure core (data centers), smart mobile devices and sensor networks. All three components share the common requirements for high-speed electronics, increased battery life, greater data storage, multi-functionality, reduced cost and ever shrinking form factor.

Each of these affect the trade-offs  with different set of needs. For example, the data centers in the infrastrure core require the highest performance with efficient power usage. Mobile device require high performance with even greater emphasis on power usage.  Sensors require lesser performance but ultra-low power, even relying on engergy scavenging techniques.

The foundation for all of these system applications is the transistor. The challenge is that this most basic of hardware building blocks must meet all these different needs at different levels. To date, this challenge has been met by feature size scaling, which is a result of Moore’s law. Continuous scaling of transistors has provided the necessary improvements in performance while reducing power consumption, cost and die size.

But in the future, mere device scaling techniques will not be enough. Scaling on the material side will also be required at the sub-10nm nodes, to continue to meet performance, power, area and cost requirements. Even today, chip designs are transitioning from planar to FinFET transistors. There will also be continuous work to enhance the transport of devices via high-mobility, non-Silicon channel materials. Finally, memory cores are evolving from 2D to 3D structures.

“Scaling must be done at many levels,” explained An Steegen, Imec logic director at the recent Imec Technology Forum (ITF) in Lueven, Beligium. Comprehensive scaling will be needed on the transistor, process and – equally important – system side, through the use of 3D interconnects, she noted. New interconnect schemes will enable scaling at a higher resolution at the die-level.

Moore's Law and Device Scaling. (courtesy of Imec)

Since the 1990’s, lithography enabled scaling has help maintain Moore’s law with a continuous push of transistor feature size scaling. Lithography improvement have permitted tighter poly pitches and increased gate density. But an inflection point occurs at 90nm, which lead to the need for material scaling.

According to Steegen, lithographic methods had to be complemented by material-level scaling beyond 90nm. Material scaling led to the introduction of High-K Metal Gate (HKMG) processes and fully depleted devices. At 22 and 14nm nodes, non-planar devices will be required to manufacture the thin channels with improved electrostatics will be needed to allow the transistors to operate at much lower supply voltage (lower power) while still providing adequate performance.

Transistor scaling and material innovation. (courtesy Imec)

What lies ahead for both feature and material scaling? Imec’s roadmap provides one perspective (see Figure 2). Beyond 14nm, band engineering will be required to enhance transport or the mobility of the transistor through the use of Group IV type materials. These materials will complement the enhanced electrostatics for the device through band engineering.

Much uncertainty lies beyond 14nm. Undoubtedly, new transports will be introduced to fully evolve the capabilities of transistors. Some of these new transports will include tunneling FETs. The tunnel field-effect transistors (TFETs) are seen as successors to today’s metal-oxide-semiconductor (MOS) FETs due to their extremely low voltage requirements.

Another possible innovation beyond 14nm might be extreme channel electrostatics, explained Steegen. Such extreme channel confinement goes one step beyond Fin-Fets into nanowires. Quantum characteristic are another possible improvement, where traditional charge-based technologies are replaced with electron spin devices.

While the transistor remains the elemental building block for all semiconductor electronics, traditional feature scaling techniques will not be enough to meet future needs. That is why transistor designs must be seen in the context of the whole circuit and even larger electronic system (data center, mobile devices and sensor networks). This is clearly the approached used at major research and development operation such as Imec.

By Pallab Chatterjee
At Semicon West, a number of the key speakers and TechXPOTs were talking about current products being assembled and shipped with 3D technology. 3D die stacking is no longer a technology of the future. In fact it has been here for many years and has been used in millions, if not billions, of consumer, commercial and high-reliability designs.

The two leading technologies that have embraced this technology are memories and MEMS. Memories have used stacked die (back to top stack) with wire bonds for decades and have shipped literally billions of parts to the marketplace. These parts have been both DRAM and non-volatile memory technologies. Memory technologies, due to their high I/O and bandwidth requirements, are still a key driver of the 3D technologies. Many designs are being implemented with TSVs, and utilizing a silicon interposer layer. The goal is to get multiple device types connected together, such as CPUs, MEMS, and RF, and not just multiple instances of the same chip.

MEMS subsystems are also a known technology for multi-die stacking. A typical three-layer stack would be a MEMS gyroscope, a MEMS accelerometer and a signal-processing chip to interpret the output of the two MEMS sensors and interface to a standard logic design. These designs are currently available from many companies in the United States and Europe and are able to meet consumer-level price points. The Nintendo 3DS, for example, uses a MEMS gyroscope from Invensense, which is a mixed MEMS and CMOS product. Similarly, a control IC appears in the Nintendo Wii motion-plus controller. All are considered cost-effective and reliable.

On the high-performance side, Xilinx is shipping array-based designs. These SoCs feature four bit-cell blocks of Virtex-7 cores distributed over a silicon interposer to provide the high speed interconnect. The technology uses TSVs, microbeads, microbumps. C4 balls, BGA solder balls, and multiple 28nm FPGA bit-slice chips. Xilinx’s new stacked silicon interconnect technology enables a single FPGA device to deliver more of the FPGA resources that customers need—logic, memory, serial transceivers and processing elements—while providing industry-leading capacity and bandwidth performance. The technology allows for multiple FPGA die to be combined and provides up to 100x improvement in inter-die bandwidth per watt over conventional approaches (See fig. 1)

IMEC of Belgium and Leti of France both presented new directions for integrating core processors and face-to-face stacked memory that act as cache RAM. These systems also will include RF die stacked face to face on the silicon logic. Extended research will lead to further integration of stacked interposer with passives and advanced RF components—inductors, capacitors and large resistors—with these die and finally lateral communication interfaces such as silicon lasers and other nano photonics.

These photonic interconnects have been the internal baseline for 1Gb/sec. and higher communication links for long distances for many decades. The localized heat and micro-machined optics (gratings, etc.) have been well addressed and now allow for integration with other circuits. The work at IMEC is focusing on integration of these lateral signal paths with vertical TSV-based connectivity. The testability and reliability advantages of using tested “known good” die is driving this method forward in systems.

The next big driver in multi-processor systems is the integrated APU, which has a CPU, GPU, and memory controller in a single die and connected directly to system memory with TSV technology. This structure, which is not using a silicon interposer, features tens of thousands of connection points to give very high-bandwidth and low-latency connectivity to both cache and local main memory in a single unit. These systems will be available in end products shortly and are the key technology that will realize the next generation of tablet and smart phone products.

By David Lammers
Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations.

“This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech. “Many companies are assessing the ETSOI path as a way to build on their history of planar devices. But other companies are considering non-planar devices, perhaps because they see a longer scaling path. The next year will be a period of intense evaluation and development.”

Thomas Hoffmann, the front end of the line program manager at Imec, said many of the fabless companies that belong to Imec’s Insite program—which allows the large fabless IC vendors to gain early understanding about technology trends—are now asking for information about finFETs. During the first year of the Insite program, the main topic of interest was high-k/metal gate technology.

“Today, there are a lot of questions about finFETs, and not so many about high-k, which they may have already tackled,” Hoffmann said. “Many of them expect one of the major foundries to adopt finFETs.”

At the Imec technology forum, TSMC senior vice president of technology S.Y. Chiang confirmed that finFETs were on the foundry’s roadmap. “We evaluated the device physics and decided that we cannot extend planar devices that far. So we will use finFETs at the 14nm node.”

Before then, Intel may lead the way into vertical transistors, using its tri-gate design as early as the 22nm node. With its history of pushing bulk silicon technology, Intel may adopt vertical devices on bulk silicon wafers rather than switching to the more-expensive SOI wafers. University of Florida Professor Scott Thompson, who earlier worked at Intel, is among those predicting an early switch by Intel to the vertical dimension at the 22 nm generation. Others believe Intel will figure out how to extend planar bulk technology at the 22nm node.

Though it is still evaluating finFETs, analysts including Gartner Inc.’s Dean Freeman expect the Fishkill Alliance to switch to ETSOI at the 22nm node, taking advantage of the ability to fully deplete carriers from the thin channel. IBM has worked closely with its primary SOI wafer supplier, Soitec (Bernin, France), to create a volume supply of extra-thin SOI wafers with a top silicon thickness of 12nm, plus or minus .5 nm. Maintaining uniformity of the top silicon layer is critical to controlling the threshold voltage in ETSOI technology.

Imec’s Hoffman said at the 22nm generation, about 75% of the process steps used to create planar transistors are also common to a finFET process flow. “When it comes down to the 22nm node, I wouldn’t be surprised if IBM goes to a fully depleted SOI technology. In the first order, companies have to figure out how to scale the gate length, but ultimately they will do it in order to scale the supply voltage.”

Yannick Le Tiec, a researcher at Leti (Grenoble, France) now working at the Fishkill Alliance, said the undoped channel in ETSOI technology removes the problem of dopants moving around during the high-temperature steps. Also, ETSOI improves control of the gate. “We can use the buried oxide layer of SOI and create a back bias at the ground plane. That is an option that bulk technologies don’t have,” Le Tiec said.

Fig. 1:Fully depleted SOI devices with a gate length of 40 nm and a thin (10 nm) buried oxide. (Source: STMicroelectronics, Leti, and Soitec presentation at 2010 Symposium on VLSI Technology)

With strain techniques and high-k/metal gates pushed close to their limits, leading-edge IC vendors have to do something new to keep power consumption under control, said Jan Rabaey, head of the Gigascale Systems Research Center at the University of California at Berkeley. The undoped channel in ETSOI “gets around the key problem for leading-edge devices, which is the random variability of the dopants.” Also, by putting a fourth terminal beneath the oxide, Rabaey said ETSOI transistors can improve the ability to fully turn off the transistors.

“Intel is very committed to finFETs, and TSMC also is talking about finFETs at the 15nm node. But ETSOI is a technology that may be more amenable to rapid deployment,” Rabaey said. FinFETs would require a “total redesign of any company’s hard IP,” he said. With vertical transistors, the design rules governing spacing, proximity, and density all will change. And vertical transistors require innovations in manufacturing as well, including lithography and CMP.

Fig. 2: At the 2010 Symposium on VLSI Technology, IBM Research and other members of the Fishkill Alliance presented a finFET SRAM cell measuring 0.094 μm2

At 22nm and beyond, the design community is likely to see the major foundries go in different directions. TSMC may support a bulk 22nm flow, while GlobalFoundries, Samsung, IBM, and other members of the Fishkill Alliance may commit to a planar ETSOI process. If TSMC follows through on its commitment to finFETs at the 15nm generation, the EDA, IP, and fabless semiconductor companies may confront another divide, with TSMC adopting vertical transistors while GlobalFoundries and others remain planar. At that point, Rabaey said foundries will need to get much more involved with design, and fabless companies will “have to know a lot more about the process.”

Gap-fill challenges
The shift to vertical transistors will require new manufacturing techniques, said Randhir Thakur, general manager of the Silicon Systems Group at Applied Materials. Applied unveiled a flowable CVD (FCVD) tool on Aug. 24 that is aimed at finFETs and vertical memory devices where conventional CVD dielectrics and spin-on dielectrics (SOD) both run out of gas. Electrical isolation of the vertical transistors requires filling the isolation trenches with dielectrics from the bottom up, rather than from the sides.

“FinFETs raise the complexity beyond what spin-on dielectrics can handle. Those chemistries also have a lot of carbon, which creates fixed charges,” Thakur said in announcing Applied’s “Producer Eterna” flowable CVD tool.

The Eterna system includes a proprietary precursor, a carbon-free chemistry that can fill 10nm openings with very high (30:1) aspect ratios. “If carbon is introduced, that causes the threshold voltage to shift and creates leakage,” said Bill McClintock, general manager of Applied’s dielectric systems and chemical mechanical planarization products. Also, finFET manufacturing requires relatively low processing temperatures. “Going forward, these new device architectures involve filling gaps which are not doable with the current systems on the market,” he said.

By David Lammers
Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanical stress had relaxed over time and the top die had delaminated.

3D researchers around the world are paying much closer attention to thermal and mechanical stress, particularly as ever-thinner die are stacked and connected. At last week’s 2010 Symposium on VLSI Technology in Honolulu, IMEC researchers described the mismatch in the coefficient of thermal expansion between copper through-silicon vias (TSVs) and the surrounding silicon. Using a 45nm digital analog converter test chip, the IMEC team measured transistor drive currents with TSVs located at various distances from the active circuits. Tensile stress near the TSVs was in the range of mega Pascals (MPa), declining to zero stress at a distance of about 10 microns from the TSV edge – a distressingly long distance for today’s leading-edge devices.

That kind of fundamental information (IMEC will deliver a more-complete paper at IEDM in December), Marchal said, is allowing EDA vendors and chip manufacturers to begin creating stress models. “Thermal and mechanical stresses induced by TSVs is a big worry for the community, but I believe there are different ways to mitigate them. A lot depends on what type of devices you use. Stress is not uniform for different types of devices; for example, long channel devices see more impact.”

At its Leuven facility, IMEC is fabricating a series of test chips, named after volcanos, which have sensors positioned at various places on the die to measure thermo-mechanical stress. “We position the smart sensors at the most critical places inside the stack, with the DRAM on top, to study the thermal and mechanical impacts. Then we provide the information to our supply chain partners, including the DRAM makers and packaging houses. Our partners, such as Qualcomm and STMicro, want to gain a head start. When they start RTL-level design they want to know what is feasible and what is not.”

Fig. 1: IMEC is working with several EDA partners to create a pathfinding flow for 3D prototype creation. (Source: IMEC)

While the EDA community is making progress, Marchal worries about is the relative absence of the packaging design community. Co-design of the die and package is particularly important as top die are thinned to 50 microns or less, positioned on top of a much thicker die.

“The die are becoming as thin as aluminum foil, and if you have the wrong glue, or different heat cycles, the die do not remain flat. That builds up stress across the die. The EDA and packaging communities need to be more active in how to analyze this,” Marchal said.

These challenges will be solved, particularly as increasingly large investments are being made in 3D TSV technology. At the DAC conference last week, Myung-Soo Jang, a design infrastructure manager at Samsung Electronics, described Samsung’s plan to use TSVs to link a mobile logic device with a 400 MHz DDR3 memory. “Because we are the world’s largest memory maker, which also has systems expertise from our cell phone business, we believe we have an advantage in this area,” Jang said.

Memory manufacturers such as Samsung and Toshiba, bring certain advantages, but fabless and foundry vendors are forming their own alliances, including EDA vendors and packaging houses. At DAC, L.C. Lu, director of the design methodology division at TSMC, called 3D TSV “the next killer application” and outlined a 3D design flow that TSMC is developing.

The mobile systems vendors need TSV interconnects to support the bandwidth needed for new data services, which include point-to-point video, a market set to accelerate over the next five years. High-definition video encoding requires about 12.8 GB/s of bandwidth between the processor and DRAM memory. The only way to do that in a mobile system is with TSV-connected logic-memory solution, using three or four tiers of die thinned to 30 to 40 microns. To achieve the same bandwidth, conventional DRAMs would require the power-hungry GDR5 DRAM standard, some 2,000 I/O pins, and a frequency that would kill any cell phone battery quickly.

Sitaram Arkalgud, director of Sematech’s 3D interconnect initiative in Albany, N.Y., said Sematech is focused now on a copper-copper bonding, vias-middle manufacturing flow that will come into use in several years. To tackle the stress challenge better standards are needed for how to measure and report thermal and mechanical stress levels. At next month’s Semicon West in San Francisco, Sematech and Germany’s Fraunhofer IZFP research center will hold a workshop on 3D stress management, including DFM-like approaches for managing stress, material properties, and measurement techniques.

Arkalgud said Sematech and SEMI are working on a data exchange format for TSV applications, and will hold a meeting on the subject at Semicon West and again at Semicon Europa in the fall.
“Especially as we go to thinner die the TCE and stress issues will be something we need to watch. To do that, we have to agree on how to measure it, so a data exchange specification needs to be there,” Arkalgud said.

By Ed Sperling

Synopsys is teaming up with Imec, the Belgian research lab, to help solve the problems of 3D IC stacking and through-silicon vias. This is important stuff for re-use of older technologies, not to mention cutting verification time and achieving timing closure and getting chips to market on time and improving yield and…well, you get the idea. Synopsys also added design-rules-driven technology to Galaxy Custom Designer that helps speed DRC repair tasks.

Mentor Graphics added Amba 4 verification IP to its Questa library. Given the growing popularity of ARM’s processor, this is a necessary step—especially with Mentor’s commitment to the Android phone.

Actel got its first public endorsement of its new SmartFusion chip. Micrium is porting its embedded software stack to the mixed-signal FPGA. Micrium’s software is targeted at the ARM Cortex-M processor line.

TSMC sales were up 0.1% from January to February, which isn’t much. But when you consider that’s 144% higher than last year it starts putting things in perspective. Still, it would be nice to have a breakdown by process nodes.

By Cheryl Ajluni

At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs).

The concept of 3D stacking or integration technology is not new. In fact, 3D stacking of dies has been successfully demonstrated and is currently being commercially employed in some embedded domains (e.g., stacking DRAM memory on CPU cores). A recent 3D IC report from Yole Développement suggests that by 2012, the number of 3D IC-processed wafers could surpass 10 million units, driven in part by handset, wireless and computing applications. Given the intense interest and work going into developing 3D integration technology, this prediction seems just about right—assuming, of course, that a few challenges can first be met.

Exploring the third dimension

Very simply put, 3D integration consists of stacking integrated circuits and connecting them vertically so that they behave as a single device. A 3D chip is therefore just a stack of multiple device layers with direct vertical interconnects tunneling through them. So what’s the big deal about 3D integration?

Today’s semiconductor chips face extreme pressure to achieve increased performance, while reducing their size and accommodating lots of new functionality. When these factors coalesce in traditional 2D chips, longer interconnects result. In SoCs, longer interconnects translate into reduced speed and increased power consumption.

A key benefit of 3D integration is that it can reduce the length of interconnects. Additionally, it provides higher transistor density, faster interconnects and heterogeneous technology integration, with potentially lower power, cost and faster time-to-market. As Matt Nowak, director of engineering in the VLSI technology group of Qualcomm’s CDMA technology division, pointed out in a DAC 2008 presentation, the 3D approach “achieves extremely high densities, allowing us to use heterogeneous technologies and reduce form factor. The key is that it enables the use of new differentiating technologies to build new architectures that cannot be built in existing technologies.”

Eyeing recent developments

Up to this point, most efforts in 3D integration have focused on developing different fabrication techniques for stacking multiple device layers and forming the vertical interconnects. Much of the work has been done through collaborations with academia, industry organizations and government-sponsored laboratories around the world. One of the key technologies to come out of this research is a next-generation interconnect technology known as Through-Silicon Via (TSV). The TSV is a vertical electrical connection that passes completely through a silicon wafer or die to produce multilevel chips with an optimum combination of cost, functionality, performance, and power consumption. By using TSV technology, 3D ICs can pack greater functionality into a smaller footprint and realize shorter critical electrical paths, resulting in faster operation.

Some of the other developments to come out of ongoing 3D integration research were recently recognized at the Electronic Components and Technology Conference. Sandia National Laboratories presented details of its W TSV process, which is said to provide a suitably low-resistance metal with a coefficient of thermal expansion close to Si, a via fill that is conformal, and can be readily integrated into IC fabrication. IMEC introduced a novel process for die-to-wafer bonding (using Cu-Cu bonds) of its 3D SIC technology and a scalable TSV technology for 3D wafer-level packaging. Its TSV technology is designed for 3D structures where interconnects are fabricated after standard CMOS processing.

SEMATECH also is focusing its 3D research on TSV technology, particularly for implementation. The industry organization is actively working to bring together partners from across industry—chipmakers, equipment and materials suppliers, assembly and packaging service companies—to make 3D TSV suitable for high-volume manufacturing (Figure 1).

Figure 1. In contrast to the 2D-SoC or 3D System-in-Package, 3D TSVs offer a cost-effective way to achieve high density and performance, while also being able to integrate non-CMOS products with CMOS. The SEMATECH 3D project is based on cost modeling to assure products will be both manufacturable and affordable.

Help: tool support needed!

While ongoing research and development is absolutely critical to the success of 3D integration, perhaps one of the greatest challenges it faces is tool support in terms of design techniques and methodologies. Without it, engineers have virtually no efficient way to exploit the technology’s benefits. Tool support is especially critical when it comes to 3D integration because vertical stacking tends to increase thermal resistances, further exacerbating temperature-induced problems that can negatively affect system reliability, performance and leakage power. The use of 3D also will significantly complicate the typical design flow.

The key, of course, lies in creating a standardized design environment and methodology for physical design of 3D chips that could support a range of different tools. Having the tools integrated in one place would make it easier for designers to explore and make architectural decisions and then, to hand those decisions off to next stages in the design process.

3D IC integration is still in its infancy and, as a result, tools developed today for one specific application (e.g., stacked memory) may not be suitable for heterogeneous integration tomorrow. Nevertheless, there are some tools available now, with more in development. Some of these tools include:

3D PathFinding

Javelin Design Automation. 3D PathFinding provides a detailed 3D flow for accurate performance/power/cost estimates that can be used for rapid design exploration and optimization of 3D stacked ICs. Developed in collaboration with IMEC and Qualcomm, the solution extends Javelin’s existing PathFinding methodology and j360 Silicon PathFinder physical design prototype platform to support virtual chip design (Figure 2).

Figure 2. Javelin’s 3D PathFinding solution allows the designer to assess the impact of various 3D interconnect strategies throughout the IC design and fabrication process, in a matter of just a few hours or days. Silicon process engineers can use it to fine-tune their technology to the system architecture specifications.

MAX-3D, R3Integrator, R3CAD, and R3Artist; R3Logic

These tools, developed through work conducted as part of research programs sponsored by the Defense Advanced Research Projects Agency (DARPA), enable 3D IC design and analysis (Figure 3). MAX-3D is a 3D mask layout tool whose technology file includes all properties of stacking process, wafer orientations, bond materials, via electrical/material properties, and also incorporates 2D foundry design kits. R3Integrator is used for die/interposer/package co-design with TSVs. R3CAD is a java-based, multi-platform tool for 3D design research and prototype study and R3Artist is an embedded 3D layout editor (Figure 3).

R3Logic is currently collaborating with STMicroelectronics and CEA-LETI to develop a full 3D design flow for 3D heterogeneous system and system-in-package design.

Figure 3. R3Artist features single and multiple wafer technologies, integrated material properties database and solid model extraction, including dielectric layers.

3DCACTI

3DCACTI estimates the optimum access times and power dissipation of a cache using 3D IC technology for a given number of active device layers and by partitioning device layers for various technology nodes. Based on the estimation, it searches for the optimized configuration that provides the best delay, power and area efficiency trade-off according to the cost function for a given number of different 3D partitions.

3D Magic and PR3D, Massachusetts Institute of Technology

3D Magic is a comprehensive layout methodology for 3D circuit-layout editing and extraction with MAGIC, an open source layout editor developed by UC Berkeley. PR3D is a placement and routing tool for standard cell design in 3D. Both tools were developed through MIT’s Interconnect Focus Center Research Program. MIT also developed SysRel (System-Level IC Reliability) for assessing the interconnect reliability of 3D ICs from a thermal-aware perspective at the circuit-layout level.

Conclusion

With the pressure on traditional 2D chips mounting, 3D integration has begun to establish itself as a viable means of breathing more life into Moore’s Law. It certainly touches on all the hot buttons in the industry today, namely low power, cost and time-to-market. The challenge will be in ensuring that these benefits are realized in a timely and efficient manner. 3D-specific design tools and methodologies are coming to meet this challenge head on. In the meantime, the tools available now and the groundwork for future tools and methodologies being laid by industry organizations, academia and commercial companies alike, will go along way in ensuring 3D integration plays a critical role in the future of the semiconductor industry.