By Ed Sperling
System-Level Design sat down to discuss the future of stacked die with Riko Radojcic, director of engineering at Qualcomm; Prasad Subramaniam, vice president of design technology at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that conversation.

SLD: Where are we with 2.5D and 3D?
Radojcic: I think 2.5D was a misnomer, because that implies they are sequential. It’s clear that what we call 2.5D and 3D are going to co-exist for a long time. Some things make sense with an interposer and some make sense to be 3D.
Reiter: I agree—2.5D is a parallel effort to 3D. Lots of things will not use 3D because it’s too expensive. In 2.5D we will see production this year. With 3D it will take until next year for the first ones. I would guess computing or networking would be the first.
Radojcic: I would think those guys will pursue 2.5D.
Subramaniam: Memory makers are already offering 3D solutions today. If you look at just the memory chip, to increase the size of the memory rather than the die they’re stacking it vertically. That kind of 3D is already in production. It’s the question of co-mingling logic and memory that will take time. The advantage of 2.5D is that it allows afterthought. It allows you to take an existing design and to create a new set of I/Os and put in a 3D type of application.
Radojcic: I see no value in doing that. You’re creating an expensive solution to something you can do more cheaply. If you add the 3D interposer you’re adding another wafer. That’s cost. We can solve that problem with a flip chip. It’s cheaper.
Subramaniam: I disagree. We’ve done the analysis. It allows us to take an existing design, like an ARM subsystem in 28nm, even though surrounding logic doesn’t have to be at that 28nm process node. It can be 40nm or 65nm. Rather than building a new chip at 28nm, I can take my existing design, use it as one component of my 3D IC, and build a second chip in a cheaper, older technology.
Radojcic: Yes, as long as you’ve architected your chip like that, such that you can partition it.
Subramaniam: You can’t take any design, no. There has to be some partitioning in the architecture and some forethought. It’s not 100% an afterthought, but there is still some afterthought there.
Radojcic: You have to architect for it. If you haven’t done that, taking an existing chip will just cost you more. If you have done that, of course there is an avenue to doing things better and more flexibly.
Subramaniam: There is enough flexibility in designs that allow you to partition it in some manner.
Radojcic: True, but before 3D came along most of us wouldn’t have partitioned. We wouldn’t have architected it that way. To be able to leverage that value proposition, you must have 3D in mind.
Gianfagna: That’s true. It’s a premeditated act. If you don’t think it through way up front it doesn’t work.
Subramaniam: Because the SoC has a well-defined architecture, it lends itself to this type of application.
Radojcic: But only if you plan for it ahead of time.

SLD: Is this true in all cases?
Reiter: That’s the view of a high-volume supplier. I see low-volume solutions where they use an existing die, put it face down on an interposer, and connect memory to it. So for low to medium volume, 2.5D works. You call it an afterthought. I call it a customized solution.
Radojcic: Why wouldn’t you do that in a traditional multichip package?
Subramaniam: Because you don’t get the interconnectivity. The advantage of a silicon interposer is that you get thousands of interconnects.
Radojcic: But you have to design it sufficiently so you can leverage the interconnects from die to die. If you had designed for a traditional design, though, you would say, ‘I can’t have thousands of interconnects so I’m going to make a serial interface with 100 pins.’ If you take that design for a 100-pin interconnect and stick in an interposer it’s an expensive way of doing things.
Subramaniam: You may be able to take some internal signals out, which you are not able to do with a traditional MCM (multi-chip module) approach.

SLD: Let’s do a reality check. How far along are we toward stacking?
Gianfagna: Last year we had a hot-wired 3D system that was 2D with a bunch of scripts and manual effort. The customer base had strange, contrived designs and they were trying to see what they could and couldn’t do, and the foundries didn’t know what they wanted to do. A year later we have native 3D planning capability, the customer base has specific designs for implementation this year and next, and the foundries have a laser-sharp focus on process learning, mostly around 2.5D initially. If that’s a metric, things are clearer this year than last year. From an EDA perspective, I still think the market is two years away. But we still think this is big.
Reiter: If you look at the Atom chip with the FPGA from Altera, that’s basically a 2.5D solution. The FPGA is for customizing things. The Atom chip was not designed for this application.
Radojcic: But why use an interposer? Why not use a substrate and a multichip package?
Reiter: You could do that.

SLD: What’s missing from the tools side to make all this work?
Reiter: The ability to demonstrate what this technology can do is the most important capability. If you look at big corporations, top management is still hesitant to invest in this technology. If we could demonstrate in a credible way what it can do, people will be more successful in getting money to start programs using this technology.
Gianfagna: The way that happens is the early adopters blaze the trail, everyone tries to follow and the market heats up. What’s needed are commercial drivers. The tools aren’t there, but they’re close enough.
Subramaniam: The tools are not the issue. The development needed to support 3D is incremental. It can be done with the existing infrastructure. It’s really the end application.
Radojcic: Other than path-finding, which is hard to do with traditional tools. And the analysis.
Gianfagna: The complexity is higher. We’ve discovered that, too. RTL prototyping for a single chip has a certain set of challenges. When you go to 3D the modeling requirements are much greater, the constraint generation is more complicated. And we need standards. We can generate all the constraints, but we don’t know where to put them and how to express them because there is no agreed upon way to do that.

SLD: Do the standards organizations know where to start with all of this?
Radojcic: Standards are on a good track. We’ve worked with Si2 and Sematech to propose initials blasts for standards so we can feed them into Si2 and the EDA community and accelerate the process. The bits and pieces are moving, and we are on track to have a set of design exchange format standards by early next year.
Reiter: And Wide I/O.
Radojcic: Yes. The standards are channeled and the engine is revving.
Reiter: We have a bunch of players in a 3D enablement center participating. There are 15 companies listed, including Intel, IBM, TSMC, GlobalFoundries, and so on.
Radojcic: The way this was set up was Sematech said we are going to start a 3D enablement center initiative driven by the SIA. All the members of Sematech were mapped into this. Then a number of companies like Qualcomm, LSI and ASE joined.

By John Blyler
Interconnect technologies are nothing new at Intel. During the recent Intel Developers Forum (IDF) 2011, several processor-centric interconnect technologies were on display in the company’s Labs Pavilion. Most noticeable of these were Many Core Application Research Community (MARC) and its derivative called the Many Integrated Cores (MIC) projects.

In terms of interconnect fabric, the MARC platform relies on an open standard “Message Parsing Interface” (MPI) to communicate between as many as 48 Pentium cores within a single die. The goal of this research is to develop the interconnect hardware and parallel software applications that would support the “millions of processor” program. In this activity, Intel has been working with the U.S. government on a project called Ubiquitous High-Performance Computing (UHPC).

Interconnect strategies change as vendors move from processor-centric to SoC third-party IP-based designs. While Intel laid out its SoC development strategy years ago, few details concerning the interconnect fabric have been made public. Bill Leszinske, the company’s general manager of technical planning and business development at the Atom processor SoC development group, recently revealed that the Intel interconnect fabric will serve as a “chassis” within which a variety Intel and third-party IP can be swapped in and out for different applications. The company calls this proprietary chassis the Intel On-Chip System Fabric (IOSF). It is analogous to the ARM community’s Advanced Microcontroller Bus Architecture (AMBA) interconnect platform. Other proprietary on-chip bus structures include MIPS SoC-it and IBM’s CoreConnect, to mention a few. These buses have bridging capabilities to ARM’s AMBA bus or the Open Core Protocol (OCP) standard for IP cores (OCP-IP) socket technology.

Leszinske is quoted as saying that the IOSF is a scalable fabric that supports multicore operation and maintains the PCI-bus order. This last item is critical because Intel’s Atom processor uses the PCI bus to connect to the outside world, for example, to provide embedded programmability via Altera’s FPGA core (see, “Intel Teams Up with Altera.”) The popular PCI bus is also an important interface between ARM processors of Xilinx FPGA fabric (see, “FPGAs Move to IP through Processor Interface”).

NoC vs. internal buses
The growing demand for low power and high performance chips is putting new demands on the on-chip IP interconnect architecture. Perhaps that is why many chip companies have migrated from internal interconnect technology to on-chip networks. This approach allows them to protect their legacy IP cores and any proprietary communication features while providing access to third party IP vendors. But how do overall SoC networks, such as a network-on-chip, relate to proprietary buses like Intel’s IOSF or ARM’s AMBA?

Drew Wingard, Sonics’ CTO, puts it this way: “Our principal competitor is internal technology, which is typically derived from either legacy computer buses or the various flavors of ARM’s AMBA specifications. Intel’s IOSF represents such an internal technology, and their press interviews about IOSF make it clear that supporting the ordering requirements of PCI is crucial to them for supporting their large, existing software base.”

Figure: Intel’s hierarchical approach to SoC integration, with separate interconnection fabrics (networks) for Intel IP and most third- party IP.

Processor-centric companies like ARM and Intel need interconnect architectures to grow an ecosystem of third party IP providers. But these providers have widely varying communication requirements that are difficult to manage.

Here is where NoCs can be of great value. As chief architect and co-founder of Arteris, Phillippe Boucard explains that before NoC technology was available IDMs would use hybrid-bus technology to connect IPs to a centralized crossbar, which would then route the traffic throughout the chip. In the past five years, NoC on-chip interconnect architectures began to replace proprietary hybrid bus technology.

“Our NoC IP uses Network Interface Units to convert the ARM protocol into a packetized protocol format. Instead of having a centralized crossbar, the NoC interconnects are distributed throughout the SoC. On top of that, the NoC provides several services, such as security, quality of service, software bring-up, power management, domain management, and so forth.”

There are multiple challenge facing today’s SoC designers. Chips must meet the often-conflicting requirements of low power, high performance, small die size, low cost, low heat generation and development in a very tight time-to-market period. The problem with traditional, proprietary hybrid-bus interconnects is that any change in the IP requires a physical change in the overall system topology, including the buses. With a NoC architecture, only the interconnect needs to be reconfigured.

Complex designs have spurred the growth of design re-use via semiconductor IP. To handle all of this IP, on-chip interconnects had to become more complex. Proprietary internal buses have been giving way to more open on-chip interconnect specifications. NoCs further reduce chip complexity by providing a easily reconfigured communication subsystem between the majority of IP cores on an SoC.

By Ed Sperling
Cadence won a deal with Taiwan-based Sunplus Technology, which has adopted Cadence’s TLM flow for its next-gen SoCs. Sunplus makes chips for TVs, set-top boxes and DVD players.

MIPS won a deal with Loongson Technology Corp.—a Beijing-based company formed through the Beijing Municipal Government, the Institute of Computing of the Chinese Academy of Sciences and the Loongson development team—to use its cores for everything from high-end computing, cloud servers to embedded applications in the industrial control, smart meter, automotive, GPS and mobile markets.

TSMC’s net sales were down slightly again in July—2.9% compared with June and 3.4% compared with July 2010. Of that amount, about 0.4% can be accounted for by Global Unichip, which is no longer included in TSMC’s numbers.

Processor sales appear to be booming. Intel declared a quarterly cash dividend of 21 cents per share. Given that Intel’s stock is trading at about $20 per share, that’s a hefty dividend.

By Ed Sperling
Mentor Graphics rolled out its Pyxis custom IC design platform, signaling that it has fully digested and integrated its acquisition last year of Pyxis, which made AMS routing tools. What’s particularly interesting is that Mentor says the new platform is tightly integrated with 2.5D interconnect parasitic extraction, taking yet another step alongside its role in test to position itself in the stacked die world.  Mentor also unveiled a new program for embedded software development that includes both professional services and a suite of tools for Linux, Android, open-source toochains and user interface product and design services.

Synopsys uncorked the next version of its LightTools for illumination analysis for the lighting industry. The focus will be on lighting and solar designs, which are both rapidly growing markets. Being able to apply advanced CAD tools to these sectors should produce some interesting results.

A standard for sharing memory between two chips, which was jointly developed by Arteris and Texas Instruments, has been licensed by 10 SoC vendors in the mobile and wireless markets. You might recognize some of these names: Intel, Samsung, LG, ST-Ericsson, HiSilicon and VIA Telecom.

Ansys’ proposed acquisition of Apache Design Solutions got a boost when the U.S. Justice Department and the Federal Trade Commission reduced the waiting period for the deal. The acquisition is expected to close next quarter.

TSMC issued its Q2 earnings report. Revenue was up 6.5% from Q1 and 16% year over year (in U.S. dollars). Net income was down 0.9% from last quarter. What’s most interesting in the earnings report, though, is the outlook. The company says the “global economic condition has weakened in the last few months,” adding volatility into the supply chain and impacting the demand for wafers next quarter. Consumer and computer sements are expected to decline while the industrial/standard segment will increase.

By Ed Sperling
MIPS has positioned itself head-to-head with ARM in the Android world, adding yet another competitor. The other one is Intel’s Atom, of course. MIPS stake on this one involves a smartphone that passed the Android Compatibility Test Suite.

Moortec Semiconductor taped out its embedded temperature sensor IP using TSMC’s 40LP and 28HP processes and Synopsys’ custom design solution. Who says analog isn’t migrating down the process curve? Moortec is based in Plymouth, U.K. 8

TSMC’s net sales, which are a good indication of how the semiconductor industry is faring, were down 0.7% from April to May—basically flat—but they are still up 6.3% from last May, which was well into the recovery period. Revenue was up 12.2% in the same period compared with 2010.

GlobalFoundries, meanwhile, swapped out its top leadership team. Ajit Manocha will replace Doug Grose as acting CEO. James Norling will become executive chairman and Ibrahaim Ajami the vice chairman, while COO Chia Song Hwee—former CEO of Chartered Semiconductor, which was acquired by GlobalFoundries—will leave the company in August.

By David Lammers
Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied.

Now that Intel has come out of the closet with its tri-gate technology, “the foundry customers are all going to ask, ‘When am I going to get a FinFET? What does it look like?’” said one source, who asked not to be identified.

What they may find is a transistor that is rather difficult to build, at least for the companies that lack the resources to make the jump from planar to vertical structures. “Intel’s competitors will all be taking that thing (the tri-gate device) apart. They will learn from it. They will catch up, but it is not automatic and takes time. Intel has shown its technology leadership, but of course they have to invest an enormous amount of money to stay ahead and the competitors have to spend a much smaller amount to copy,” the source said.

Opinions differ on how quickly finFETs will enter the SoC space. At the Intel tri-gate rollout, Intel architecture general manager Dadi Perlmutter said Intel’s goal is to achieve “parity,” rolling out MPUs and SoC products on the latest technology at the same time. The lag is declining node by node, he said.

Planar vs. FinFET

Analyst Nathan Brookwood, sees Intel introducing tri-gate-based, 22nm, Atom-based SoCs for smartphones and tablets in the fourth quarter of 2012. Those “Silvermont” SoCs would be supplanted in 2014 by the 14nm-based “Airmont” SoCs. If that scenario proves accurate, Intel will be on the market with Atom-based and MPU products at the same time in 2014.

If Intel meets its target, and if TSMC rolls its finFET technology in 2015 at the 14nm node, at least two companies would be on vertical transistors for SoCs. There is speculation that TSMC might pursue a planar transistor for low-cost applications at the 14nm generation, using finFETs for the high-performance graphics MPUs, FPGAs, and others. And some believe that Intel will be more active in the foundry space, partly as a way to monetize the estimated $2 billion it took to develop the 22nm tri-gate technology.

Dean Freeman, a manufacturing technology analyst at Gartner Inc., said Intel’s tri-gate technology is impressive. “However, the SOI group won’t give up any ground.” The SOI consortium is working closely with ARM to demonstrate lower power consumption, at 1 to 2 GHz performance, for smart phones. But Freeman said most of those smartphone chips are produced on bulk wafers today, and they will be reluctant to spend much on the additional wafer cost represented by UTB-SOI wafers. Even AMD has switched to bulk (non-SOI) technology for its low-cost Fusion products, he noted.

On the other hand, Freeman said the vertical devices require a big change in the design tools, and a complete redesign of a company’s proprietary intellectual property. “Not all devices need 3D. Tri-gate will be used for Intel’s X86 products, and IBM will go 3D for its high-performance devices. Some high-performance ASSPs might need 3D as well. I am not certain about the ARM devices,” he said.

Gary Patton, an IBM vice president who manages the Fishkill Alliance including Samsung, Toshiba, STMicro, and GlobalFoundries, said the alliance is developing several different transistors for the 14nm node. IBM will continue to develop an SOI technology with finFET transistors, adding its on-chip SOI-based embedded DRAM technology. Other members of the alliance need a bulk FinFET, and others, including STMicroelectronics, are pursuing a planar UTB-SOI approach (which IBM refers to as Extremely Thin (ET)-SOI) using back-gate biasing underneath the planar channel to boost performance or reduce power consumption.

“ET-SOI with a back-bias operation is pretty comparable with finFETs for certain applications. FinFETs are pretty complex, and ST Micro is pretty confident in ET-SOI,” Patton said during a brief interview at the Advanced Semiconductor Manufacturing Conference, held in Saratoga Springs, N.Y., this month. Patton said members of the Fishkill Alliance and IBM Albany will give three papers at the upcoming VLSI Symposium, planned for early June, on SOI finFETs, bulk finFETs and ET-SOI.

“FinFETs have some performance advantages, but Intel and others will have to show that they can control the tolerances, including at the source and drain regions. On the other hand, ET-SOI appears to have some resistance problems, so we’ll have to see how it plays out,” Patton said.

Freeman said the Fishkill Alliance has been a huge success, but warned that the shift to a tri-gate transistor “does give Intel a crack at the mobile device market, as the power consumption is very good.”

The Gartner analyst added, “What IBM needs to look out for is an Intel alliance forming. You already have Toshiba and Samsung working with Intel on some transistor technology, so there could be some cracks forming. There is the possibility of two camps, but Intel is so protective of its IP it will be interesting to see how this plays out.”

Chenming Hu, who led a UC Berkeley team that did much of the early work on both finFETs and UTB-SOI a dozen years ago, said he believes for finFETs and UTB-SOI technology will be deployed. Manufacturing finFETs, with the need for a very thin fin at close tolerances, is challenging for all but the largest companies such as Intel and TSMC.

“If the interface with the design team is close, and the resources are large enough, the lure of finFETs is that they can be scaled. But it does take investments. UTB-SOI does not take as much technology development investment,” Hu said.

UC Berkeley's Hu

“I remain steadfast in my belief that both FinFETs and UTB-SOI will be going to manufacturing,” Hu said. “I expect both to go into production. The very large companies, such as Intel and TSMC, will have the resources to go to FinFETs. Some other companies may go to UTB-SOI. ST Microelectronics is probably the closest to using UTB-SOI. FinFETs may be more versatile in performance and power. On the other hand, FinFETs take a lot more development resources, in terms of the manufacturing control, the layouts, and the libraries. In FinFETs, the gate widths are discrete, rather than continuous. And the thickness of the fin needs to be scaled, along with the gate length.”

Scott Thompson, a professor at the University of Florida, said the manufacturing challenges of finFETs may provide Intel with a five-year lead, or longer.

“Developing a complex technology like tri-gate requires significant investment in silicon resources and manpower—development teams of perhaps more than 1,000 people. The complexities for development mean that hundreds of thousands of wafers have to be run to solve the issues. The tri-gate development is at least an order of magnitude more complex than strained silicon at 90nm, or HKMG at 45nm. That is why it took Intel eight years to implement, and why I don’t think anyone else will have in market for more than five years,” said Thompson, who spent two decades in technology development at Intel’s technology and manufacturing group at Hillsboro, Ore.

Manufacturing perfect fins over billions or trillions transistors is quite a challenge, Thompson said, adding that “it can be done in a fab that runs a single process, with equipment and settings that are kept constant. The manufacturing flow has unique advantages for high-end processors but does have problems supporting several key features needed for SOCs: multiple threshold voltages, and thin and thick oxides in support of analog.”

By Ed Sperling
A power shift is under way across the SoC world that ultimately determine who wins the business, who gets the biggest share and what technologies are ultimately used to get there.

Complexity has reached a point where being able to pull the necessary pieces from a disaggregated supply chain is becoming much more difficult. That helps explain why all three of the major EDA companies now offer IP in addition to a slew of adjacent services. It also explains why Intel acquired Wind River and why Apple is now re-aggregating into a vertically integrated device manufacturer.

This complexity began rearing its head at 65nm, when issues such as power, silicon stress and third-party IP integration became rampant. At 28nm there are other physical effects to consider, and at 20nm and into stacked die there are a slew of other issues ranging from packaging, power budgeting, modeling, more complicated test and complex IP integration—to name a few.

Normally this would force re-aggregation of a supply chain, and there are some examples of this happening, but the economics of reaggregation are unusual in an industry where building a state-of-the-art fab now costs upward of $5 billion and where a large 100 million-gate design can pass the nine-digit mark for the first time.

“Most industries would vertically integrate at this point,” said John Bruggeman, chief marketing officer at Cadence. “But in this industry the economics of the different segments are so dramatic that vertical integration will not solve the economic issues. It would solve the technology issues.”

Within that framework, much tighter groups will emerge—cabals is probably a more accurate term—of large companies with deep pockets sharing common interests. They also will share much more of their technological know-how with each other, something that they currently refrain from doing in the design world for fear of theft of corporate secrets. Bruggeman said this is only beginning in the design sector at 28nm, but at 20nm or 14nm it will become necessary for survival.

“You will see power battles emerge, but they won’t be effective groupings until they realize no one will be the general contractor. There will be two main ecosystems—star IP and foundries—and EDA will connect them together. Companies like ARM cannot connect to TSMC without EDA.”

Foundry battles
Much of what will unfold will mirror what has happened on the manufacturing side, where foundries have set up their own ecosystems. The most complex one is the Common Platform and the Fishkill Alliance, which were started by IBM largely as a way of spreading out the very expensive process development across a number of companies that had deep enough pockets or technological expertise to contribute something.

The core members of the Common Platform—GlobalFoundries, Samsung and IBM—have been building up their expertise for next-generation chip manufacturing since the 90nm process node. TSMC has formed its own smaller ecosystem for similar reasons, striking up strong relationships with EDA companies.

It remains to be seen how those collaborative efforts will fare, however, against Intel’s vertically integrated model. Intel’s announcement that it will introduce FinFETs at 22nm—probably later this year—has set the whole manufacturing sector abuzz about whether the technology will be manufacturable, whether it will offer promised gains in power savings and performance, and whether their own developments will be competitive. Intel’s FinFET rollout is about two process nodes ahead of schedule.

Stacking effects
The other kind of 3D—stacked die, whether using an interposer or a TSV—is likely to create new issues about who owns what. Two good die may equal one bad stacked die, which is a problem when they are being put together. Heat, thinner substrates and noise can all have disastrous effects on signal integrity and performance.

“There is an issue of who owns the problem,” said Sunil Patel, principal member of the technical staff at GlobalFoundries. “We have not productized any of this yet, so it will all be played out over time.”

He noted that a much closer collaboration will be necessary. “This is not the old model of a GDS-II file where you expect a fully functioning package. It may not work. We all have to work together on what is now a back-end process. That’s a different relationship between customers and foundries. We have to understand the key deliverables for every die.”

Software vs. hardware
There has been much talk about who’s going to be in control of designs, hardware or software engineering teams. The answer is probably both.

Bridging hardware and software design sounds logical enough on paper, but more than a decade after this idea first began receiving attention it has achieved only modest success. So what’s holding up the process?

The real challenges stem from a rather complex combination of technology and business. While there is plenty of reason to align hardware and software development much more closely from a system-level standpoint—it can certainly improve performance and boost energy efficiency, for example—some key pieces have been missing.

“The software guys are used to getting a static hardware model,” said Mike Gianfagna, vice president of marketing at Atrenta. “There needs to be a balancing of software and hardware, but some of the pieces still need to be developed. We need modeling and simulation for both. We don’t believe a hardware-centric world will be successful. The software guys need to help drive architectural decisions. That is a new opportunity for both sides.”

He noted that software engineers currently have no way to communicate their concerns back to the hardware team. “What if you could take a generated model and send back the list of what they did and didn’t like and 24 to 48 hours get a new design? That would make a big difference.”

It also would help ease some of the stress about who should be in charge and how communication will work across disciplines that don’t necessarily speak the same language.

Make vs. buy
The other piece of the puzzle in a control shift is what actually gets used in a design. With IDMs such as Intel and Apple, there’s no question about who owns the design and who makes the pieces. For the rest of the industry that isn’t the case.

“We’re seeing a value inversion,” said Jack Harding, chairman and CEO of eSilicon. “The best companies can’t understand what other companies are doing unless it’s their job to know. For most companies, do-it-yourself is dead. No one can make one 28nm chip a year and be successful at it. You may come up with a solution, but it very likely will be sub-optimized.”

What’s interesting about this model—one shared by companies such as eSilicon, Open-Silicon and Global Unichip—is that the expertise is shifting from companies that design the chips to companies that actually put them together. The designers don’t work closely enough with the assembly to understand the intricacies of the technology, and the cost of developing the IP and subsystems is too high.

Stacking of die potentially removes that level of understanding by an entire die, which ultimately will be bought and sold as a complete, integrated subsystem. In that case, the real value may be less about the individual pieces of the technology and more about the tradeoffs between business and technology. Companies that get this right may be the biggest beneficiaries, while companies that develop the technology in a crowded market may find their market position severely eroded.

Conclusion
The changes that will be wrought over previous process nodes were mostly about technology—putting more on a chip, using technology to add unbelievable complexity and push the limits of physics. The next wave of changes will be as much about the intersection of business and technology as about advancing Moore’s Law.

As these changes unfold, there will be winners and losers, and there will be some companies squeezed out while others gain a toehold, a foothold, or win market dominance. But as these worlds converge—hardware, software, manufacturing, merchant IP and the business of all of these the semiconductor design market will be redefined for the next phase of growth. In some respects this is a normal business cycle, but change is always unsettling, unexpected and not of equal benefit to everyone.

By Ed Sperling
Synopsys expanded its Discovery verification platform with a regression and analysis extension called CustomExplorer Ultra. The focus is analog and mixed signal, which is a hot topic these days with the momentum over 2.5D stacked die with interposers. Case in point: Texas Instrument’s purchase of National Semiconductor.

TSMC filed its annual 2010 report with the U.S. Securities and Exchange Commission. The report shows that 2010 sales hit a record $14.5 billion, up 68% over 2009. Net income was $5.68 billion, an increase of 84% year over year. The foundry noted in the filing that capital expenditures this year will total about $7.8 billion, an amount that may fluctuate depending on market conditions. It plans to add capacity to its 300mm and 200mm wafer fabs, develop process technologies at 28, 20 and 14nm, and invest in solar and LED production facilities. Also of note is that fabless companies accounted for 79% of 2010 sales compared with 80% in 2009.

Intel showed remarkable resilience in its earnings, as well. GAAP revenue for 2010 was $12.8 billion, up 25% over 2009. Net income was $3.2 billion, up 29% over the previous year. For the first quarter, Intel’s data center group showed the strongest growth, up 32%. Atom sales were up 4% to $370 million.

Those numbers coincide with strong sales growth at IBM, which got a boost from increased mainframe sales, and at Apple, which was bolstered by both iPhone sales over the Verizon network and new Mac sales. The iPhone uptick helped Qualcomm, as well.

By Ed Sperling
What’s in a name? Apparently not enough. Cadence’s Tom Anderson looks at some alternative suggestions for DVCon.

Mentor’s Thomas Bollaert cites some really interesting verification stats, which were presented at DVCon by Mentor CEO Wally Rhines.

Synopsys’ David Hsu examines high performance computing in a cloud and what effect that could have on EDA. The impact on chipmakers’ operating expenses could be significant, but only if they’re actually willing to move data into the cloud.

Harry Gries, aka The ASIC Guy, talks about the blurred lines between winners and losers in sports and in EDA. In EDA there’s certainly good reason for being civil to the competition, though. You never know who’s going to be your next hire or your next boss.

John Cooley’s DeepChip features an anonymous but positive report of a speech by VC Jim Hogan on SoCs, IP, design management and verification. In Hogan’s opinion, the future is all about SoCs and IP.  DeepChip also ran the results of a Mentor survey on high-level synthesis from Shawn McCloud. What’s particularly interesting are the advantages for cycle-accurate implementations of control logic using HLS and the split between untimed, partially timed and cycle accurate on algorithm implementation.

Cadence’s Richard Goering drills down on the Open SystemC Initiative with a video interview of its chairman—Intel’s Eric Lish. Goering asks all the important questions.

Mentor’s Mike Jensen compares fast cars to simulation. That assumes, of course, your simulation actually runs fast.

Synopsys’ Navraj Nandra looks at a new standard, G.hn., which unifies the physical layer and data link layer over multiple wire types in the home. The next step is unifying wired and wireless, which should have interesting ramifications for all sorts of consumer and business electronics.

Speaking of converged communications, Semico’s Tony Massimini takes the covers off Thunderbolt, the new and much faster interconnect technology developed by Intel that made its debut in Apple’s new MacBook Pros. The big question is how fast it will be adopted—and by whom.

Cadence’s Joe Hupcey rolls out another video, this one for assertion-based verification involving a paper from Freescale and Cadence. Considering formal verification’s continued growth, this is an area that everyone will need to get comfortable with.

Mentor’s Dave Rich offers up some inside knowledge for using UVM 1.0 with Questa. If you work in this environment, this stuff should come in handy.

Also deep in the weeds of verification, check out the blog by Verilabs’ Asif Jafri in Synopsys’ VMM Central.

And on a broader note, Cadence’s Sharon Rosenberg looks at TLM 2.0, UVM 1.0 and what they mean to verification. At 28nm, quite a bit.

By Pallab Chatterjee
In the enterprise it’s all about speed and power—as in more speed and less power—and those changes are forcing shifts in the chip architectures as well as the processes used to develop those chips.

At the Linley Data Center Conference the next generation of network control chips were discussed. The keys for the new networks are 10G data lanes to be used with 10G/40G and 100G applications. For 100G the alternate configuration from 10 lanes of 10G was 4 lanes of 25Gb/s also being designed with 40nm.

The 40nm processes give the advantage of the data speed that was needed, plus power savings that are required to keep the reliability of the die and package. The trend is that these high-speed switches need to be available not as single PHYs, but as duals and quads. The 40nm node allows for target power at about 3W for these parts, which will enable 24- and 48-channel switch products.

The PHY that is being provided by most of the vendors can, with the 40nm process, support security data processing. The architecture for many of the high-throughput data systems includes local data analysis, decryption, policy and authentication testing off the early data bus just after the transceivers. These application processors can be on the same die or separate die from the PHY.

In applications where there are separate server processor chips, the trend is toward 32nm processes with multicore configurations. Intel is offering 6- and 10-core products under the Westmere architecture. For the upcoming Sandy Bridge architectures, they are featuring 8 and 12 cores using the 32nm process. On the server processor side, there also are 32nm products from AMD using the new “Bulldozer” architecture. Rounding out the server side there are also new cores from ARM with the Cortex A-15.

For dedicated application processors, a number of multicore processors are now available using 40nm processes. These include the 16-core Octeon from Cavium Networks, the 8-core QorIQ from Freescale, the 4-core ACP3448 from LSI, and the 8-core XLP family of processors from Netlogic Micro. Also in this space is the Netronome NFP-3240, which is a 40-core 40Gbps flow processor that is a co-processor to the Xeon main processor for network traffic handling.

One of the power/performance drivers is the security aspects of the networks. The Federal Information Processing Standards (FIPS) 140 is focused on cryptography and security systems, not on items such as firewalls, Web filters, spam and virus protection, or content and flow control. The cryptographic modules are constantly increasing in complexity of their algorithms and degree of touch of the data.