By Ed Sperling
A power shift is under way across the SoC world that ultimately determine who wins the business, who gets the biggest share and what technologies are ultimately used to get there.

Complexity has reached a point where being able to pull the necessary pieces from a disaggregated supply chain is becoming much more difficult. That helps explain why all three of the major EDA companies now offer IP in addition to a slew of adjacent services. It also explains why Intel acquired Wind River and why Apple is now re-aggregating into a vertically integrated device manufacturer.

This complexity began rearing its head at 65nm, when issues such as power, silicon stress and third-party IP integration became rampant. At 28nm there are other physical effects to consider, and at 20nm and into stacked die there are a slew of other issues ranging from packaging, power budgeting, modeling, more complicated test and complex IP integration—to name a few.

Normally this would force re-aggregation of a supply chain, and there are some examples of this happening, but the economics of reaggregation are unusual in an industry where building a state-of-the-art fab now costs upward of $5 billion and where a large 100 million-gate design can pass the nine-digit mark for the first time.

“Most industries would vertically integrate at this point,” said John Bruggeman, chief marketing officer at Cadence. “But in this industry the economics of the different segments are so dramatic that vertical integration will not solve the economic issues. It would solve the technology issues.”

Within that framework, much tighter groups will emerge—cabals is probably a more accurate term—of large companies with deep pockets sharing common interests. They also will share much more of their technological know-how with each other, something that they currently refrain from doing in the design world for fear of theft of corporate secrets. Bruggeman said this is only beginning in the design sector at 28nm, but at 20nm or 14nm it will become necessary for survival.

“You will see power battles emerge, but they won’t be effective groupings until they realize no one will be the general contractor. There will be two main ecosystems—star IP and foundries—and EDA will connect them together. Companies like ARM cannot connect to TSMC without EDA.”

Foundry battles
Much of what will unfold will mirror what has happened on the manufacturing side, where foundries have set up their own ecosystems. The most complex one is the Common Platform and the Fishkill Alliance, which were started by IBM largely as a way of spreading out the very expensive process development across a number of companies that had deep enough pockets or technological expertise to contribute something.

The core members of the Common Platform—GlobalFoundries, Samsung and IBM—have been building up their expertise for next-generation chip manufacturing since the 90nm process node. TSMC has formed its own smaller ecosystem for similar reasons, striking up strong relationships with EDA companies.

It remains to be seen how those collaborative efforts will fare, however, against Intel’s vertically integrated model. Intel’s announcement that it will introduce FinFETs at 22nm—probably later this year—has set the whole manufacturing sector abuzz about whether the technology will be manufacturable, whether it will offer promised gains in power savings and performance, and whether their own developments will be competitive. Intel’s FinFET rollout is about two process nodes ahead of schedule.

Stacking effects
The other kind of 3D—stacked die, whether using an interposer or a TSV—is likely to create new issues about who owns what. Two good die may equal one bad stacked die, which is a problem when they are being put together. Heat, thinner substrates and noise can all have disastrous effects on signal integrity and performance.

“There is an issue of who owns the problem,” said Sunil Patel, principal member of the technical staff at GlobalFoundries. “We have not productized any of this yet, so it will all be played out over time.”

He noted that a much closer collaboration will be necessary. “This is not the old model of a GDS-II file where you expect a fully functioning package. It may not work. We all have to work together on what is now a back-end process. That’s a different relationship between customers and foundries. We have to understand the key deliverables for every die.”

Software vs. hardware
There has been much talk about who’s going to be in control of designs, hardware or software engineering teams. The answer is probably both.

Bridging hardware and software design sounds logical enough on paper, but more than a decade after this idea first began receiving attention it has achieved only modest success. So what’s holding up the process?

The real challenges stem from a rather complex combination of technology and business. While there is plenty of reason to align hardware and software development much more closely from a system-level standpoint—it can certainly improve performance and boost energy efficiency, for example—some key pieces have been missing.

“The software guys are used to getting a static hardware model,” said Mike Gianfagna, vice president of marketing at Atrenta. “There needs to be a balancing of software and hardware, but some of the pieces still need to be developed. We need modeling and simulation for both. We don’t believe a hardware-centric world will be successful. The software guys need to help drive architectural decisions. That is a new opportunity for both sides.”

He noted that software engineers currently have no way to communicate their concerns back to the hardware team. “What if you could take a generated model and send back the list of what they did and didn’t like and 24 to 48 hours get a new design? That would make a big difference.”

It also would help ease some of the stress about who should be in charge and how communication will work across disciplines that don’t necessarily speak the same language.

Make vs. buy
The other piece of the puzzle in a control shift is what actually gets used in a design. With IDMs such as Intel and Apple, there’s no question about who owns the design and who makes the pieces. For the rest of the industry that isn’t the case.

“We’re seeing a value inversion,” said Jack Harding, chairman and CEO of eSilicon. “The best companies can’t understand what other companies are doing unless it’s their job to know. For most companies, do-it-yourself is dead. No one can make one 28nm chip a year and be successful at it. You may come up with a solution, but it very likely will be sub-optimized.”

What’s interesting about this model—one shared by companies such as eSilicon, Open-Silicon and Global Unichip—is that the expertise is shifting from companies that design the chips to companies that actually put them together. The designers don’t work closely enough with the assembly to understand the intricacies of the technology, and the cost of developing the IP and subsystems is too high.

Stacking of die potentially removes that level of understanding by an entire die, which ultimately will be bought and sold as a complete, integrated subsystem. In that case, the real value may be less about the individual pieces of the technology and more about the tradeoffs between business and technology. Companies that get this right may be the biggest beneficiaries, while companies that develop the technology in a crowded market may find their market position severely eroded.

Conclusion
The changes that will be wrought over previous process nodes were mostly about technology—putting more on a chip, using technology to add unbelievable complexity and push the limits of physics. The next wave of changes will be as much about the intersection of business and technology as about advancing Moore’s Law.

As these changes unfold, there will be winners and losers, and there will be some companies squeezed out while others gain a toehold, a foothold, or win market dominance. But as these worlds converge—hardware, software, manufacturing, merchant IP and the business of all of these the semiconductor design market will be redefined for the next phase of growth. In some respects this is a normal business cycle, but change is always unsettling, unexpected and not of equal benefit to everyone.

By Ed Sperling
Synopsys expanded its Discovery verification platform with a regression and analysis extension called CustomExplorer Ultra. The focus is analog and mixed signal, which is a hot topic these days with the momentum over 2.5D stacked die with interposers. Case in point: Texas Instrument’s purchase of National Semiconductor.

TSMC filed its annual 2010 report with the U.S. Securities and Exchange Commission. The report shows that 2010 sales hit a record $14.5 billion, up 68% over 2009. Net income was $5.68 billion, an increase of 84% year over year. The foundry noted in the filing that capital expenditures this year will total about $7.8 billion, an amount that may fluctuate depending on market conditions. It plans to add capacity to its 300mm and 200mm wafer fabs, develop process technologies at 28, 20 and 14nm, and invest in solar and LED production facilities. Also of note is that fabless companies accounted for 79% of 2010 sales compared with 80% in 2009.

Intel showed remarkable resilience in its earnings, as well. GAAP revenue for 2010 was $12.8 billion, up 25% over 2009. Net income was $3.2 billion, up 29% over the previous year. For the first quarter, Intel’s data center group showed the strongest growth, up 32%. Atom sales were up 4% to $370 million.

Those numbers coincide with strong sales growth at IBM, which got a boost from increased mainframe sales, and at Apple, which was bolstered by both iPhone sales over the Verizon network and new Mac sales. The iPhone uptick helped Qualcomm, as well.

By Ed Sperling
What’s in a name? Apparently not enough. Cadence’s Tom Anderson looks at some alternative suggestions for DVCon.

Mentor’s Thomas Bollaert cites some really interesting verification stats, which were presented at DVCon by Mentor CEO Wally Rhines.

Synopsys’ David Hsu examines high performance computing in a cloud and what effect that could have on EDA. The impact on chipmakers’ operating expenses could be significant, but only if they’re actually willing to move data into the cloud.

Harry Gries, aka The ASIC Guy, talks about the blurred lines between winners and losers in sports and in EDA. In EDA there’s certainly good reason for being civil to the competition, though. You never know who’s going to be your next hire or your next boss.

John Cooley’s DeepChip features an anonymous but positive report of a speech by VC Jim Hogan on SoCs, IP, design management and verification. In Hogan’s opinion, the future is all about SoCs and IP.  DeepChip also ran the results of a Mentor survey on high-level synthesis from Shawn McCloud. What’s particularly interesting are the advantages for cycle-accurate implementations of control logic using HLS and the split between untimed, partially timed and cycle accurate on algorithm implementation.

Cadence’s Richard Goering drills down on the Open SystemC Initiative with a video interview of its chairman—Intel’s Eric Lish. Goering asks all the important questions.

Mentor’s Mike Jensen compares fast cars to simulation. That assumes, of course, your simulation actually runs fast.

Synopsys’ Navraj Nandra looks at a new standard, G.hn., which unifies the physical layer and data link layer over multiple wire types in the home. The next step is unifying wired and wireless, which should have interesting ramifications for all sorts of consumer and business electronics.

Speaking of converged communications, Semico’s Tony Massimini takes the covers off Thunderbolt, the new and much faster interconnect technology developed by Intel that made its debut in Apple’s new MacBook Pros. The big question is how fast it will be adopted—and by whom.

Cadence’s Joe Hupcey rolls out another video, this one for assertion-based verification involving a paper from Freescale and Cadence. Considering formal verification’s continued growth, this is an area that everyone will need to get comfortable with.

Mentor’s Dave Rich offers up some inside knowledge for using UVM 1.0 with Questa. If you work in this environment, this stuff should come in handy.

Also deep in the weeds of verification, check out the blog by Verilabs’ Asif Jafri in Synopsys’ VMM Central.

And on a broader note, Cadence’s Sharon Rosenberg looks at TLM 2.0, UVM 1.0 and what they mean to verification. At 28nm, quite a bit.

By Pallab Chatterjee
In the enterprise it’s all about speed and power—as in more speed and less power—and those changes are forcing shifts in the chip architectures as well as the processes used to develop those chips.

At the Linley Data Center Conference the next generation of network control chips were discussed. The keys for the new networks are 10G data lanes to be used with 10G/40G and 100G applications. For 100G the alternate configuration from 10 lanes of 10G was 4 lanes of 25Gb/s also being designed with 40nm.

The 40nm processes give the advantage of the data speed that was needed, plus power savings that are required to keep the reliability of the die and package. The trend is that these high-speed switches need to be available not as single PHYs, but as duals and quads. The 40nm node allows for target power at about 3W for these parts, which will enable 24- and 48-channel switch products.

The PHY that is being provided by most of the vendors can, with the 40nm process, support security data processing. The architecture for many of the high-throughput data systems includes local data analysis, decryption, policy and authentication testing off the early data bus just after the transceivers. These application processors can be on the same die or separate die from the PHY.

In applications where there are separate server processor chips, the trend is toward 32nm processes with multicore configurations. Intel is offering 6- and 10-core products under the Westmere architecture. For the upcoming Sandy Bridge architectures, they are featuring 8 and 12 cores using the 32nm process. On the server processor side, there also are 32nm products from AMD using the new “Bulldozer” architecture. Rounding out the server side there are also new cores from ARM with the Cortex A-15.

For dedicated application processors, a number of multicore processors are now available using 40nm processes. These include the 16-core Octeon from Cavium Networks, the 8-core QorIQ from Freescale, the 4-core ACP3448 from LSI, and the 8-core XLP family of processors from Netlogic Micro. Also in this space is the Netronome NFP-3240, which is a 40-core 40Gbps flow processor that is a co-processor to the Xeon main processor for network traffic handling.

One of the power/performance drivers is the security aspects of the networks. The Federal Information Processing Standards (FIPS) 140 is focused on cryptography and security systems, not on items such as firewalls, Web filters, spam and virus protection, or content and flow control. The cryptographic modules are constantly increasing in complexity of their algorithms and degree of touch of the data.

By Pallab Chatterjee
The 2011 CES show was highlighted by the large number of tablet computers and mobile devices that support Internet access. The form factor for these devices is based on use models, but the computing capabilities are based on the power and operational life between charges. The platforms are drawing diving lines between x86 cores vs ARM cores, and CPUs vs GPUs.

While on the high level the tradeoffs were on screen size, battery life, UI and apps available, the hardware battle for the BOM was with a much smaller set of players. These new tablets were derived from either smart phones or laptops. The ARM CPU selection is the dominant platform for the oversized smart-phone derived products. The x86 CPU selection is the dominant platform for the reduced function laptop computer products.

The ARM devices are available in multiple forms. These include straight single and multicore CPUs, embedded CPUs in graphics chips, and full mobile chipset with memory controllers and display control. These can be found in parts from Nvidia, the Tegra products, and parts from Marvell and Qualcomm such as the Snapdragon products. In a lot of the cases, these ARM cores are combined in systems with MIPS cores and graphics acceleration from Imagination Technologies.

The ARM platform is highly power optimized for battery operation and for the RF interface. The key driver for the platform in the tablet space is the development environment. The platform software, available from both ARM and third parties, covers bus architecture for multicore design, operating system functions and high-level applications. To complete the tablet design, there are many suppliers making compatible IP for USB, HDMI, microphones, headsets, eSATA, and other components that have firmware interoperability with ARM. The majority of the ARM-based designs shown used the Android operating system rather than cell phone OSes.

The x86 platforms are primarily coming from the business applications and higher data throughput side. The main chipset uses Intel Atom cores, and some of the “lighter” duty reduced function tablets featured VIA x86 cores. These platforms were running Windows derivatives and Linux. The highly promoted Moblin environment was not really present in the new product mix. These x86 products have separate CPUs and GPUs. They feature either Intel graphics or Nvidia graphics co-processors. These tablet chipsets are lower-power versions of the one in the netbook/ultra-light laptop market and several also included the Imagination Technology POWERVR graphics and shader engine.

As the tablet form factor does not allow for a fan and has thickness that is driven by the height of the peripherals connectors, balancing power for the applications is the major challenge. Some of the new tablets released played with the options of single core CPU, multicore CPU, single GPU, multi-GPU, and a hardware codec. As one of the high-power and high-use applications is for playback of video and displaying high-resolution graphics, efficient utilization of the H.264 codec is a key.

Based on the compression involved with the data and the length of the video streams being viewed, there are power tradeoffs doing the video decoding in a CPU or a GPU with software vs. a hardware codec. There are similar issues for the camera interface if it supports stills, video, and single/dual/triple (S3D on one side, single on other) data streams going to a single codec. The format for the tablets affects not only the configuration of the cores but also their duty cycle. If a single part gets an extended operation, this changes the thermal gradient on the die and the board—hence the software has to balance the activities to help balance the heat.

By Ed Sperling
Synopsys added Android OS support for its ARC cores, shifting its efforts into the mainstream where companies such as ARM and MIPS now play. Synopsys’ pitch is that it can provide a full array of design and debug tools, thereby cutting time to market. This is an interesting new development in the Android market.

Mentor Graphics and Dongbu HiTek released design kits for analog BCDMOS processes. BCDMOS includes bipolar, CMOS and laterally diffused metal oxide semiconductor technology (LDMOS). The advantage of BCDMOS is low resistance and double metal layers for high current.

Cadence rolled out the next version of its Incisive verification platform, fully supporting the Universal Verification Methodology 1.0 and allowing coverage data to be merged with formal analysis and simulation. Also new is support for enhanced low-power corruption and isolation simulation.

GlobalFoundries uncorked its 28nm silicon-validated signoff-ready digital design flows for mobile and consumer electronic devices. It uses a 28nm super low power process, which uses an average of 1.0 volts, as well as gate-first high-k metal gate technology.

The other big foundry, TSMC, saw sales drop 5.5% from November to December of last year, although total sales for the year were still up 42.4% from 2009.

Don’t panic yet, though. Intel reported a record year and a record fourth quarter. Revenue for 2010 was up 24% over 2009, and gross margins were 66% vs. 56% in 2009. Net income grew 167% for the year, and 15% sequentially from Q3 to Q4.

By Ed Sperling
Mentor Graphics is integrating 6WINDGate software with its embedded Linux platform, which chops a big step out of the development process. It allows developers using Freescale and NetLogic multicore processors to optimize packet-processing performance without re-verifying applications. In the race for re-use, this is a big step forward.

Synopsys expanded its DesignWare Sonic Focus IP, which it picked up with its acquisition of Virage Logic. The IP greatly improves sound quality in low-power DSP-based devices.

MIPS took advantage of the Consumer Electronics Show to roll out a bunch of new products and announcements. From a consumer standpoint, the first MIPS-based smartphones and tablets hit the market based upon SoCs from Actions Semiconductor and Ingenic Semiconductor. MIPS also won a deal to provide its 1004K and 74K cores to MStar Semiconductor for use in DTV. MStar, based in Taiwan, is the No. 1 supplier of ICs for TVs and monitors.

And MIPS introduced its SmartCE—the CE stands for connected entertainment—platform, which integrates Android, Adobe Flash for TV, Skype, Home Jinni ConnecTV and social media on everything from digital TVs to set-top boxes and Blu-ray players. The macro story about Google buddying up with Adobe–Flash still isn’t available in the iPhone, although work is underway—is interesting.

Microsoft announced support for SoC architectures from Intel, AMD and ARM for its next version of Windows. But unless Microsoft can slim down its OS this effort will face the same kinds of power/performance/efficiency issues that have plagued Intel trying to run an x86 OS. What’s particularly interesting here is the emphasis on SoCs, not just processors. Most of the press coverage has been about the dissolution of the Wintel duopoly, but the bigger story is about the growing importance of SoCs. Intel has been talking about this approach for several years, but so far no one outside of Intel has seen much progress. ARM’s whole pitch has been SoC ecosystems, while AMD has fit somewhere in the middle with third-party IP built into its processors.

By Ed Sperling
Synopsys expanded its DesignWare MIPI IP portfolio with support for a handful of new PHY protocols. The trend is an interesting one—big IP companies adding lots of support and configurability, making it far harder for small IP companies to keep pace.

In a similar vein, MIPS joined the MIPI alliance to support standard interfaces for mobile handsets.

SMIC adopted Cadence’s DFM and low-power silicon realization technology for its 65nm reference flow. The silicon realization technology includes a slew of different tools. Across the East China Sea, Fujitsu is supporting Cadence’s C-to-Silicon compiler for high-level synthesis.

Mobileye, which makes camera-based driver assistance systems, is using Arteris’ network on chip IP for its next-gen EyeQ SoCs. This stuff is really cool.

TSMC said its net sales for November dropped 4.4% from October, but before you hit the panic button that’s still up 21.7% from November 2009. One month does not make a trend even though it can cause sleep deprivation.

On the big picture side—literally—AMD, Dell, Intel, Lenovo, Samsung, and LG all said they would phase out analog display technology and move entirely to scalable and lower-power digital interfaces. That spells the end for VGA and LVDS panel interfaces. It might be time to trade in that old monitor.

By Ed Sperling
Mentor Graphics bought all up most of the assets of CodeSourcery, the open-source GNU-based toolchains and services provider, moving the company squarely into the Linux world. This builds on the company’s acquisition last year of Embedded Alley, which makes runtime Linux. This moves Mentor well into the open source world, but even beyond that it positions the company particularly well for 3D stacking, where the company can flex its expertise in Linux, Android and RTOSes. Mentor did not disclose the purchase price.

Mentor also won a deal to build a verification environment for Infineon based on Mentor’s Questa platform.

Synopsys revenue for its fiscal Q4 was $375.5 million, up 1.5% from the same period in 2009. Net income was $25.4 million for the quarter, vs. $19.5 million in 2009. Put in perspective of the EDA industry this is very positive–particularly on the profit side–and the outlook for 2011 is even better.

The University of Cambridge in England has figured out what it claims is an economical way to replace copper interconnects with carbon nanotubes, which should allow for shrinkage of features well beyond 22nm. Companies such as Intel and IBM have suggested that nanostructures will be present in advanced designs beyond 22nm, although possibly not until 8nm. What makes this discovery interesting is the possibility of mass growing nanotubes at very low cost.

Simon Segars, ARM’s executive vice president and general manager of the company’s physical IP group, talks about the war with Intel and which markets it’s likely to affect.