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Blog Review – Monday, June 26, 2017

Monday, June 26th, 2017

This week, hot on the heels of DAC, a review of the Austin event; Intel administers a dose of precision medicine; Challenges for drivers; How to choose between a GPU or FPGA and a blockchain reaction for the IoT

DAC 2017 took place in Austin, Texas, and Paul MeLellan, Cadence Design Systems, was there and has collated a wide-ranging report, with day-by-day news, including bats and bagpipes from the 54 th incarnation of the event.

Writing from a very personal viewpoint, Bryce Olson, Intel, advocates precision medicine, and looks at Intel’s scalable reference architecture to speed up the research and answers in medical care.

Vehicle safety is critical, and Stephen Pateras, Mentor Graphics, looks at self-test and monitoring in autonomous cars, using the Tessent MissionMode architecture. He explains in a clear, detailed manner, the IC test capabilities and simulation for self-driving cars.

Still with vehicle design, Robert Vamosi, Synopsys, flags up the security hazards around the connected car as sensors proliferate and hackers ramp up their assaults. He advocates software security and the communication protection afforded by the IEEE 802.11p protocol.

A handy white paper is brought to our attention by Steve Leibson, Xilinx, for those deciding whether a GPU is better than an FPGA in cloud computing, machine leaning, video and image processing applications.

I learned a couple of things from Christine Young, Maxim Integrated this week. One is that there is a job title of ‘chief IoTologist’, the other was to put the term ‘blockchain’ into context for the IoT. She reports from the IoT World Conference about how blockchain, using advanced cryptography, provides a “tamper-proof distributed record of transactions” and how the IoT Alliance is occupied in developing a shared blockchain protocol as a common identifier to secure IoT products.

Starstruck John Blyler, looks at the reality behind the stardust and conducts an interview with Dr Clifford Johnson, physicist at University of Southern California and script adviser for the National Geographic Channel’s TV program, Genius, about Albert Einstein.

Blog Review – Monday, June 12, 2017

Monday, June 12th, 2017

This week, we find traffic systems for drones and answers to the questions ‘What’s the difference between safe and secure?’ and ‘Can you hear voice control calling?’

An interesting foray into semantics is conducted by Andrew Hopkins, ARM, as he looks at what makes a system secure and what makes a system safe and can the two adjectives be interchanged in terms of SoC design? (With a little plug for ARM at DAC later this month.)

It had to happen, a traffic system designed to restore order to the skies as commercial drones increase in number. Ken Kaplan, Intel, looks at what NASA scientists and technology leaders have come up with to make sense of the skies.

Voice control is ready to bring voice automation to the smart home, says Kjetil Holstad, Nordic Semiconductor. He highlights a fine line of voice-activation’s predecessors and looks to the future with context-awareness.

More word play, this time from Tom De Schutter, Synopsys, who discusses verification and validation and their role in prototyping.

Tackling two big announcements from Mentor Graphics, Mike Santarini, looks at the establishment of the outsourced assembly and test (OSAT) Alliance program, and the company’s Xpedition high-density advanced packaging (HDAP) flow. He educates without patronizing on why the latter in particular is good news for fabless companies and where it fits in the company’s suite of tools. He also manages to flag up technical sessions on the topic at next month’s DAC.

Reporting from IoT DevCon, Christine Young, Maxim Integrated, highlights the theme of security in a connected world. She reviews the presentation “Shifting the IoT Mindset from Security to Trust,” by Bill Diotte, CEO of Mocana, and In “Zero-Touch Device Onboarding for IoT,” by Jennifer Gilburg, director of strategy, Internet of Things Identity at Intel. She explores a lot of the pitfalls and perils with problem-solving.

Anticipating a revolution in transportation, Alyssa, Dassault Systemes, previews this week’s Movin’On in Montreal, Canada, with an interview with colleague and keynote speaker, Guillaume Gerondeau, Senior Director Transportation and Mobility Asia. He looks at how smart mobility will impact cities and how 3D virtual tools can make the changes accessible and acceptable.

Caroline Hayes, Senior Editor

Blog Review Monday, May 8, 2017

Monday, May 8th, 2017

This week, there is some N7 news, and the beginning of an HPC renaissance; ARM survives a mountain-top ordeal and Intel has a strategy for IoT; Odd place for sunburn

https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2017/05/05/tsmc-n7

TSMC’s 7nm process is detailed by Paul McLellan, Cadence, from a visit to CDNLive Silicon Valley. His report is well illustrated and informative.

Predicting a second renaissance in high-performance computing (HPC), Prasad Alavilli, ANSYS, explains the role of CFD and the state-of-play for HPC and what that means for chip design.

Likening Internet security to the American ‘wild west’, Alan Grau, Icon Labs, fears for security measures and corrective actions. He looks at some recent attacks and cures and advocates a strong stance on security.

I suspect Scott Salzwedel, Mentor Graphics, is rather excited about the New Horizons spacecraft, which is due to emerge from its hibernation. His enthusiasm is infectious, and his well-illustrated blog puts the reader as in thrall to the project – and the role of the company’s own Nucleus RTOS – as he clearly is.

The three phases of the IoT revolution are set out by Aaron Tersteeg, Intel. He sets out a clear plan to nuture big ideas and how technology can support the evolution.

PVT (process, voltage and temperature) sensor systems are exciting Rupert Baines, UltraSoC. He considers the company’s co-operation with Moortec Semiconductor, and what this means for SoC monitoring.

Life is not looking too rosy for ARM engineer Matt Du Puy and fellow climbers, at the moment. They are stuck on Mt Kanchenjunga in Nepal, without the drone copter that was confiscated by customs officials. True the team has a toolbox of ARM-powered devices, like the Suunto Ambit smartwatch, satellite beacon, Outernet networking device, Google Pixel smartphone, Go Pro and Ricoh Theta 360-degree camera, reports Brian Fuller, ARM, but there is also sunburn – inside the nostrils (eughhh!).

Caroline Hayes, Senior Editor

Blog Review – Monday, April 10, 2017

Monday, April 10th, 2017

This week, there are traps and lures in the IoT, as discussed by ARM and Maxim Integrated; Xilinx believes a video tutorial is a good use of time; Get cosy with SNUG for some insight; and ON Semiconductor is keeping an eye on you

Beware of delivery men bearing IoT gifts, warns, Donnie Garcia, ARM, who also looks at trap doors and NXP’s Kinetis KBOOT bootloader to foil a new attack vector and advertise a related webinar on April 25.

Nagging parents had the right idea, decides Russ Klein, Mentor Graphics, remembering entreaties to turn off lights, and whose energy saving advice he now applies to SoCs and embedded systems, with the help of the Veloce emulator.

Gabe Moretti, Chip Design, gets a bit saucy, trying to figure just what is Portable Stimulus. He gets down to the nitty gritty with how the Accellera System Initiative can help, but still believes some areas need to attended to. Let’s hope the industry pays heed.

More warnings from Kris Ardis, Maxim Integrated, and connected devices. While a Jacquard print may not be to everyone’s taste, the idea of protecting the IoT and its data has universal appeal.

The appeal of Agile design is not lost on Randy Smith, Sonics, who writes about the concept and Agile software development. He deftly dives into advances in Agile hardware design and IC methodology for Agile techniques – keeping every design engineer on their toes.

A visit to ISC West, the security expo, has made Jason Liu, ON Semiconductor, think about surveillance systems, as he throws a spotlight on one of the company’s introductions.

14 minutes does not sound like a long time to pack in all you need to know about Zynq UltraScale+ MPSoCs and Vivado Design Suite, but Steve Leibson, Xilinx points readers towards an interesting, informative video, which he describes as a fast and painless way to see the development tools used in a fully operation system.

It sounds like a self-satisfied neck-warmer, but SNUG (Synopsys User Group) events can be informative. Tom De Schutter attended the one in Silicon Valley and relates what he learned from the technical track with experts from ARM, NVIDIA, Intel and Synopsys about prototyping latch-based designs, ARM CPU and GPU increasing densities and more besides.

Striving to improve the lot of IoT designers, John Blyler, Embedded Systems, talks to Jim Bruister, SOC Solutions, about markets, licensing, open source and five elements that will drive improvement.

Compiled by Caroline Hayes, Senior Editor

Cadence Launches New Verification Solutions

Tuesday, March 14th, 2017

Gabe Moretti, Senior Editor

During this year’s DVCon U.S. Cadence introduced two new verification solutions: the Xcelium Parallel Simulator and the Protium S1 FPGA-Based Prototyping Platform, which incorporates innovative implementation algorithms to boost engineering productivity.

Xcelium Parallel Simulator

.The new simulation engine is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, internet of things (IoT) and automotive projects.

The Xcelium simulator offers the following benefits aimed at accelerating system development:

  • Multi-core simulation improves runtime while also reducing project schedules: The third generation Xcelium simulator is built on the technology acquired from Rocketick. It speeds runtime by an average of 3X for register-transfer level (RTL) design simulation, 5X for gate-level simulation and 10X for parallel design for test (DFT) simulation, potentially saving weeks to months on project schedules.
  • Broad applicability: The simulator supports modern design styles and IEEE standards, enabling engineers to realize performance gains without recoding.
  • Easy to use: The simulator’s compilation and elaboration flow assigns the design and verification testbench code to the ideal engines and automatically selects the optimal number of cores for fast execution speed.
  • Incorporates several new patent-pending technologies to improve productivity: New features that speed overall SoC verification time include SystemVerilog testbench coverage for faster verification closure and parallel multi-core build.

“Verification is often the primary cost and schedule challenge associated with getting new, high-quality products to market,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Xcelium simulator combined with JasperGold Apps, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform offer customers the strongest verification suite on the market”

The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Protium S1

The Protium S1 platform provides front-end congruency with the Cadence Palladium Z1 Enterprise Emulation Platform. BY using Xilinx Virtex UltraScale FPGA technology, the new Cadence platform features 6X higher design capacity and an average 2X performance improvement over the previous generation platform. The Protium S1 platform has already been deployed by early adopters in the networking, consumer and storage markets.

Protium S1 is fully compatible with the Palladium Z1 emulator

To increase designer productivity, the Protium S1 platform offers the following benefits:

  • Ultra-fast prototype bring-up: The platform’s advanced memory modeling and implementation capabilities allow designers to reduce prototype bring-up from months to days, thus enabling them to start firmware development much earlier.
  • Ease of use and adoption: The platform shares a common compile flow with the Palladium Z1 platform, which enables up to 80 percent re-use of the existing verification environment and provides front-end congruency between the two platforms.
  • Innovative software debug capabilities: The platform offers firmware and software productivity-enhancing features including memory backdoor access, waveforms across partitions, force and release, and runtime clock control.

“The rising need for early software development with reduced overall project schedules has been the key driver for the delivery of more advanced emulation and FPGA-based prototyping platforms,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Protium S1 platform offers software development teams the required hardware and software components, a fully integrated implementation flow with fast bring-up and advanced debug capabilities so they can deliver the most compelling end products, months earlier.”

The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Blog Review – Monday, February 13, 2017

Monday, February 13th, 2017

Among this week’s topics: two important announcements: the OpenFog Consortium and IEEE Standard for the Functional Verification Language e; a panel discusses the Internet and beyond; Mentor Graphics applies IoT to PCB design; FASTR accelerates the connected car and why USB is not as easy as 123

The importance of IP blocks is a given, but Rocke Acree, ON Semiconductor, explains how selection also has to consider technology and support tools. The company has collaborated with Hexius Semiconductor to qualify analog IP blocks to reduce design cycles and development time.

There are specific constraints, challenges and design requirements for PCBs designed for the burgeoning IoT market. John McMillan, Mentor Graphics has created a two-part blog focused on this topic.

Doing a quickstep around the topic of USB, Eric Huang, Synopsys, explores verification and FPGA prototyping for best results. He recommends some design rules, a test site, then curiously, throws in some political comment, a film review and dance-related jokes to end the blog.

It may not be an understatement by Rhonda Dirvin, ARM, to say that the day the OpenFog Consortium announced its reference architecture is the day we have all been waiting for. Hyperbole? Possibly not, as it defines how secure, interoperable products should be built – just what the connected world needs. She helpfully includes a link to the architecture, and a heads-up on a presentation at Mobile World Congress in Barcelona, Spain (Feb 27 to March 3).

If there is an award for Most Apt Acronym, the Future of Automotive Security Technology Research (FASTR) consortium, must be a contender. The uncredited Rambus blog reviews the brief history of the consortium, and discusses its recent manifesto, looking at why it is need for a secure, connected vehicle industry.

2017 begins with the publication of IEEE Std 1647 2016, the IEEE Standard for the Functional Verification Language e. of 2017. Efrat Shneydor, Cadence Design, looks at the enhancements which have been made and proficiently summarizes the highlights.

Generic connectivity is not enough – NASA has been designing, building and launching satellite systems with the goal of providing connectivity throughout the world. The concept and realities of the Internet of Space is the panel discussion topic, reported by John Blyler, Chip Design Magazine.

Caroline Hayes, Senior Editor

Blog Review – Monday, January 23, 2017

Monday, January 23rd, 2017

This week’s blogs show the human face of automated driving; and why energy should be taken seriously. There is lift-off for SpaceX to bring more satellite comms and a poetic turn, in the style of Rudyar Kipling’s classic poem.

There is a human element to automated driving, namely Human Machine Interface (HMI) and Jack Weast, Intel, uses his second blog post to examine how and why it can be used. He promises more in part three into the company’s research.

Energy is a serious business, says Grant Pierce, Sonics, and the electronics industry must shoulder some responsibility for power savings. The company, with Semico Research is conducting a survey and wants your help into understanding today’s and tomorrow’s power requirements.

Boosting the satellites to provide point-to-point communications, the SpaceX Falcon 9 rocket put the first 10 Iridium NEXT satellites into Low Earth Orbit (LEO), equipped with Xilinx space-grade Virtex-5QV FPGAs to implement the satellites’ On Board Processor (OBP) hardware. Steve Liebson, Xilinx, includes a link to a video describing the constellation and the launch.

Celebrating the relationship with Ericsson, Dassault Systèmes’ Olivier Ribet, looks at how the latter’s Networked Society will transform the way we interact with the world around us and meet technology challenges, such as 5G, IoT and the cloud.

Moving to 10nm and lower process geometries pushes the boundaries of FinFET and the custom layout flow and this means trouble ahead, warns Graham Etchells.

A touch of culture, with a poem “wot I wrote” by Keith Hanna, Mentor Graphics. He deftly tackles Computational Fluid Dynamics (CFD) as Rudyard Kipling might.

Image data and the mysteries of how to create, access and use a Qimage to greatest effect is detailed by Laszlo Agocs, Qt, with three case studies to illustrate what can be done.

A sharp video addressing the interconnect verification challenges is hosted by Nimrod Reiss. Cadence’s Corrie Callenbach has found and highlighted the video.

Caroline Hayes, senior editor

Blog Review – Tuesday, November 22, 2016

Tuesday, November 22nd, 2016

New specs for PCI Express 4.0; Smart homes gateway webinar this week; sensors – kits and tools; the car’s the connected star; Intel unleashes AI

Change is good – isn’t it? Richard Solomon, Synopsys, prepares for the latest draft of PCI Express 4.0, with some hacks for navigating the 1,400 pages.

Following a triumphant introduction at ARM TechCon 016, Diya Soubra, ARM, examines the ARM Cortex-M33 from the dedicated co-processor interface to security around the IoT.

Steer clear of manipulating a layout hierarchy, advises Rishu Misri Jaggi, Cadence Design Systems. She advocates the Layout XL Generation command to put together a Virtuoso Layout XL-compliant design, with some sound reasoning – and a video – to back up her promotion.

A study to save effort is always a winner and Aditya Mittal and Bhavesh Shrivastava, Arrow, include the results of their comparisons in performing typical debug tasks. Although the aim is to save time, the authors have spent time in doing a thorough job on this study.

Are smart homes a viable reality? Benny Harven, Imagination Technologies, asks for a diary not for a webinar later this week (Nov 23) for smart home gateways – how to make them cost-effective and secure.

Changes in working practice mean sensors and security need attention and some help. Scott Jones, Maxim Integrated looks at the company’s latest reference design.

Still with sensors, Brian Derrick, Mentor Graphics Design, looks at how smartphones are opening up opportunities for sensor-based features for the IoT.

This week’s LA Auto Show, inspires Danny Shapiro, NVIDIA, to look at how the company is driving technology trends in vehicles. Amongst the name dropping (Tesla, Audi, IBM Watson) some of the pictures in the blog inspire pure auto-envy.

A guide to artificial intelligence (AI) by Douglas Fisher, Intel, has some insights into where and how it can be used and how the company is ‘upstreaming’ the technology.

Caroline Hayes, Senior Editor

Blog Review – Monday 07 November 2016

Monday, November 7th, 2016

Browsing the MIT Library; AI and HPC for cancer breakthroughs; FPGAs on Mars; Romancing ISO 26262; It’s IoT conference season; Who’s going to pay?

For smart and connected IoT devices, Intel has introduced the Intel Atom processor E3900 and Ken Caviasca, Intel explains how the series brings computing power nearer to the role of the sensor.

Crash scenes from Mars, as taken by the Mars Reconnaissance Orbiter’s High Resolution Imaging Science Experiment (HiRISE) reveal features previously unseen on the planet. Steve Leibson, Xilinx, explains how we have FPGAs to thank. (For the images, not the crash!)

Ahead of GE’s Minds & Machines Conference (November 15-16, San Francisco) Lane Lewis, Ansys, celebrates the marriage of the Simulation Platform and Predix Platform to create a profitable asset health monitoring and the industrial IoT.

As mobile payment matures, Martin Cox, Rambus Bell ID, identifies that tokenization is becoming a hot topic. His blog explains the role of the company’s Token Gateway as a means to integrate multiple mobile payment schemes. No excuse not to get a round of drinks in now.

Moving automotive and safety into the realm of Dungeons and Dragons, Paul McLellan, Cadence, reviews the recent DVCon Europe and how ISO 26262 – the critical safety standard – became a theme, but not necessarily one to dread and fear or avoid. Like St George, you just have to grit your teeth and tackle it head-on, to find the pot of gold that is critical safety design success.

Fresh from IoT Planet in Grenoble, France, Andrew Patterson, Mentor Graphics, is occupied by two topics – connectivity and security. He shares some interesting thoughts and statistics around these gleaned from the event.

Fascinating insights into the world of bio-medicine and computational bio-medicine are provided by Dr Michael J McManus, Intel. He explains how Artificial Intelligence (AI) and High Performance Computing (HPC) are used by researchers to analyze data and predicts an era of revolutionary cancer breakthroughs, of both drug development structures and genome analytics running on a single Intel cluster using Intel Xeon, Intel Xeon Phi processors and Intel Omni-Path architecture.

There is a fascinating collection of rare books at MIT, exhibited to mark Ada Lovelace Day. For those can’t walk the aisles of the MIT Libraries, Stephen Skuce, MIT Libraries, shows us through some of the collection relating to women who have contributed to science, math and engineering with its annual celebration of the history of women in the STEM (Science Technology, Engineering and Mathematics) subjects.

Caroline Hayes, Senior Editor

Blog Review –Monday, October 24 2016

Monday, October 24th, 2016

The how, what and why of time-of-flight sensors; Conference season: ARM TechCon 2016 and IoT Solutions Congress; Save time on big data analysis; In praise of FPGAs; Is it time for augmented and virtual reality?

Drastically reducing big data analysis is music to a data scientist’s ears. Larry Hardesty reports on researchers at MIT (Massachusetts Institute of Technology) have presented an automated system that can reduce preparation and analysis from months to just hours.

Keeping an eye on the nation’s bank vaults, Robert Vamosi, Synopsys, looks at the what bank regulators are doing to ramp up cybersecurity.

If you can’t head to Barcelona, Spain this week for IoT Solutions World Congress (October 25-27), Jonathan Ballon, Intel, reveals what the company will unveil, including a keynote: IoT: From Hype to Reality, what 5G means, smart cities and a hackathon.

Tired of the buzz, and seeking enlightenment, Jeff Bier, Berkeley Design, delves into just what is augmented reality and virtual reality. He examines hardware and software, markets and what is needed for widespread adoption.

Closer to home, 2016 ARM TechCon, in Santa Clara, California (October 25 – 27), Phil Brumby, Mentor Graphics, offers a heads-up on its industrial robot demo, using Nucleus RTOS separated by ARM TrustZone, and the ECU (Engine Control Unit) demo in a Linux-hosted In-Vehicle Infotainment (IVI) system. There is also a technical session: Making Sure your UI makes the most of the ARM-based SoC (Thurs, 10.30am, Ballroom E)

The role of memory is reviewed by Paul McLellan, Cadence Design System, as he discusses MemCon keynotes by Hugh Durdan, VP of the IP Group and Steve Pwalowski, VP of Advanced Computing Solutions at Micron. There is comprehensive pricing strategy and a look at industry trends.

A teardown of the Apple iPhone 7, by Dick James, Chipworks, links STMicroelectronics’ time-of-flight sensors with the Starship Enterprise. The blog has a comprehensive answer to questions such as what are these sensors and why are they in phones.

If the IoT is flexible, Zibi Zalewski, Aldec, argues, then FPGAs can tailor solutions without major investments in an ASIC. He takes Xilinx’s Zynq-7000 All-Programmable SoC as a starting point and illustrates how it can boost performance for IoT gateways.

Elegantly illustrating how multiple Eclipse projects can be run on a single microcontroller with MicroEJ, Charlottem, ARM, runs through a connected washing machine that can communicate via Bluetooth, MQTT, Z-Wave and LWM2M.

Caroline Hayes, Senior Editor

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