Part of the  

Chip Design Magazine

  Network

About  |  Contact

Posts Tagged ‘IP’

Next Page »

More space for satellites and a roadmap for data protection

Monday, February 12th, 2018

Blog Review – Monday, February 12, 2018
This week’s selection includes 100G Ethernet for data centers; Satellites will vie for space; A roadmap for data protection, and more from the blogsphere

The rise of data centers and increase in cloud-based computing has prompted Lance Looper, Silicon Labs, to examine how wireless networks are changing to meet the demands for performance and low latency and implementing 100G Ethernet.

https://www.silabs.com/community/blog.entry.html/2018/02/05/ethernet_s_role_inh-pTeJ

Marveling at how connectivity has ‘shrunk’ the world, Paolo Colombo, ANSYS, looks skywards to consider the growth of connected devices. He looks at the role of space satellites and how small satellites will have their day for critical applications and introduces ‘pseudo sats’ which are vying for space in space.

An article about medical device design and manufacturing challenges has prompted Roger Mazzella, QT, to address each and provide a response to reassure developers. Naturally, QT’s products play a role in allaying many fears, but it is an interesting insight into the medical design arena.

An interesting case study is recorded by Hellen Norman, Arm, featuring Scratchy the robot. She asks German embedded systems developer, Sebastian Förster how he used a Cortex-M4, some motors, Lego bricks and cable ties to create a four-legged robot, programmed to walk using artificial intelligence (AI).

It’s not unusual to feel bewildered at a technology conference, so we can sympathise with Thomas Hackett, Cadence, who has a twist on the usual philosophical question of “What am I here for?” A walk through DesignCon caused a lightbulb moment, illuminating the real world interplay of IP, SoC and packaging.

With the IoT there are no secrets, and Robert Vamosi, Synopsys examines how data sharing may not be as innocuous as companies would have us believe, if it is not configured flawlessly. The Strava heatmap which reveals secret military locations has thrown up some serious issues which, we are assured, are being addressed, and which Vamosi sees as a model for other IoT and wearable device manufacturers.

Tackling software-defined networking (SDN) head-on, Jean-Marie Brunet, Mentor Graphics, presents a clear and strong case for accelerating verification using virtual emulation. Of course he advocates Veloce VirtuaLAB PCIe for the task, but backs up his recommendation with some sound reasoning and guidance.

By Caroline Hayes, Senior Editor

Driving To the Shops with Graphics and Bluetooth

Monday, January 29th, 2018

The car’s the star this week, as bloggers look to upgrade models, examine the safety systems, and look at how to use graphics. Other posts concentrate on retail therapy and how Bluetooth can help warehouses manage stock and processes

There’s only 330 days shopping days until Christmas, and Intel’s Ryan Parker’s blog could change how those days pan out as retail is redefined with IoT, artificial intelligence (AI), and digital signage combined with video to make the shopping experience to not only meet customer demands, but changing supply chains too.

Examining the backbone of automotive safety systems, Sandeep Taneja, Synopsys, presents an informed and well-illustrated post on what is needed and for what purpose in safety conscious vehicles.

Graphics double data rate (GDDR) memory has evolved to exceed the realm of gamers and is now used in vehicles. A blog by Rambus charts the changes and benefits of graphics technology for both inside and outside the car, and how it can be used in other markets.

The spread of the industrial IoT brings opportunities for warehouses of the future, writes Torbjørn Øvrebekk, Nordic Semiconductor. He looks at what the Bluetooth Mesh standard will mean and the benefits it will bring for networks and energy useage.

Corrie Callenbach, Cadence, has identified a great video hosted by Nick Heaton, distinguished engineer, Cadence, describing the verification challenges for SoCs when integrating CCIX (Cache Coherent Chip-to-Chip Protocol) IP.

Aligning CAD to a car leads an anonymous blogger at Altium to reminisce about old cars owned, cared for, restored, driven and abandoned when adulthood beckoned and manages to make a comparison with upgrading to the 64-bit world where PCB designers now live and work. Nostalgia mixes with practical tips on scaling up.

Caroline Hayes, Senior Editor

Blog Review – Monday, April 24, 2017

Monday, April 24th, 2017

This week’s blogs are concerned with AI and intelligent, connected vehicles, sometimes both. There are quests to find the facts behind myths and searches for answers for power management and software security too.

Is an effective tool for verification, the stuff of legends? Gabe Moretti, Chip Design Magazine, seeks the truth behind Pegasus – no, not the winged horse, the more earthly verification engine from Cadence.

A power strategy is one thing, but a free trial adds a new dimension to energy management. Don Dingee, Sonics, elaborates on the company’s plan to bring power to the masses, using hardware IP and ICE-Grain Power architecture.

If you are unsure about USB, Senad Lomigora, ON Semiconductor’s blog should help. It looks at what it’s for, why we can’t get enough of USB Type C, USB 3.1, connectors and re-drivers.

Every vehicle’s ADAS relies on good visuals, observes Jim Harrison, guest blogger, Maxim Integrated, and good connectivity. He looks at the securely connected autonomous car, and then homes in on explained how Maxim Integrated exploits GMSL, an alternative to Ethernet, in its MAX96707 and MAX96708 chips, to create an effective in-car communication network.

Still with the connected car, Pete Decher, Mentor Graphics, is fresh from the Autotech Council meeting in San Jose. The company’s DRS360 Autonomous Driving Platform launch was high on the list of discussion topics, along with the role of artificial intelligence (AI) in the future of driving.

Still with AI, Evens Pan, ARM provides an in-depth blog on Chinese start-up, Peceptin’s enabled embedded deep learning. The case study is fascinating and well reported in this comprehensive essay.

Making any software engineer feel insecure about software security is an everyday occurrence, helping them out is a little more out-of-the-ordinary, so if it refreshing to see a post from the editorial team, Synopsys, letting the put-upon software engineer know there is a webinar coming soon (May 2) to enlighten them on the Building Security In Maturity Model (BSIMM), with a link to register to attend.

Caroline Hayes, Senior Editor

Determining a Fair Royalty Value for IP

Monday, March 13th, 2017

Gabe Moretti, Senior Editor

The legal case between Apple and Qualcomm made me ask: “What is a fair royalty a supplier can charge a user?”  The answer is not clear, since the product that uses the IP can benefit in many different way from the IP.  I asked a few questions to exponents of the IP business and I received answers that, even if they do not provide one solution, clear the issue significantly.

In this article I will cover answers from Robert (Bob) Smith, executive director of the ESD Alliance, Warren Savage, general manager of IP at Silvaco, Farzad Zarrinfar, Managing Director of Novelics, Mentor Graphics, and Grant Pierce, CEO of Sonics and also Chairman of the Board of the ESD Alliance.

I am publishing Grant’s response as a separate article with the title: “Behold the Intrinsic Value of IP “.

It must be noted that the ESD Alliance has launched a project called “IP Fingerprinting Initiative” using technology from Silvaco.

Chip Design (CD): Should royalties be fixed at a certain amount regardless of the sale price of the unit that use the licensed IP? Or, should royalties be a percentage of the price charged to the customer of the end product?

Robert Smith (RS): Royalties should be based on value provided. Value comes in many forms, such as how much of the functionality of the end product is provided by the IP, the risk and time-to-market reduction, and design and verification cost savings. There is no simple formula for IP royalties. In fact, they can be quite complicated.

Warren Savage (WS): Business models used for licensing royalties are ALWAYS a negotiation between the buyer and seller with each party striving to optimize the best outcome for their business. In some cases, the customer may be willing to pay more for royalties in exchange for lowering the upfront licensing costs. A different customer may be willing to invest more upfront to drive down the cost of royalties. Calculation of the actual royalty amounts may be based on a percentage of the unit cost or a fixed price, and each may have sliding scales based on cumulative volumes. Both parties need to derive the value that fits their own business model. The IP user needs to arrive at a price for the IP that supports the ROI model for the end product. The IP supplier needs to ensure that it receives sufficient value to offset its investment in IP development, verification and support. It is able then to participate in the success of the buyer’s product based (at least in part) on the value of the IP provided.

Farzad Zarrinfar (FZ): No. It will not be practical.  Royalty is a form of payment for IP licensing. Using royalty-based payment, IP providers can share the business risk and rewards with IP users.  Royalty is typically “negotiable” and is dependent to a variety of parameters such estimated volume, estimated product life, IP value, the amount of R&D invested in IP development, the business model for IP suppliers, competitive landscape for IP, and others. In reality, good relationships between IP users and IP providers are important in developing a win-win business model.  IP royalty is negotiable. However, some of the most utilized models are:

  • Royalty fee, as a percentage of end product selling price (i.e. the selling price of packaged IC)
  • Royalty fee, as a percentage of end-product cost (i.e. die cost)
  • Royalty fee, as a percentage of wafer revenue that the foundry generates
  • Royalty fee, as a portion of cost saving that IP providers offer to IP users.

CD: What is the intrinsic value of an IP?

WS: An IP has ZERO intrinsic value in of itself. The value is completely dependent on the application in which it is used, the ability of the IP to offset development costs and risks and the contributions it makes to the operation and success of the target product. For example, an IP that is developed and ends up sitting on the shelf has no value at all. In fact, its value is negative given the resources and costs spent on developing it. Size doesn’t matter. An IP that has hundreds of thousands of gates may command a higher price because the IP supplier needs to sell it for that price to recoup its investment in creating it.  A small IP block may also command a high price because it may contain technology that is extremely valuable to the customer’s product and differentiates it significantly from the competition. The best way to think about intrinsic value is to think of it in the context of value delivered to the customer. If there is no apparent difference in this regard between an IP product from two or more suppliers, then the marketplace sets the price and the lowest cost supplier wins.

FZ: It depends from various situations such as;

The value could be related to the cost saving for IP user. In the slide below, several cost savings have been calculated.

The value could be related to the time-to-market saving or the saving for IP implementation. These will impact “build vs buy” decisions.


How many times can the owner of the IP charge for its use in the same system to the same customer?

WS: This again is a negotiation determined by the buyer and seller. As long as both parties receive what they perceive as fair value, there is no magic number.

FZ: If I understand your question correctly, the typical licensing model is “step-function” or “flat”. In step-function, IP providers offer a licensing fee for “First-Use”, “first-re use”, and “second re-use & beyond”. Therefore, the more designs customers do, proportionally, more IP builders generate revenue. In addition, royalty revenue for differentiated IPs offer scalable business for IP providers. Therefore, more successful and higher volume the chip supplier gets, will also benefit IP provider by royalty.

Royalty can be paid in several forms. Following are several popular royalty payments:

  • Per parts
  • Per wafer
  • Buy out
  • Buy down
  • Royalty with Cap
  • Royalty with step function

It is also important to structure a solid tracking system to track and verify the proper value of paid royalty. In this case, as President Ronald Reagan said “I trust you, but I need to be able to verify”.

CD: How can the owner of the IP protect it from illegal use by customers?[NVC1]

WS: This is the great problem we have in the IP industry today. Approximately 99% percent of IP is delivered to customers in source code form and IP companies rely on the good faith of their customers to use it within the scope of the license agreement. However, there is a fundamental problem. Engineers rarely know what the usage terms and restrictions of the agreement their company has with the IP supplier, so it is quite easy for a semiconductor company to be in violation—and not even know it. New technologies are coming into play, such as the IP fingerprinting scheme that the ESD Alliance is promoting. Fingerprinting is a “non-invasive” approach that protects both IP suppliers and their customers from “accidental reuse.”

RS: IP suppliers can utilize The Core Store (www.the-core-store.com) at no charge to showcase their products and register “fingerprints” of their technology. Semiconductor companies can use this registry to detect IP usage within their chips by means of “DNA analysis” software available through Silvaco.


[NVC1]Warren and Bob changed the question a bit.

Blog Review – Monday, December 19, 2016

Monday, December 19th, 2016

Today’s the day -Bluetooth 5 and ARM is ready; A vision for disruptive technologies; When being better connected counts; Memory – the jewel in the crown; Functional Safety, in three video parts

At the launch of Bluetooth 5, Paul Williamson, ARM, celebrates the contribution of the ARM Cordio IP, qualified to Bluetooth 5 standards, available on the day that qualifications are available.

Gearing up for some disruption in the automotive market, Jeff Bier, Berkley Design, anticipates the role of computer vision and how it is central to autonomous vehicles. His view has shifted from an enhancement for the automotive industry to a transforming force.

Functional safety is adroitly explained by Charles Qi, highlighted by Corrie Callenbach, Cadence Design System. This is the second of a three-parter Whiteboard Wednesdays video series – all well worth a viewing.

Jeff Klaus, Intel, is wondering where has Pokémon Go, gone. His blog looks at the demands on data centers for the future and the world of connectivity of IoT, wearables, navigation devices and their impact on enterprise servers.

https://www.mentor.com/products/fv/blog/post/-that-s-unusual-memory-consistency-acc55210-aa68-41ea-95a3-9f598548e7ec

An audacious jewelery heist by elderly thieves inspires Russell Klein, Mentor Graphics Design, to ponder how Big Data and memory was their downfall, and how CodeLink brings memory consistency.

The connected world is occupying Joe Bryne, NXP and the danger posed by malicious software running on internet connected devices, with a touch of ‘I told you so’, and advocating prevention is better than cure.

Blog Review – Tuesday, May 31 2016

Tuesday, May 31st, 2016

Security issues around IoT and maritime vessels; CCIX Consortium accelerates data centers; Cheers for metering; Noise integrity in ADAS; Virtual Reality in practice

Protecting IoT devices is clearly and elegantly outlined by Jim Wallace, ARM, he includes illustrations, a lot of information and guidelines on advice on how security can produce new business models.

Accelerating data centers always raises interest and when names like AMD, ARM, Huawei, IBM, Mellanox, Qualcomm, and Xilinx come together. Steve Liebson, Xilinx, describes how the companies, via the CCIX (Cache Coherent Interconnect for Accelerators) Consortium are developing a single interconnect technology specification whereby processors using different instruction set architectures can share data with accelerators and enable efficient heterogeneous computing to improve efficiency.

Advocating an alternative to the plan to drink beer when the fresh water runs out, David Andeen, Maxim explains the importance of an ultrasonic water meter which can accelerate design cycles and reduce the cost of meters.

All in the name of research, Alexandru Voica, Imagination, tries his hand at Daydream, the Virtual Reality (VR) platform built on Android N and outlines the rules of VR.

Another cyber threat is identified by Robert Vamosi, Synopsys. His blog looks at research from Plymouth University and how vulnerable marine vessels can be at risk.

The undeniable increase in Advanced Driver Assistance Systems (ADAS) needs careful design consideration, and Ravi Ravikumar, ANSYS, discusses how the ANSYS CPS simulation helps power noise integrity to be met. His blog is informative, with some clear graphics to illustrate ADAS design.

For a quick catch-up on USB 3.1 and the Type-C connector, turn to Chris A Ciufo, eecatalog, for a quick reference guide. He includes some handy links for extra reading.

A review of the Bangalore, India, Design&Reuse event is provided by Steve Brown, Cadence Design Systems. A rundown of keynotes ends with a head-up for the next event.

Blog Review – Monday, April 25 2016

Monday, April 25th, 2016

System validation partnership; Cloud’s blue sky thinking; Happy 50 th optic fiber; Back to PCIe basics; Pointing the fingerprint; Financial forecast

Retracing his steps, Richard Solomon, Synopsys, looks at the progress of PCI Express, and more specifically, how to handle the bandwidth increases. This blog details some solid principles and extends an offer of help for developers.

Fresh from rubbing shoulders with attendees of the SAE World Congress automotive industry technical conference and tradeshow, Pete Decher, Mentor Graphics, clearly has his eye on the latest Tesla model and its plans for autonomous driving. He reviews reactions to V2X (Vehicle to Infrastructure & Vehicle to Vehicle) and ECU (Electronic Control Unit) Consolidation.

Another review is delivered by Steve Brown, Cadence Design Systems, who attended the Optical Fiber Conference. He manages to celebrate the 50 th anniversary of fiber optic communications technology and looks at how it started and where it’s going.

Poring over financials is not everyone’s idea of fun, but Chris Ciufo, eecatalog, takes one for the team and compiled this blog about the economical outlook for the technology industry. He considers the role of the IoT, autonomous vehicles and their role on productivity.

Best practice for cloud computing is set out in the blog from Wim Slagter, ANSYS. He elaborates on eight Dos and Don’ts for High Performance Computing (HPC) and cloud computing to maximize it for engineering simulation.

Identifying the bottleneck of functional validation in SoC design, Eoin McCann, ARM, examines some of the IP tools the company offers to its ecodesign partners

New tools reduce the risk of IP reuse, believes Warren Savage, IP Extreme. He sets out a clear case for fingerprinting IP, a brief checklist and explains how Chip DNA Analysis software can be used in SoC design.

Caroline Hayes, Senior Editor

Blog Review – Monday, March 07, 2016

Monday, March 7th, 2016

IP fingerprinting; Beware- 5G!; And the award goes to – encryption; Fear of FinFET; Smart kids; Virtual vs real hardware

Keeping an eye on the kids blends with wearable technology, as demonstrated by the Omate Whercom K3, which debuted at Mobile World Congress 2016. It relies on a 3G Dual-core 1GHz ARM Cortex-A7 and an ARM Mali-400 GPU, relates Freddi Jeffries, who interviews Laurent Le Pen, CEO of Omate.

The role of MicroEJ has evolved since its inception. Brian Fuller, ARM, looks at the latest incarnation, bringing mobile OS to microcontroller platforms such as the ARM Cortex-M.

Rather overshadowned by the Oscars, the winner of this year’s Turing Award could have more impact on everyday lives. It was won, says Paul McLellan, Cadence Design Systems, by Whitfield Diffie and Martin Hellman for the invention of public key cryptography. His blog explains what the judges liked and why we will like their work too.

The inclusion of a Despicable Me photo/video is not immediately obvious, but Valerie Scott, Mentor Graphics makes a sound argument for the use of a virtual platform and includes a (relevant) image of the blog’s example hardware, the NXP i.MX6 with Vista.

Everyone is getting excited about 5G, and Matthew Rosenquist, Intel, sounds a note of caution and encourages readers to prepare for cyber risks as well as the opportunities that the technology will bring.

Fed up with FinFET issues? Graham Etchells, Synopsys, offers advice on electro-migration, why it happens and why the complexity of FinFETs does not have to mean it is an inevitable trait.

Efficiency without liabilities is the end-goal for Warren Savage, IP Extreme. He advocates IP fingerprinting and presents a compelling argument for why and how.

Caroline Hayes, Senior Editor

Blog Review – Monday, July 27 2015

Monday, July 27th, 2015

IoT for ADAS; ESC 2015 focuses on security; untangling neural networks; what drives new tools; consolidation conundrum; IoT growth forecast; three ages of FPGA

Likening a business collaboration to a road trip may be stretching a metaphor that would make Jack Kerouac blush, but David McKinney, Intel, presses on as he explains Intel and QNX’s ADAS solution, based on Intel IoT for automobiles. He includes some interesting links and a video to inform the reader.

A review of ESC 2015 shows that Chris Ciufo is not only ahead of the curve, advocating embedded security, but also not one to pass by a freebie at a show. He relates some of the highlights from the first day of the Santa Clara event.

Neural network processors hold promise for computer vision, believes Jeff Bier, BDTI. His blog explains what work is needed for the scale of computation the industry expects.

Posing an interesting question, Carey Robertson, Mentor Graphics, asks what prompts the development of new tools. He blends this with helpful information about the newly launched Calibre xACT extraction tool, without too much “hard sell”.

“It works!” is the triumphant message of the blog co-authored by Jacek Duda and Steve Brown, Cadence. Reporting from this month’s workshop where Type-C USB was put through its paces.

What to do with wireless IP is asked and answered by Navari Nandra, Synopsys. He explains what can be done and how it can contribute to the IoT.

The SoC market is consolidating fast, says Rupert Baines, UltraSoC, on an IP Exteme blog. This poses two challenges that he believes licensed IP can simplify.

A common proposition is to move from Intel to ARM, and Rich Nass, ARM presents a well-rounded blog on how to make the transition, with some input from WinSystems hardware and software experts.

Forget consumer, the future of the IoT growth is in enterprise, reports Brian Fuller, ARM, observing analyst IDC’s webinar on which parts of the IoT will be lucrative and why.

Recalling the talk by Xilinx Fellow, Dr. Steve Trimberger, Steve Leibson, explains the three ages of the FPGA, with a link to a video on the history of the technology.

Caroline Hayes, Senior Editor

eSilicon Launches Integrated ASIC Design And Manufacturing Platform

Tuesday, May 26th, 2015

Gabe Moretti, Senior Editor

Since 2001 eSilicon has helped system companies with some of the most time consuming tasks needed to successfully manage a chip development project.  Today the tools provided by eSilicon allow customers to: browse and buy IP, Optimize a design, get quotes from foundries and compare them, and track a project.  Just in time for DAC, the company announced the availability of its second-generation online ASIC design and manufacturing platform the groups all of the tool under a unified and coherent environment.

Figure 1: The STAR Logical Architecture

Named eSilicon STAR (self-service, transparent, accurate, real-time), the platform supports eSilicon’s existing IP browsing, instant quoting and work-in-process tracking capabilities along with a new chip optimization offering that leverages design virtualization technology. The platform also delivers an enhanced user interface with simplified account setup and access. Tool names have also been unified under the STAR platform as follows:

  • Navigator: Search, select and try eSilicon IP online
  • Optimizer: Versatile self-service IC design optimization for power, performance and area
  • Explorer: Evaluate options and get fast, accurate quotes for MPW and GDSII handoffs
  • Tracker: Real-time design progress and IC delivery tracking, including order history, forecasts and yield data

Figure 2: Details of STAR’s  Components

The newly introduced STAR Optimizer provides ASIC designers with an easy way to access eSilicon’s block- and chip-level optimization services. Users can download free software that will analyze their design’s register transfer language (RTL) description to check for robustness. If the design passes these tests, users can then request a design optimization service engagement online. eSilicon’s design optimization service uses unique design virtualization technology to find the optimal design implementation from a power, performance or area perspective. The service is built on a “pay for results” philosophy – the customer pays for the service only if a pre-determined optimization result is achieved.

At first such income scheme may appear naïve when judged in a traditional EDA practice of quarter by quarter revenue measurement, but I think that the approach has great value from a strategic point of view.  It builds not customers but partners that feel they are being treated fairly, and this is the secret to the success of eSilicon: find partners, not just sources of income.

“We have been using our design virtualization technology to optimize the PPA of customer designs for years,” said Prasad Subramaniam, Ph.D., vice president of design technology at eSilicon. “We’ve achieved some significant results in literally minutes with this technology. We are now making this powerful capability available to all design teams worldwide through the STAR Optimizer interface.”

Optimizer is based on design virtualization technology, which rapidly explores all possible ASIC implementation scenarios to identify the best fit for a particular set of PPA and cost requirements. Design choices such as cell libraries, memory architectures, process options, operating conditions and Vt mix are enumerated instantly, without the need to perform time-consuming what-if implementation trials. Design virtualization uses big data analytics and machine learning to rapidly deliver the business and technical insights needed to build an optimized design.

“Our market research told us that the semiconductor community was ready for online technology and big data analytics,” said Mike Gianfagna, eSilicon’s vice president of marketing. “With over 500 users who have generated over 1,000 custom quotes in 47 countries, we have validation that our research was correct. The new eSilicon STAR platform takes the user experience to the next level, both from an ease-of-use and capability point of view.”

The eSilicon Star platform is available now. There is no cost or obligation to use any of the STAR tools. See for yourself how easy to use and how powerful it is in the eSilicon booth at DAC.

Next Page »

Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.