By Ann Steffora Mutschler
Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT — IEEE 1685, “Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP.

The IP-XACT technical committee has been busy over the past year. Formerly an effort of The SPIRIT Consortium, which merged with Accellera in April, the standard was ratified by the IEEE in June, and has since been downloaded hundreds of times, according to Accellera vice-chair Dennis Brophy, who also serves as director of strategic business development at Mentor Graphics Corp.

“In the first few months of operation we have had several hundred copies downloaded for free,” he noted. “We can predict a very good multi-year trajectory for making the standard easily available to users and consumers, and will help also promote a healthy SoC design environment enabled with IP-XACT.”

IP-XACT, which is an XML schema for meta-data documenting IP and an API that allows tools to access the meta-data, has its roots at STMicroelectronics dating back to 2003. Other vendors involved at a highly visible level include Atrenta, Semifore, NXP Semiconductors, Cadence, Duolog and AMD.

Accellera is well aware what work is not done, and one of the groups inside the standards body is a verification IP technical subcommittee, “whose initial task was to find a way to bring multiple methodologies together so that you could author in one environment and use in another. We proved that through bringing VMM and OVM together so that they could actually work side-by-side and users could author in one and use in the other. We had an open-source kit that users could download in conjunction with their preferred methodology to use and then promote verification IP interoperability,” Brophy explained.

That group took the next step of asking why there isn’t a single standard methodology and have begun work on UVM (universal verification methodology), which intends to bring together the best of all technologies to focus the industry development resources around one methodology – and this is where IP-XACT comes in, he continued.

As a result, the IP-XACT committee relaunched itself over the summer to determine where to go next and are now in the beginning phases of asking themselves that question and inviting other industry participants to join with the committee to start the next phase of development. One of those, interestingly enough, is what can be done to cross-pollinate between the UVM work that is going on, and what impact it will have on IP-XACT. “We know it should have some. IP-XACT has been what I would characterize as a very strong support for design IP that facilitates the design process, but has been a bit weaker in terms of delivery of verification IP,” Brophy observed.

“What Accellera sees is that we really need to have both comprehended in an IP-XACT so we have an ongoing cross-relationship between the technical subcommittees–the IP-XACT group and the VIP group in Accellera. The elements of development that are underway for UVM are, we hope, going to have a positive impact in being able to extend the IP-XACT definition to also comprehend use of verification IP just as the community has done so with design IP. And that is just at its very beginning stages right now,” he said.

While not making any 2011 predictions as to deliverables, Brophy stressed that participants are interested to move forward sooner rather than later, and expects more verification IP companies to join in as they learn about the effort.

For more information, or to download the standard, click here.

By Ann Steffora Mutschler
With the amount of IP blocks being integrated in SoCs today – in some cases as many as 100 blocks in a single chip – SoC design methodologies are shifting to address the new challenges this complexity brings. The good news is that these integration challenges has put the spotlight on the issues—along with the skyrocketing development costs for the creation, qualification, acquisition and integration of IP, which can account for as much as 25% of the total hardware design budget.

“There is an increasing amount of external IP being used and things are moving toward a printed circuit board-type methodology where we have large customers that are making several IPs and buying the rest, but we also have some smaller customers that only make one IP (the differentiator of their chip) and everything else is bought,” noted Charlie Janac, chairman, president and CEO of Arteris.

Design project managers are struggling to know how quickly that SoC can be assembled, what the cost is of the assembly, and how quickly the verification can be complete.

“The challenge is to quickly integrate IP that has multiple protocols. IP can be wrapped to chase a protocol, but that introduces unwelcome latency and risk. So you really want to use the native IP protocol that the IP comes in because that’s what is proven,” Janac said.

Further quantifying the situation today, Neil Hand, director of product marketing at Cadence Design Systems pointed out that “at 65 nm about a quarter of a $45 million design spend was spent on qualification of IP, which seems a little big but other customers tell us that for every dollar they spend on acquisition of IP they are spending $2 to $3 to make it work.”

The problem is “there is still a complete lack of consistency between the IP providers. There is no consistent set of standards for deliverables or consistent standards for quality or even what it means to be IP. Some vendors will say it has to be silicon proven when all they’ve actually done is put it in a test environment,” he said.

“Designers spend a lot of time creating the extra views, the extra models, and the extra things to integrate into their design before they can even get it to work. Even if you’ve got “silicon-proven IP” it doesn’t mean it works it all works well together,” Hand pointed out.

Mike Gianfagna, Atrenta’s vice president of marketing, believes this trend spells opportunity for EDA. “The shift from authoring to integration demands a new set of design tools to support reuse and integration. IP-XACT is one standard that is helping to drive this. There are others. At the center of the shift is the need for a rapid assembly, prototyping and validation tool set that works at a high level of abstraction on designs that are not yet complete. The need to interface to the software developer is also present here. These new tools will be in high demand, and should command a good average selling price. EDA hasn’t seen new budget dollars for quite a while – this new trend will break that streak.”

Cadence’s answer to this is its Open Integration Platform, whose stated goal is to reduce SoC development costs, improve quality and accelerate production schedules by concentrating on an application-driven development process and encouraging open, standards-based, collaboration within an ecosystem of production-proven semiconductor design companies, IP providers, foundries, service providers, EDA vendors and assembly houses. It is part of the company’s EDA360 view of next-gen, application-driven development. Cadence’s recent acquisition of Denali Software fits into this, as well.

The platform includes integration-optimized IP from the company and its ecosystem partners, an Integration Design Environment along with integration services. Cadence mixed-signal (analog and digital) design, verification and implementation products and solutions are the underpinning of the Open Integration Platform, the company said.

At the same time, while it has not been stated directly, Synopsys, with its acquisition of Virage Logic, is also expected to come out with IP subsystem products of its own at some point, possibly arranged around a sophisticated interconnect. ARM and Posedge also provide IP subsystems.

What does complexity mean for the interconnect?
While design teams have been using third-party and internally-developed IP in SoC designs for at least 10 years, what’s changed is that over time they have put more and more IP blocks onto the SoC. Today for high-end parts there could be upwards of 100 blocks on the SoC, according to Rich Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research.

“The connectivity between the IP blocks is absolutely critical because the advantage of the SoC may be that you can put all of these blocks on the same chip to get the performance, but if the interconnect is incorrect, improper or not efficient enough you lose all of the advantages that you just gained. The biggest issues on these things are the type of bus architecture you’re going to be using,” said Patrick Soheili, vice president of marketing and business development at eSilicon.

Technical issues surrounding the interconnect abound, including IP re-use; efficient transport (how quickly the data can be moved around the chip); memory bandwidth issues; the number of gates needed, and routing congestion.

There is also the issue of SoC services. Here, Janac believes the industry has been confused about where those services go – whether they belong in the IP, the memory controller or in the interconnect. “The network-on-chip (NoC)-type interconnect handles the data transactions (signal packetization), which gets the SoC data onto the network and the wiring and transport services which move the data all over the chip,” he said, noting that Arteris’ NoC supports SoC services—higher level functions that control the operation and performance of the SoC. SoC services include quality of service, security, power domain management, frequency domain management and software debug.

“These higher-level functions have an impact on SoC performance, power consumption, security and software quality and belong in the SoC interconnect because they represent SoC system-wide functions that need to go to many parts of the chip. In a multicore SoC, the interconnect is the only part of the chip that sees all of the data traffic and thus is the best place to consolidate these higher level service functions,” Janac explained.

“The NoC-type interconnect is ideal for implementing these services it implements predictable networking techniques with relatively modest number of interconnect wires and communications control logic. Individual IPs such as memory controllers and processors no longer see all of the data operations that occur in an SoC and so they not the best place to try to implement these types of SoC wide functions,” he added.

Particularly on the road to 28nm, interconnect issues are a key roadblock along with IP readiness. “What’s challenging about 28nm is obviously the complexity, the readiness, the availability of the IP; the readiness of that IP becomes a major Achilles heel of getting to 28nm,” Soheili said.
In order to reduce the risks, costs and time to market for its customers headed for 28nm, eSilicon is planning to take a platform-based approach in which it would pre-design SoCs.

“This works in particular vertical markets where a customer can look to this platform that could be a certain percentage of the design already completed. Then, the customer’s value-add is in selecting and providing the software stack, the applications, the drivers all the way up to the system-level, along with marketing and channels and getting the customers. This could be done in very large volume markets or could be in smaller volume/higher margin markets or anywhere in between. The smarts go in finding a superset and going after vertical markets so you do the job once, you get through the silicon validation process and the design process and then harden it as much as you can before the customer comes in. Now the NRE is down, the engineering time and the risk are down, the time to revenue is down.

To be sure, this is an interesting time in the industry as design complexity and vendor consolidation bring up new challenges to address.

By Ann Steffora Mutschler
As more features are packed into a single SoC there are simply more time-critical decisions to make. Instead of holding up one chip of a six-chip chipset, a delay or error on one chip can stop the whole parade.

That explains why one of the most vibrant parts of the business at big EDA companies these days is standard IP, and why most of the other commercial IP makers are issuing bullish forward-looking statements. IP is only a piece of it, too. With more and more companies looking to maximize their resources in building increasingly complex chips, whatever can be outsourced is a win—sometimes even the design itself.

“No matter what you are outsourcing, whether it is payroll, IT or semiconductor operations, the argument against it is always control,” said eSilicon chairman and CEO Jack Harding. “That’s a fallacy. There’s virtually no company in the world that does its own payroll, yet they control it fine. There is virtually no major corporation in the United States that manages its own IT yet they control it fine. In the case of our customers that do semiconductor operations outsourcing, it’s the existing operations team that typically says they really don’t want it to happen – it’s more self-preservation.”

SoC or PCB?
In terms of SoCs, that world is coming under a lot of pressure between issues of price point, time to market, quality, and schedule predictability, said Charlie Janac, chairman and CEO of Arteris. The impact is that increasingly, SoCs are going to start to look like PC boards because they will be assembled out of pre-made parts. “There are some parts that are not going to be like that and those parts are where the company makes the IP internally, which is reflecting its competitive advantage.”

The rest can be bought. “That makes a lot of sense because to build an internal IP is becoming very, very expensive. The verification is the main cost, and if those costs can be shared across the entire industry, then that allows the SoC maker to deliver that SoC at a more attractive price point. It’s not about technical capability, particularly with the large SoC makers, but it is about running a profitable business.”

Whether or not the IP is a differentiator for the semiconductor company can also determine where IP will be acquired from. When it comes specifically to IP models, Ran Avinun, marketing group director for the system design and verification segment at Cadence, believes that customers want them from the IP provider, not the EDA tool provider.

“They are looking at anything that is not their core competency as something they are willing to get from the EDA companies. This could include some of the memory models, or some of the I/O subsystem models,” he said. “Semiconductor companies don’t want to, and simply cannot, produce all of the IP models by themselves. They don’t have the bandwidth or resources to do it. As the real estate in each ASIC becomes enormous, they can’t do it by themselves. They have to rely on their ecosystem, and they prefer to focus on their core competency, which is IP that is unique for their business, or their IP stack – they way they connect to peripherals or software layers,” Avinun said. “We’ve seen that there is a shift in many companies. In the past, they used to focus on their IP creation, the process they are using, the fab. These days, a lot of those companies are losing those fabs or selling their fabs and they don’t want to develop all of the IP, so the name of the game becomes integration and how do you integrate all of these components with our combination of what you developed plus with what other companies are developing – integrated in an optimized way.”

You get what you pay for
In any situation, with any product, cost is a factor – which goes hand-in-hand with value.

“To go low cost and low skill doesn’t buy you a damn thing,” Harding said. “I would argue that it’s not the lowest cost you are seeking. It’s the highest value you’re seeking, which is output divided by cost.”

And interestingly, based on perception audits, eSilicon found that people will pay more for the company’s U.S.-based team – partly because they are very senior, but partly because they are based here. “We’ve seen over and over again with one competitive threat after another, none of the Asian-based competitors we have, they’ve all tried to land here and go upscale into our market and they can’t because their businesses are based around extremely low cost. The converse is true for us—we know how to make money with a relatively high cost basis by having higher quality engineers who get more yield per wafer and lower test times and smaller die sizes and the like – we are able now to go into Asia, transporting a methodology that works in a complex setting to a very low cost basis,” Harding noted.

Where IP, IP models or design services come from geographically is of concern to some, to many others it is not. However, a determining factor across the board in choosing an outsourcing partner is quality.

“I’ve seen a tremendous concern about quality and people want quality IP, no matter which part of the world it comes from,” Janac said.

Of course, quality IP means different things to different people. “From the SoC architect’s point of view, it means there are no architectural issues with a given IP. From the SoC assembly people point of view, it means that IP goes through the SoC integration and physical design process smoothly. From the director of the project point of view, it means there is no impact on schedule – to them bad quality means being late and having problems in the field. Basically, the more an IP has been verified in-real world designs, not just verified with tools, the more valuable it becomes and the more confidence people have in its quality,” he concluded.

By Ed Sperling
The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways.

It’s difficult to tell whether the trend is being driven more by the IP vendors or pulled through by chip developers looking to cut costs—or whether it builds upon the stamp of approval by foundries for certain pieces of IP. The net effect, however, is the creation of subsystems and partial platforms that are one step below reference platforms.

“A reference design suggests a complete solution,” said Eric Schorn, vice president of marketing for ARM’s processor division. “Customers don’t want us to go that far. But we are moving in a segment-oriented fashion. That’s the reason we bought a graphics processor company. We are making a processor along with a graphics socket for mobile phones and set-top boxes.”

The company isn’t alone in recognizing the opportunity for putting together more pieces of IP in very specific ways. Virage Logic’s recent acquisitions of ARC and NXP’s IP unit have positioned it to lead with integrated subsystems in markets such as high-performance audio and video.

“You have to have a reference platform these days,” said Yankin Tenurhan, vice president and general manager of Virage’s ARC business unit. “That’s not much different from the good old days of silicon, though, when you needed a complete solution and a full blown prototype. Philips, NXP, Texas Instruments and ST all have demonstrator chips for whatever you want on a cell phone. The same is happening in the IP world.”

Putting together the pieces
It’s not just the IP vendors that are putting together suites of IP. Two startups are focused on making IP easier to understand and integrate. Parallel Engines, which emerged from stealth mode this week, is focused on organizing IP by data mining pertinent information about everything from power requirements to the interfaces and interconnects.

“There are 12,000 pieces of IP out there, including 8,000 pieces of hard IP that are made by about 50 companies and about 4,000 pieces of soft IP,” said George Janac, CEO of Parallel Engines. “The hard IP is already in FPGAs from companies like Actel, Xilinx and Altera. You just need the soft IP to make it work.”

Somewhat conveniently, Janac’s brother, Charlie, is the CEO of Arteris, which makes network on chip technology that can be used to glue together these IP blocks.

“A company may have one or two pieces of IP that are the secret sauce and some software,” Charlie Janac said. “Why not drop those into an FPGA and connect up the other pieces of IP? Those two worlds are merging. We’re going to see much more custom logic on an FPGA.”

Another company involved in bringing IP together is Silicon IP, run by Kurt Wolf (formerly of TSMC), who said there’s a disconnect between chipmakers and IP vendors that still needs to be closed. “The chip guys distrust the IP industry,” Wolf said. “There’s more integration of IP, but there’s still a lack of confidence about how to choose, buy and license IP.”

Wolf’s company is focused more on bringing the two sides together with better information and connecting the pieces in an organized way.

The future
All of these efforts—by both large IP vendors and startups—are signs of just how important commercial IP has become in chip development. What began with embedded processors and standard memory designs has evolved into a huge market that actually gained momentum in the recent downturn.

Outsourcing is gaining ground at every level of business, even outside of the semiconductor world, but in the past most of the gains have been in areas where there was little value add. Outsourcing traditionally has been relegated to commodity services. What’s changing is that IP now includes areas that companies cannot do themselves in addition to those they don’t want to do, as well as the extremely tedious and time-consuming integration work that is necessary to create a final product.

When most analysts predicted a massive growth in IP at the beginning of the decade they were largely talking about small, relatively unsophisticated IP blocks pieces that can be put together by highly sophisticated companies. In the future, the differentiation may be less around the technology and more on getting very complex chips assembled and to market faster for specific market segments.

By Ed Sperling

Acquisitions are beginning to pick up in the system-level design world, signaling that even if the market isn’t fully recovered top executives believe it has at least bottomed and started its journey back from the depths of despair.

Virage Logic has stated its intention to acquire some of NXP’s intellectual property—and pick up 160 of its employees. Because NXP—formerly Philips Semiconductor—is a Dutch company, it requires the approval of a workers’council.

“These are the pieces we don’t have in our portfolio right now, like analog IP,  high-speed I/O and SoC infrastructure IP,” said Alex Shubat, Virage’s president and CEO. “We will be able to bundle this and integrate it with the rest of our IP to create re-usable components.”

Analog IP as a whole has been a tough market for companies for companies to crack because much of the IP in this market isn’t re-usable. NXP’s approach has been to develop more standardized analog IP, such as video decoding for digital TVs and set-top boxes, but it lacks some of the other pieces required to make a complete solution. Coupled with Virage’s previous acquisition of ARC, this potentially can make Virage a powerhouse in a number of high-volume consumer electronics areas.

As part of the complex deal, NXP also gets access to Virage’s IP portfolio for 44 months and will receive 2.5 million shares of Virage stock, priced today at just under $6 a share. It also agrees to pay Virage $60 million over four years.

The NXP deal was the second significant deal in the past few days. Mentor Graphics also signed a deal to acquire Valor Computerized Systems, an Israel-based maker of PCB productivity software, for $82 million. The deal is a recognition by Mentor that system-level design now reaches well beyond the chip and out onto the entire printed circuit board.

Mentor is not alone in this recognition. Companies like IBM have been talking about holistic design that spans well beyond the semiconductor for several years.

By Xiaodan Wang

The new message in China is integration, and that message is being spun and re-spun as companies jockey for position in a converged consumer world.

Case in point: When Frank Liang, Broadcom’s general manager for Greater China, released a 65nm chip that included Bluetooth, FM radio and GPS functionality two months ago, it hardly seemed like a major innovation. Texas Instruments and Cambridge Silicon Radio introduced a similar chip 10 months earlier. But as Liang put it, it’s not the time of releasing but integration quality that counts.  

Integration is Broadcom’s favorite topic these days, and with good reason. According to IDC’s latest statistics, combination chips will account for half of the market by next year. Companies with stronger abilities to integrate technologies and tackle interference issues when those functions are combined will win the market.

Within two years, all mainstream mobile phones will be embedded with GPS, triggering plenty of new opportunities for service providers, media and advertising. It’s no wonder that wireless chip vendors at the upper stream of the industry chain such as TI, CSR, Broadcom, Atheros and NXP are jockeying for position in this market.

The trend for “omnipotent” mobile phones also presents enormous opportunities and challenges for chip providers. Everyone sees the cake but not everyone can eat it. To make sure they’re in line, many companies are accelerating their acquisition plans so they can include more functions on chips more quickly. Despite clear signals that this was where the market was heading, Broadcom didn’t make a significant move in this direction until 2007 when it acquired Global Locate, then the world’s second largest GPS chip provider. Global Locate boasts leading GPS chip IP and powerful network-assisted GPS. Not surprisingly, that technology is in Broadcom’s new chip.

CSR, meanwhile, acquired Sirf Technology Holdings in February for the much the same reason. Interestingly, Sirf posted losses as an independent company, despite the growing popularity of GPS technology.

More integration ahead

Broadcom once claimed that it would release a new chip every two months. The product roadmap displayed by Broadcom when it introduced its new chip in February showed the new selling point will be WLAN connectivity. Questioned about this direction, Liang responded, “It’s good reasoning.”

There is widespread speculation in China that telecom operators will actively deploy “3G+WiFi.” 3G is used for the wireless communication in remote areas and between cities, while WiFi is the wireless Internet model of the highest price/performance within cities. Simultaneously supporting 3G, WiFi, Bluetooth and GPS is already a burgeoning trend. Broadcom, which is second only to Qualcomm as the 3G (WCDMA) solution provider, not to mention supplier for Nokia and Samsung, market watchers don’t expect to be kept waiting very long.

Scott McGregor, president and CEO of Broadcom, said his company is no longer a simple baseband chip provider, but a mobile phone chip provider. The difference is all about integration.

Xioadan Wang is chief editor of EEFocus, the Chinese affiliate of Low-Power Design and System-Level Design.

By Ed Sperling

The market for EDA and IP was down in Q4 of 2008. That should come as no surprise to anyone.

Nevertheless, there were a couple of bright spots even in that bleak picture. Statistics compiled by the EDA Consortium show IP sales were up 7.6 percent, which is a reflection of increased complexity in making SoCs at 65nm and 45nm, as well as better tools and standards for integrating that IP.

IP is about a $1 billion market, according to EDAC Chairman Wally Rhines. Within that sector, ARM is by far the largest single provider of IP and posted most of the gains, he said. Other beneficiaries include MIPS, Virage Logic, Denali, the IP divisions of Mentor Graphics and Synopsys, and a number of smaller players.

Other bright spots:

·      Parasitic extraction, up 10%

·      Process simulation, up 18%

·      Mixed Signal, up 39%

·      Services, up 25%, although much of that is due to eliminating contractors and taking the work in-house.

Most of the growth follows the trends in system-level design, with the greatest growth showing up in the areas of most pain. Since those numbers were recorded, however, there also are glimmers of life in other parts of the industry.

“What we’re seeing is a bounceback from desperation in the fourth quarter to a point now where there is a need for finished goods,” Rhines said. “The February [Semiconductor Industry Association] numbers were negative. In March, there were signs of a bounceback. But the semi industry and electronics tend to sort out early and prices readjust. EDA is one level removed from semiconductors, which makes it harder to read anything into the numbers.”

The total EDA industry was down 17.7%. But industry sources say at least part of that was skewed by Cadence’s change in the way it recognizes revenue, from up-front recognition to recording revenue as it is received. Taking Cadence out of the picture, the industry declined about 8%. That’s still severe, but at least it’s a single-digit decline.

Still, the tools industry is hardly on solid ground. More than half of semiconductor companies are rated “B” or worse. If a number of semiconductor companies go out of business, the overall effect on the EDA industry would be profound.

On a global basis, Europe’s decline was in the single digits while the rest of the world showed double-digit declines. Europe is very system-oriented, but some of its chip makers have stumbled badly in the downturn. 

Analog and mixed signal IP began closing the gap with digital core IP in design explorations in the first two months of this year, a clear sign that multicore systems on chip have emerged as the dominant semiconductor model and that the architecture requires both types of IP.

While it’s too early to tell this year what effect that will have on overall design activity—the economy is the real determining factor there—the convergence is pronounced. In January, when chip design exploration typically is at its lowest even in a good year, there were 894 digital IP core explorations vs. 427 for analog and mixed signal. Last month, the number for digital had grown to 2,729 while those for analog/mixed signal had increased to 2350.

Off-chip interface IP also is becoming important, although to a far lesser extent. Much of that work is still being done by hand, but many industry insiders believe that approach will change over the next couple of process nodes as design engineers are called upon to add more context to their designs, including software applications and application interfaces, as well as connections at the board level. The exploration with off-chip interfaces was 211 in February, up from 75 in January.

On chip bus IP activity, meanwhile, was 173 in January vs. 327 in February, and verification IP—still in emerging market mode—showed 9 investigations in January and 28 in February.

January (blue) vs. February design investigations.

–Ed Sperling

By Ann Steffora Mutschler

With the cost of failure at an astronomical high, the last thing chip designers want to worry about is the physical IP they will use to build their SoC.

In addition to less willingness on the customer’s behalf to take risks, complexity and economics have driven the need for more off-the-shelf IP and a corresponding rise in interest in verification IP. Compounding matters, IP investments are being stretched out for longer periods of time than in the past. That has made verification IP even more popular. Confidence in IP is critical, and this comes through a comprehensive IP validation discipline on the part of the IP provider.

However, the maturation of any method or tools means new focus on them, and so far the design industry has not even settled on what the optimal methodology should be for IP verification.

As a starting point, it helps to define types of verification. First, there is an intense level of unit-level verification where compliance to the relevant protocols is focused on and where the functionality of the block itself is detailed, said Mark Gogolewski, CTO at Denali Software. In addition, there is a separate step during which the subsystem or the system is constructed, with verification at this point being very different.

“For a time, there was a lot of IP verification when you had a bigger subsystem, but these days, the IP gets completely wrung out at the unit level and then when you construct the system, you are focused much more on connectivity and dataflow and how the system interacts,” he explained.

“If you are testing an IP block, there are two major dimensions of verification challenge. One is the protocols that are relevant to the IP block, and the other is the functionality, which is making sure the microarchitecture that was used to design the IP was correctly implemented,” Gogolewski said. “Correct” can have many meanings in terms of correct function and leading off performance objectives of that particular block of IP, he noted.

“Verification is all about observability and control. You need to make sure you are observing every aspect of the protocol, but then you have to give the customer control. One dimension for memories is giving easy control of the data space, and another is error injection and that’s another level of investment has to be made,” he added.

Carl Ruggiero president and CEO of Trilinear Technologies, agrees that common definitions of IP verification need to be established. “Depending on [a customer’s] point of view, everyone has a different idea of what verification ought to be, and that’s really making our job very challenging. Everybody says they want verification, but right now there is really no defined vocabulary for it. You cannot call it gates and flops like you can on the design side. People want to talk about coverage and percent of coverage, but at the same time coverage is very subjective. You can get 100% coverage with five coverage points. Therefore, it is hard to say what good coverage is because if you have 300 coverage points, you might be missing that 301^st, which is the critical one. How do we go about putting metrics on it? How do we define the vocabulary so we can all speak the same language? We struggle with this on a daily basis.”

In an effort to start out clearly with customers, Ruggiero says Trilinear talks about its verification in terms of functional coverage. “We talk about the actual things that we set out to do. We talk about garnering 100% functional coverage. While we don’t say that we’ve tested every ad nauseum combination of things, that for the things that our software drivers and reference drivers, the functions that are listed in the data sheet and in the specification, those are the ones we’ve tested to.”

IP Verification Challenges

Ken Brock, director of physical IP marketing at Virage Logic, said that when it comes to IP validation specifically for on-chip physical IP, challenges and solutions can include taking a standard cell library of more than 1,600 unique circuits and running them through one of several EDA vendors synthesis tools, running them again through the same or different EDA vendors’ physical synthesis/place and route tools and have them all work perfectly; taking a memory compiler with a dozen different knobs and switches and producing a fully functional memory IP over the number of words and bits with multiple aspect ratios, test options and power optimization configurations; mixing them together with other IP on an SoC; and doing all of these things over the full speed, voltage, temperature and process variability extremes of a specific leading edge silicon process.

He noted that the IP validation process requires a rigorous discipline, which includes unit validation, integration testing, platform validation and silicon validation.

Indeed, IP giant ARM is pursuing just that. Tom Lantzsch, VP of ARM’s Physical IP Division noted, “We spend a lot more time with the EDA partners integrating our IP under their flows much earlier and having them leverage it and test it themselves. It is a constant activity because when we do our verification, unlike an internal supplier, which probably has a limited EDA flow, and maybe even a limited customer set within their company, we have to be much more systematic and have to create a verification environment that supports us for multiple years.”

The Cost of Providing Verified IP

Whether making an investment into a new technology for entrepreneurial reasons or encouraged by major customers, the latter of which Denali did with its entry into the PCI Express arena, making it pay off is no small task both to the customer and for the IP provider.

As Gogolewski explained, with the company’s entry into PCI Express, “the world got a lot more complicated because it is extremely configurable, programmable and complicated. What we mean by configurable is that before you even put a design in silicon there are many choices. We have a couple hundred choices in our configuration spec just to correctly specify what that particular device even looks like at a specification level. It is programmable because it has all sorts of register settings that have to be set correctly and which can change the behavior of the device. And then it’s just complicated—our engineers had to become experts on two to three thousand pages of documentation. We had to make sure all the functionality was in there with the flexibility and programmability; we had to make sure all of those thousands of pages of spec became error checks and assertions. And then the way that [PCI Express] protocol works, your IP has to both handle correct functionality and incorrect functionality and respond properly. So there was a multitude of error injection that we had to make available to our customers as well as our own design team to make sure that they could inject all these levels of errors and validate whether or not their design caught it correctly.”

To deliver this level of backup data to customers for PCI Express, Denali estimates the extra engineering effort required is equal to approximately 70 to 75 man-years of effort over 7 years, with about 550,000 lines of new code created, not including the company’s Purespec library code.

The IP Verification Horizon

In the next phase of IP verification, one thing is for sure—there will be more of it provided by third parties.

“We’re at a tipping point from ‘make unless you have to buy’ to ‘buy unless you have to make,’ and the current economic climate is going to accelerate that. Basically the fundamental premise of third party IP is that if it is a ubiquitous problem and it is solved well, then the market is overall more efficient and better off when a third party solves it, rather than each customer solving it on its own,” Gogolewski said.

He also sees more IP verification moving toward third party IP vendors, even though there will always be customers that will create their own IP to maintain their place on the very bleeding edge of design. And he believes coverage-centric verification will be embraced. “It used to be something that leading-edge design teams would use, but now it is becoming ubiquitous,” he said.

By Ed Sperling

Santa Clara, Calif. — Feb. 3, 2009 — Build or buy has always been a question for system-level developers. There are time-to-market pressures to create and test a system, and there frequently are integration issues even with the best-qualified third-party intellectual property.

But what’s the actual tipping point where it makes sense to buy IP? Mark Gogolewski, chief technology officer at Denali, said it’s based on a factor of 10. If it costs 10 times more to build than to buy, then it makes sense to go outside.

Gogolewski noted that it generally costs IP vendors 5 times the initial investment to productize, sell, market and finance IP development. Profit-taking accounts for an additional factor of 3. Those numbers get multiplied, so it costs 15 times the investment to create a final product that can be licensed commercially.

The numbers for an IP vendor, however, can still be significantly lower than an internal development team within a semiconductor company. There is less overhead, more specialization, and sometimes there is an opportunity for re-use of code that already has been developed. On top of that, many companies simply don’t have the skilled engineers on staff to develop specialized IP, which has become dramatically more complex over the past decade.

Quality from third-party IP also has improved from the early part of the decade, when off-the-shelf IP blocks often caused more integration headaches than they were worth. They are now viewed as essential building blocks on complex chips, which is a testament that repeatedly throwing very smart people at a problem and learning from mistakes eventually pays off.

There also is enough critical mass in the market to be able to test IP designs in a variety of applications. “Our internal rule is that if there are not 40 designs a year, it’s not a viable enterprise,” Gogolewski said. “You even want more designs than that because not everyone will outsource this work at the same time.”

In addition, the companies selling the IP are likely to be around in five years. The majority of IP vendors at the beginning of the decade were small startups. Those startups have since been acquired or grown enough through their own sales and acquisitions to have gained staying power—even in the worst downturn in decades.

Virtually all the major EDA companies offer IP. Mentor Graphics, Synopsys and Cadence all sell IP blocks. And companies such as ARM, Virage Logic and Denali have grown large enough, and specialized enough, to have built expertise in the respective areas of focus.