What do social media and EDA have in common? Gabe Moretti takes a thoughtful and quite thorough look at the subject and its effect on the regular media. For anyone who relies on a free flow of information, this provides some really good insights.

There are digits and then there are lots of digits. For example, Intel has shipped (give or take a few billion) about 50 quadrillion transistors. That’s about 7 million transistors for every person on the planet. Mentor’s Colin Walls takes on the subject of just what these kinds of numbers with lots of zeroes actually mean. It’s a great look at just how much impact this industry really has, in case you’re wondering what’s really going on in the outside world.

Is free software really free? Mentor’s Michael Buehler-Garcia takes a look at just how effective trial programs are for end customers using free EDA trials—and comes up with some interesting answers. Hint: If it sounds too good to be true, it probably is.

Synopsys’ Godwin Maben is asking the right question: why is low-power-based optimization more challenging for tools. He even answers it from a high level. But we’d love to see a lot more about this subject. This is a minefield for chip architects and design engineers, and it’s no better on the verification side.

Also on the list of big challenges is the subject of stimulus coverage—making sure all expected and critical stimulus is included in verification. This is important stuff and it’s getting more complicated at every node—particularly with some parts of a design in multiple states—on, off, sort of on, sort of off, etc. Mentor’s Matthew Balance takes a look at coverage models and some new pitfalls.

Cadence’s Jason Andrews raises another interesting question: Is verification really the biggest time-consuming part of chip design? We’ve been living with that assumption for years, but it may be time to revisit this question with an eye toward embedded software.

In the SystemVerilog world, where coding is just short of being well-defined, Dave Rich suggests that the important thing is to come up with your own style—basically a lexicon for coding—and then stick to it. This is a very practical tip.

For anyone who’s addicted to those wacky videos from the Cadence team, spearheaded by Jack Erickson, this one addresses tapeout. These folks should box the collection and market them as holiday gifts for design engineers. This is part 22, by the way.

e/Specman enthusiasts, take note: There’s a Specman-Matlab update. You can read all about it here.

–Ed Sperling

Analog design has always been considered one of the last bastions of truly creative design, where industry rules don’t necessarily apply and where independent thinking is rewarded by fat profit margins.

That’s about to change., however. Standards are coming to the analog world, driven in large part by the convergence of analog and digital on a system on chip and the need to get SoCs out the door on time and within budget.

“This is a pain point in design,” said Shrenik Mehta, chairman of the standards group Accellera. “If you are getting productivity, people want to re-use that. With analog right now you can’t. You need to get new expertise every time.”

Accellera introduced its first Verilog analog standard during the Design Automation Conference last summer. The standard provided standards for assertions and modeling, but the feature set was limited, said Mehta. He noted that the next version will provide interoperability among the tools.

No less controversial among designers is the standard for power. Accellera’s Unified Power Format (UPF) is pitted directly against Si2’s Common Power Format. However, with the backing of most of the industry’s large players behind UPF—including Mentor Graphics, Synopsys, Magma and Sun Microsystems, it will be an uphill battle for Si2 and Cadence, which turned over CPF to Si2.

UPF has been submitted to IEEE. The first round of balloting generated sufficient votes for the standard to pass, sources say. The next step is for the regulatory community to submit its corrections. Finally, after that process, the standard can be published.

–Ed Sperling