By Pallab Chatterjee
The last couple of months have been busy for data transfer standards.

Consider the following moves:

1. Power Line Communication (PLC) has become a new standard by the IEEE and has two groups promoting it: HD-PLC and Home Plug Alliance.
2. Bluetooth also has made progress with the draft of the new Bluetooth Low Energy Technology as part of the July version 4 specification.
3. EtherCAT technology group recently announced its advanced control architecture for factory networking.

The Power Line Communications group has been adopted by the IEEE as the 1901 networking standard. The networking data is segmented into two groups – AV and GP. The HomePlug AV group has a targeted data rate of 200Mbps over the power line in a single facility. This data rate and power is designed to accommodate streaming media, remote and on-line gaming and whole house audio connectivity. This network is compatible with having devices on a traditional wired or WiFi network. Several products are currently on the market, such as those from Atheros and incorporated in the Monster Cable PowerNet and Netgear products.

Supplementing the AV version, there is a GP version, which stands for Green Phy. This specification is targeted at Smart-Grid applications and is for modules operating appliances, lighting, and other similar uses. The GP spec has significantly reduced power requirements (75% reduction), a significantly reduced cost and a data rate of 1Mbps (3.8Mbps Peak for the PHY). Further information on the Smart Grid application can be found in the joint working group document created by the Home Plug Alliance and the Zigbee Alliance.

Meanwhile, the Bluetooth group has finally released its Low Energy Technology specification. The specification already was adopted as a supplemental protocol by the Continua Health Alliance. The features of the new specification include ultra-low peak, average and idle mode power consumption; the ability to run for years on standard coin-cell batteries; low cost; multi-vendor interoperability and enhanced range.

The standard Bluetooth high-speed technology is for the transfer of video, music and photos between phones, cameras, camcorders, PCs and TVs and is for rechargeable battery operation. Bluetooth low-energy technology is for low-power sensor devices and accessing new Web services within the health care, fitness, security, home entertainment, automotive and automation industries. The entire space of the Bluetooth interface has matured to the point where there are more than eight new Bluetooth enabled products being qualified every working day and more than 19 million units shipping per week. So far there are nearly 3 billion Bluetooth devices in the marketplace,

In addressing the industrial space, such as for wafer fabrication, LCD display fabrication, and assembly line robotics, the EtherCAT specification was recently adopted and the Advanced Control Architecture has been released. The interface is a factory automation interface for both machine control and data communication using Ethernet and stand CAT5/CAT6 cables. The protocol conforms for the standard 802.3 specification using a header string following the Ethernet header (see Fig. 1)

The specification operates at over 100Mbps and supports cable lengths up 100 meters each with up to 65,535 devices in a single chain. The advantages of the EtherCAT protocol include being full duplex at the 100Mbps data rate, and having cycle times of 50 to 250µs versus traditional field-bus systems, which typically have 5-15ms update cycles. The high data rate also allows for the increase in data collection rates from 10 to 100Hz for standard SEMI field tools, up to 20KHz concurrent with the control data traffic. This allows for both feed forward and feedback control loop designs that can incorporate dynamic adjustments from in-process data collection.

Additional information on the specification and applications from the over 1300 member companies can be found here.

By Ellen Konieczny

As active devices and interconnect wires shrink and are placed closer together with the march of Moore’s Law, signal integrity is becoming a huge concern. If it is not maintained, a design’s future may be marred by lower yields, unreliable performance, and failure to work efficiently—if at all.

For low-power and radio-frequency (RF) designs, which are being produced at a steady climb, this challenge is even more daunting. Such designs involve numerous aspects that make it more difficult to ensure signal integrity. Due to their very nature, RF designs also face more severe consequences if signal-integrity rears its head in the form of problems like interference and noise.

Among the design aspects that threaten low-power designs, for example, are multiple power operating modes, multiple voltage supplies, voltage and frequency scaling, and voltage islands. As noted by Shekhar Kapoor, Synopsys’ senior product marketing manager for the Galaxy Signoff Solution, “The use of low-power techniques, such as power islands and on-off switching behavior, can exacerbate signal-integrity issues. The potential issues to worry about include dynamic voltage drop, power-grid electromigration, and electromagnetic-interference (EMI) noise. All these effects could worsen if care is not taken to manage the in-rush current in turning on power switches, for example.”

To overcome this challenge, Kapoor recommends a holistic approach to handling signal integrity that has in-design and signoff analysis working together. To mitigate the signal and power-grid integrity issues, place-and-route tools must provide various optimization and fixing techniques. Examples include wire-width adjustments, multiple via insertions, and buffering. In addition, the signoff parasitic extraction and timing/signal-integrity solutions must offer detailed debug and fixing to address any undetected problems before tapeout. At smaller nodes—especially below 40-nm process technologies—the parasitics have become context-specific (i.e., layout-dependent). To ensure silicon accuracy, the extraction tools must model the context-specific device parasitics as part of the extraction process. They can then account for the amplified effects of the MOS device parasitics at smaller nodes.

Beyond a winning approach, the key to successful low-power design is really a mindset. The techniques used to achieve low-power design introduce a high level of complexity at the levels of system design, functional verification, IC physical design, and IC testing. To achieve success, it is therefore essential that the designer keep the low-power aspect in mind beginning with the earliest stages of design. According to Michael Buehler-Garcia, director of marketing at Mentor Graphics’ Design to Silicon Division, “Engineers need ways to evaluate different architectural approaches to power reduction early in the design process, at the system level. They also need to verify functionality in detail, ensuring that transitions between power modes do not create logical errors and that state retention is handled correctly when parts of a chip are temporarily powered down.”

RF Design Poses Further Hazards
The RF aspect of a design adds a much more complex set of challenges, as it is essential that the integrity of the communication path be maintained. Among the chief concerns are electromagnetic (EM) degradation and EM-interference (EMI) noise. Dave Robertson, vice president of analog technology for Analog Devices, says his company sees the maintenance of signal integrity being comprised of two elements: Amplifying, processing, and transmitting the signal with minimal degradation due to distortion or device noise, and minimizing the effects of induced external signals from crosstalk, power-supply noise, or other external interference

The simplicity with which those two goals can be stated belies their complexity—especially considering the short time to market for RF products. This issue is compounded by the fact that signal integrity traditionally has been a concern in the digital-circuit rather than the RF domain. Thankfully, as signal-integrity issues began to rear their heads in high-speed communications designs, software developers have pruned signal-integrity analysis environments to address both device and circuit models. With today’s shrinking ICs interacting more with both active neighboring devices and interconnects, it is crucial that such interactions are modeled accurately.

During analog design, custom IC layout and simulation tools are used to accurately model the behavior of an RF or other analog circuit. The designer can therefore determine if signal integrity will be compromised by interactions within the cell itself. Yet Mentor’s Buehler-Garcia notes the designer also must avoid signal-integrity problems when the RF cell is placed within the context of a full mixed-signal IC, which may interact with other circuits including digital signals.

Once active and passive device models have explored all of the high-frequency effects, signal integrity may be ensured by using a comprehensive set of analysis engines that leverage that modeling capability. According to Ted Mido, senior staff engineer for Synopsys’ circuit simulation product line, designers must be sure to exercise both of these options. He notes that most designers rely on time-domain analysis for final behavioral verification. Therefore, the baseline would be to have high-performance, high-capacity transient and transient noise analyses.

In the early design phase, Mido notes that system or subsystem behaviors may be predicted by using small-signal frequency-domain analysis to predict system S-parameters, small-signal noise parameters, transfer functions, and so on at a particular operating point. In addition, a statistical eye-diagram simulation can predict deterministic channel noises like inter-symbol interference, duty cycle distortion, and periodic noise. Finally, large-signal steady state analysis may be used to predict nonlinear and modulation effects. Of course, these analysis engines must be able to accurately accommodate all of the high-frequency effects originally modeled.

Although electronic-design-automation (EDA) tools are clearly working to ensure signal integrity in RF designs, a lot may be gained in the hardware design as well. As ADI’s Robertson notes, “There are CAD tools for capturing and analyzing parasitic resistance and capacitances, but it can be difficult to come up with models of sufficient accuracy, and for large chips it is generally impractical to exhaustively capture and simulate these parasitics. Different circuit topologies and architectures may make the problem much better or much worse, so circuit innovation can often relieve what was perceived as a ‘hard physical constraint.’”

Beyond Moore’s Law, ADI recognizes a number of challenges spawned by the functional density involved in mixed-signal and RF integration. Although active power density is a fundamental challenge, some relief may be found in advanced packaging solutions. Similarly, powering down idle blocks offers advantages when dealing with inactive power density from leakage currents in very deep-submicron CMOS. It should be noted that this benefit does come at the cost of more sophisticated power management circuits and systems.

In terms of current density, the fine metal pitch and increasing functional densities can cause electromigration and IR drop problems in the on-chip interconnect. The process solution is to use copper and thick copper interconnect. Yet bump and flip-chip packaging can provide a 2D bonding approach so these currents do not need to be routed all the way across the chip. Such approaches also reduce the inductance of these connections.

The signal-integrity puzzle will only grow more complex as designs continue to shrink while consuming less power and incorporating more wireless capability. Going forward, for example, it is critical for designers to realize that signal integrity will need to be considered between chips as well as on chips. Mido states, “The massive integration of cores on vertically stacked chips (3D ICs) that don’t necessarily feature the latest transistor technology node is becoming common. Therefore, high-speed communication between cores/chips is becoming important. With the increasing operational frequencies of these digital communication bus/links, bit-error-rate (BER) prediction is also becoming important (See Figure 1).”

Figure 1: For accurate bit-error rate predictions in high-speed digital communications, it is critical to account for aspects like high-frequency loss mechanisms, millions of possible bit patterns, special techniques for equalizing digital signal shape both in transmitter and receiver side, and multiple noise mechanisms.

By Ed Sperling

The crossover for system on insulator (SOI) versus bulk CMOS was supposed to happen at the 22nm, but that was before software developers ran into problems programming multicore chips.

For years, SOI was considered the high-performance cousin of CMOS—more expensive, more difficult to manufacture and unnecessary for most applications. It is the heart of the Cell processor, for example, which drives Sony’s Playstation 3, the latest versions of digital televisions and some network appliances that need the benefits of always-on active power.

But with the persistent problems of writing general-purpose applications that can scale with multicore processors, SOI is quietly gaining more mainstream appeal. By running either faster or cooler—or both—it can provide the performance gains that multicore chips would provide if the software could take advantage of all the cores.

“SOI does offer a way out,” says Horacio Mendez, executive director of the SOI Consortium. “The big issue is the scalability of bulk CMOS, and there are significant challenges there. When you shrink the transistors, they’re not stable. And with stability comes a power consumption problem.”

The instability is caused in large part by voltage threshold variations. As companies continue down the Moore’s Law road map, short-channel effects (see Fig. 1 below), an increase in parasitic leakage as a result of scaling gate-length dimension and gate oxide leakage all contribute to power dissipation. SOI chips use up to 40% less power due to lower parasitic capacitance, and because they can use higher current they operate at lower voltages.

In practical terms, that means SOI chips can at least keep the number of cores constant and still add performance at each process node. And because they run cooler, they also can use less expensive packages—something that affects when they become economically feasible to use in lower-performance applications.

Short Channel Effects — Source: IBM

Given the advantages, it should come as no surprise that IBM has opened its SOI fab to commercial business at 45nm. Mark Ireland, IBM’s vice president of semiconductor platforms, said SOI is expected to be adopted by the Common Platform group—IBM, Samsung and Chartered Semiconductor—at 32nm.

“What we’re doing now is creating an industry ecosystem,” Ireland said. “From a design standpoint, this is more about education of engineers. At IBM we moved our entire ASIC business to SOI at 45nm. A lot of the hesitation is just about the unknown. But it’s the same design tools and ARM physical IP.”

Opening SOI technology to a broader market also should drop the cost even further, bringing it much closer to parity even at 45nm. But the biggest advantage is still on the software side. While many applications can be threaded to deal with between two and eight cores, far fewer will gain from the addition of more cores. On top of that, very few applications are scalable so they can be written once and recompiled for as many cores as become available.

“Customers already are coming to us looking for higher single-threaded performance,” Ireland said. “Clearly, that legacy market is not going away. Applications will not change overnight. And you do get a performance gain every time you move to the next node, so at 32nm vs. 45nm, there is a performance gain.”

Intel developed a similar technology called TerraHertz in 2000, but so far has done nothing with it commercially. It is one of several possibilities that Intel can tap into at future process nodes, along with its Tri-gate technology. Likewise, IBM has been developing its own tool bag of options, which includes everything from FinFETS to AirGap insulation between structures on a chip.

All of these technologies can be manufactured using existing equipment, and likely will have a significant role in future system development

By John Blyler

Chips continue to grow in complexity. This is nothing new. But even at the existing process nodes of 180nm and 130nm, complexity is increasing as designers attempt to squeeze in more feature sets while shrinking the power budget and chip size. This growing complexity, married with the shift to time sensitive consumer product markets has led to an increase in the use of prototypes to verify these chips prior to production.

But what do users really seek in prototyping tools? The report that follows contains the summary and analysis of a survey conducted with more than 270 qualified respondents in the ASIC and related markets. The results track well with similar surveys in this space, but the details present some surprising implications.

Application Markets

Most responders listed the communication market as their primary product area, followed closely by the Consumer, Computer and Other markets (see Figure 1). Most prevalent “Other” markets were Industrial, followed Mil/Aero, Automotive and Medical.

Figure 1

In the category of communications, most respondents listed wireless handsets and wireless and wired networking as their chief application areas, followed closely by wireless base station design, telephony/VOIP and wireless Metro Area Networks (MANs). A small percent listed research, remote controllers, CDMA networks, fixed networks, telemetry and military as other areas of focus within communication category.

In the consumer market most respondents list multimedia designs – involving both video and audio subsystem – as their primary area for developing ASIC prototypes. Multimedia design concerns will be reflected proportionately in other parts of this survey, i.e., processor types, interfaces, etc. Interestingly, several designers listed games as their chief concern. That’s a trend we will watch in future surveys.

Computer design issues were most closely tied to peripherals such as storage, printers and the like. PC and workstation systems came next, with others including prototyping systems, servers, data acquisition modules, and instrumentation and software/firmware design issues.

Job Function

Most of the respondents identified themselves as ASIC or ASSP designers, followed by engineering management, corporate management, verification engineers, system architects and software designers. A small percent of users listed their function as applications engineers, business development, academia and sales/marketing.

Figure 2

ASIC/ASSP/SOC Design Details

When asked to describe their current ASIC/ASSP/SoC design, more than half of the respondents indicated a design size of less than 5M gates, with that majority below 2M gates.

In terms of memory, most designers focus on SRAM memory, suggesting the strength of on-chip memory prototyping. Still, DDR and Flash memory account for about 22% each of memory usages.

Embedded processors usage is led by the MIPS processor, which matches up with the respondents’ applications markets. ARM, Tensilica and Intel comprised roughly 16% each of the remaining usage. Other processors used for ASIC prototyping ran the gamut from microcontrollers like the 8051, Microchip’s PIC and Xilinc’s MicroBlaze to proprietary cores. A large number of DSP cores also were cited, including Ceva Teak Lite, TI and in-house multimedia DSPs.

To the question concerning the types of external interfaces used in ASIC prototyping projects, the top three busses were PCI, USB and Ethernet. SPI, SATA, XAUI and HDMI finish up the lower quadrant. Though not listed in the survey, questions have arisen about the use of the PC-104 bus. Several experts believe PCI Express represents the path forward for PC-104. This projected growth will be the subject of a future survey.

The majority of users listed Serial RapidIO (sRIO) as the main external bus of choice under the “other interface” category. This is no surprise, since the sRIO interface is commonly used to connect multiprocessor designs, especially for DSPs. This tracks well with the use of DSPs highlight in the “Processor” usage category cited earlier. Other interfaces include I2C – a low-speed serial bus used to attached peripherals to a motherboard, embedded system, or cellphone; DVI, RS-232, parallel bus, CAN – automotive bus, DigRF – digital serial interface for 3G air standards; and even UART.

Re-spins

A little over half of the respondents indicated their previous design project required no re-spin. Of those acknowledging re-spins were necessary, 50 percent stated that only one re-spin was needed. About half as many reported by two re-spins were required and slightly less than 10 percent admitted to three re-spins.

The main reason for chip re-spins was the presence of logical and functional errors. This result tracks well with other recent studies that indicate more than 60 percent of re-spun ASICs fail due to logical/functional errors, not because of timing or power issues. This means that functional verification is now the most critical phase of the chip development cycle.

Figure 3

Verification Environments

When asked what type of verification was used for a current project and planned for future work, the largest groups of respondents selected Mentor’s ModelSim/Questa. This was followed by Cadence NC Simulator and Synopsys VCS.

Figure 4

Other software simulation environments consisted of tools from IBM, Altera’s QuartusII and Xilinx’s ISE, Synplicity’s Synplify, Dolphin’s SMASH and Catena’s Analog and Mixed Signal (AMS) Simulators, Aldec’s Active-HDL Simulator and homegrown systems.

In terms of emulators, most users listed Cadence systems, followed by Mentor and Eve. An interesting side note is that only Eve emulators saw a planned increase for future projects. Formal verification favorite was Formality, followed distantly by OneSpin, Real Intent and Certess. System Verilog lead the way in Assertion-based tools, followed by OVL and PSL.

Here’s where the results get interesting. When asked what type of virtual prototyping environments were currently being used, ARM was the favorite – but by a decreasing margin for future projects. Synopsys’s Virtio was the second most popular choice, showing projected growth along with CoWare, VaST and Virtutech. One should exercise caution when interpreting these results, since the slower pace in usage of ARM tools may simply reflect the growth of virtual prototypes in non-telecom related industries.

Figure 5

Looking at the other end of the prototyping spectrum revealed that Synplicity was used more often for ASIC prototyping with FGPA-based systems – at least in the market areas highlighted by this study. ProDesign followed second, then came Dini and Gidel. It must be noted, however, that 36 percent of respondents still used custom-built FPGA-based prototyping, though the percentage was on the decline for future projects. This marked decrease in custom-built systems may attest to the growing complexity of ASIC designs and hence the corresponding complexity of FPGA prototypes.

Conclusions

This survey points to the changing dynamics in ASIC prototyping tools and methodologies. Prototyping of specific blocks on an ASIC core now seems mandatory, especially since ASICs continue to increase in design complexity. This complexity is manifested by an increase in logical and functional errors in the chips, which has resulted in a need for more complete verification tools and methodologies.

But prototyping itself has taken on a new dimension with the advent of virtual prototypes – used more often by software designers – and FPGA-based prototypes used by chip hardware engineers.

These trends have been confirmed by other studies. For example, Aberdeen’s “Best in Class” study cites verification as one of the most prevalent concerns in chip companies. Chip Design Trends reports, which tracks ASIC pre-silicon architectural trends, confirms the growing complexity of ASIC chips – at all levels of design metrics. Contrasting this complexity with the continued decrease in ASIC starts suggest that ASICs may be getting larger in size though less numerous in unique projects. All of these trends support the growth of prototyping as a key element in future chip designs.

On the business side of the equation, one should note the shift away from corporate electronic expenditures to the rapid increase in consumer’s consumption of electronic products. The consumer world is outpacing the corporate world in the purchase of electronic goods, but there is a caveat: Consumer electronics have a shorter time to market, high product volume but lower cost per unit that corporate electronics. What does this mean to chip designer? It means that they must find a way to reduce ASIC re-spins, such as with ASIC prototyping.

Santa Clara, Calif.–ARM executives unfurled a multi-market road map at the ARM Developer’s Conference this week for the company’s processor cores, intellectual property and software across a wide range of markets.

On the Web 2.0 front, the company is shipping its Cortex-A9 processor to leading customers, based upon the ARMv7 architecture. The company continues to ship the Cortex-A8 as its volume processor.

Simon Segars, executive vice president and general manager of ARM’s Physical IP Division, said the A9 will be able to handle greater complexity in mobile Internet devices, including Adobe Flash and Microsoft Silverlight Web browser. Segars said it logical to assume there also will be an ARMv8 at some point, but did not give details.

Segars noted there is a difference between synthesized performance and optimized performance. The synthesized version of the A8 runs at 800MHz, while the optimized performance runs at 1.1GHz. “Developing application-optimized physical IP will result in better performance and lower power,” he said.

ARM contends the A8 will outperform rival Intel’s Atom processor at the same frequency, while running Atom at twice the clock speed only results in a 25 percent boost in power and uses significantly more power. Moreover, the Atom processor will burn up without a heat sink, executives said.

ARM also is pushing down into the graphics processor world with its Mali graphics processor units, which currently are being licensed by companies such as Broadcom, Cisco, NXP and STMicroelectronics. ARM has developed a complete stack including the processor, drivers, middleware and developer tools, said Michael Dimelow, director of marketing for ARM’s Media Processor Division, and will continue pushing down the size and power requirements of the chip in future generations. 

Dimelow said there has been a lot of interest among companies for using the GPU as a general processor because of its energy efficiency.  

Finally, the company is heavily leveraging the AMBA architecture ecosystem in SoC design, building in adaptive verification IP and Coresight, ARM’s on-chip debug utility. Keith Clarke, VP and general manager of ARM’s Fabric IP Processor Division, said the company’s adaptive verification IP will be able to inject realistic traffic patterns into chip design and allow developers to make tradeoffs involving latency and power.

–Ed Sperling

By Ed Sperling

Santa Clara, Calif. –There are three new buzzwords you’ll be hearing a lot about in coming months: ecosystem, reusability and platforms.

We’ve all heard them many times before, of course, but we’re about to be barraged with them. As the price of developing SoCs continues a race for the stratosphere, the table stakes for getting into the business, doing something wrong that could put you out of business, or doing everything right but miscalculating the payback are potentially career-limiting moves.

ARM joined hands with the Common Platform last week, and today at the opening of the ARM Developers Conference the company—with the help of Common Platform member Chartered Semiconductor–began detailing just how ugly the convergence of technology and business has become.

ARM sees an upside in all of this, of course. Its partner base is growing, which means an increase in IP licensing and an emphasis on reusable, integrated IP blocks. Complexity feeds into the IP licensing model, particularly when the IP is integrated with other IP blocks and verified to work as a package.

Warren East, ARM’s chairman, said the macro market changes are opening vast new opportunities for those who can take advantage of them. The difficulty is mapping the changes to the right features, the right form factors and the right market segments, some of which are still ill-defined.

 “In Web 2.0, there is no typical consumer yet,” East said. “There in lies lots of opportunity and excitement.”

ARM’s focus on energy efficiency, which years ago was considered a plus, is now considered “the killer feature,” East said. Adding the ability to assemble devices relatively quickly using integrated and tested off-the-shelf parts—which includes IP—to help shield system developers from some of the complexity only makes the package more attractive.

But none of this totally gets around the growing complexity and rising risk, which accounts for the interdependency that has sprung up in the electronics industry. Kevin Meyer, VP of industry marketing and platform alliances at Chartered, said it now requires 5 million units be shipped to recover design costs—and that’s providing you’ve done everything right. The cost of a missed market window has risen from 8 percent two decades ago to 24 percent, which is enough to kill many companies.

“The smart companies will figure it out and offset up-front fixed costs by taking advantage of recurring costs,” Meyer said. “That means greater design re-use.”

He said companies also have started to do business differently. While foundries are creating new processes every two years, keeping pace with the Moore’s Law road map, many of their customers are skipping process nodes. “The 40nm to 45nm process node is not one that everyone will take advantage of.”

He said some companies are moving directly from 65nm to 32nm, and will likely ride that process a half node to 28nm to minimize costs and risk. “If you make an incorrect choice, it’s difficult to get back,” he said. 

It used to be fun to be a chip architect. You could wake up in the morning, grab a cup of strong black coffee and run through a few power and performance tradeoff calculations before deciding on the high-level architecture. That would set the engineering direction for months, if not years. On a good day, after introducing a steady infusion of caffeine into your bloodstream, you felt like the all-powerful creator of an electronic universe.

That dream job began showing its first signs of vulnerability at the 130nm process node, especially as the SoC began emerging as the leading design platform. The job description began weakening further at 90nm, and by 65nm it has transcended into something far less satisfactory—and the trend only gets worse from here. More people are entering into the conceptual design phase of building a chip with each rev of Moore’s Law. Suddenly, there are people talking about power budgets and yield and verification engineers trying to build in ways to solve their problems earlier. Managers are screaming for first-time silicon success. And software engineers—who, incidentally, no one has ever understood very well—are now sitting at the table at initial conception, slurping Diet Coke or Mountain Dew, and speaking a language no hardware engineer can understand.

Welcome to the brave new world of hardware engineering. It’s called system-level design, and it’s become so complex that just to get the job done now requires steady and concurrent input of multiple disciplines. Engineers are struggling to keep up with multiple power domains, multiple cores that exist only because classical scaling for performance died at 90nm, and timing issues that get complicated by shared busses, shared memory, and shared resources within engineering groups.

“The technologies for low-power design are well understood for silicon,” says Nikhil Jayaram, director of CPP engineering at Cisco Systems. “The challenge is in the complexity of those technologies. You have to ask yourself, can you pull it off in a reasonable design cycle?”

The answer is always yes, of course, but the cost is not always easy to swallow. Complexity is measured in terms of additional resources. Jayaram said that number is about 20% to 50% extra per design, depending upon the complexity of the design itself. Why? “You have to buy more tools and use more people.”

There are plenty of tools, too. In order to address this complexity, vendors have been introducing a steady stream of new tools that raise abstraction levels or combine multiple tasks. Those go hand in hand with new standards such as TLM 2.0. But the learning curve on these new tools and standards is quite steep, demanding time from engineers who are hard pressed already. Even the IP that is supposed to simplify chip design and development is so complicated that it often needs additional IP just to be able to ensure it can be debugged or manufactured properly.

One verification engineer at a very large, well-known chip maker (he asked for anonymity because he didn’t get approval from his bosses before talking to System-Level Design), said overload is becoming a serious issue among engineers.

“Designers are required to become experts in three completely different languages that the industry has standardized on as mainstream,” says the engineer. “The languages are SVA (System Verilog Assertion) for the assertion-based methodology, SV (System Verilog) for the testbench methodology, and C/C++ for system-level hardware/software verification. A verification engineer cannot get by without becoming an expert in these three languages. The way to deal with this is through the right schooling so that engineers come out with the expertise in all three. Standards have definitely helped with this. The frustration of course will be for the engineers that are on the job for many years and now need to become skillful in three different areas. As things are today, I am finding it very difficult to justify all three methodologies to my customers and they are missing out on quality because of this.”

That’s only part of the problem in verification. While five years ago engineers were complaining about getting too little data back from foundries such as TSMC, UMC and Chartered Semiconductor, they’re now complaining about being flooded with data. There are volumes of it—literally—and there’s no way other than just plain luck to pinpoint a bug without running tests on broad areas of that data. TLM 2.0 purportedly will help (see related story), but it also has a fairly high learning curve to be able to use TLM 2.0 tools. How do you construct a test model, for example, using object-oriented code?

There’s a reason why verification is still 70 percent of the NRE time budget and cost for developing new chips. Despite throwing lots of money, resources, and the best minds in the world at the problem, that number hasn’t budged much.

IP, Verification IP, and insurance IP

Nowhere is this overload more evident than in the IP world. Why write a piece of code for a standard interface or a piece of memory if someone with experts on the bleeding edge of technology has already done it? That way of thinking is growing. IP is a big market, and the problems of five years ago when companies bought advanced IP only to face challenges—and potentially huge expense—getting it to work are enormous.

Buying IP isn’t like buying a pair of shoes. It’s more like setting up a deep partnership that lasts for the life of a chip’s many iterations. And getting those partnerships to work properly can be a time-consuming process. That explains why many of the smaller IP companies have evaporated even though a decade ago pundits said the barrier to entry for IP startups would create a vast array of parts that could be simply plugged into a system on chip. Things didn’t work out so well in the real world.

“When you walk in to a partnership you need to get a complete match on the methodologies and tool sets,” said an engineer, who spoke on condition that he not be named. “This is soooo difficult. Very high level managers are finding themselves bleeding trying to make this work. Your tool set may be delivered by multiple vendors in addition to internal tools. Internal tools cause even more problems that are related to support, IP, etc.”

The engineer noted that standards will help solve this—everything from standard formats, standard languages and standard methodologies, which is what the new verification IP committee is trying to tackle.

Business, As Usual?

Beyond all of this, there is the incursion of the business groups. It was bad enough to build chips that worked. Now they have to be built on time, within a financial budget, and they have to include more complex technology and tricks than ever before.

One solution for keeping chips in budget is using the lowest-cost tools. The problem with that approach, say engineers, is that not all tools share exactly the same functionality. So what happens when you run simulators such as VCS (Verilog Compiler Simulator, formerly from Chronologic but now owned by Synopsys), IUS (Cadence Incisive Unified Simulator), and (Mentor Graphics’) ModelSim? The answers to that question vary by project, and frequently for the same project.

But no matter how bad it looks, at each new process node there will be more cooks in the kitchen. You can fight it, ignore it, embrace it, but know that only the last choice is the right answer.

–Ed Sperling