By Ed Sperling
System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), and Charlie Cheng, CEO of Kilopass.

SLD: Where will biggest challenges be at future nodes?
Schirrmeister: For us it’s the combination of hardware and software that gets interesting. You may have a network operator determines he wants coverage for the NFL on Sundays. That trickles through the design chain of what the network needs in terms of bandwidth and what the devices need to be able to process. As an EDA vendor, there are huge challenges for us because what used to be a small IP model has grown into a subsystem. People are building chips as an assembly of subsystems. The integration and the verification become a big issue at both the subsystem and the system level. There are lots of ways to grow.
Janac: I see things getting fragmented, concentrated and disintermediated. Nobody can afford to do everything themselves, so you wind up focusing on your core competencies. The people in those core competencies become more concentrated. The chip world also gets more concentrated because there won’t be many people who can afford to build a platform at 20nm. But the components for that platform are going to be disaggregated. Companies will have to outsource a big chunk of those designs and a lot of the tools they used to do themselves. So the little chip companies die. They will have a really tough time, particularly at the leading edge. The EDA industry has a lot of problems because it will be sharing the volume, which is going to explode, and it will be hurt by the fact that the number of projects will decline. You wind up with someone owning 80% of the processor market, someone owning 80% of the interconnects, and someone owning 80% of the memory. The DSPs get concentrated. Tools get concentrated, where someone owns place and route and someone owns simulation and ESL.

SLD: But you have to redefine what’s a chip company, don’t you? Are Open-Silicon and eSilicon chip companies?
Janac: Yes. And if I’m a small company I have to go to Open-Silicon or eSilicon because I can’t afford a staff of engineers to get a chip out.

SLD: But traditionally they were not considered chip companies.
Zahiri: They’re an aggregator of chip demand. Maybe eSilicon and Open-Silicon become the equivalent of midsize to large chip companies, aggregating the demand of the little companies that have to go to that model to be competitive and survive in the marketplace.
Sherwani: Along these lines, one of the challenges I see is that we’ve set up the market to expect 50% gross margins and 30% net margins. If your IP is coming from ARM and Kilopass and other companies, then how do you achieve those kinds of margins? You can’t. And if you can’t achieve those kinds of margins then you also have a business problem, and your business structure has to change. If you do everything in-house you’re not paying all the up-front fees to IP vendors. So first there is a problem of size. And second, even if you have the size there is a profitability problem with respect to the expectation that has been fed to Wall Street.
Janac: If your gross margin goes down, your operating margin has to improve, which means you can’t do enough R&D. So instead of using 25% of revenue for R&D you can only afford to do 10%. The PC guys are reasonably profitable at 25% margins because they don’t do any R&D. Intel does it. That’s why people are starting to outsource the IP. They can’t afford to do the R&D as the gross margin drops.
Sherwani: That’s one piece. But if you look at what’s going on in chip companies, the R&D budget goes down for IP, but it doesn’t go away. It goes into software. The number of software engineers is increasing. The market expectation still remains for hardware gross margins, but your expenses are going up.
Schirrmeister: You can’t just look at the chip in isolation. You have to look at it holistically. One large OEM says it’s losing money on every TV it sells. They have to get it back other ways. You can’t look at these things in isolation.
Janac: It gets back to the business model. If you don’t have a good business model and you just keep squeezing the margins then you’ll go out of business. But there are people who have innovative business models, like Amazon and Apple, that can afford to sell the hardware at cost.
Cheng: Worrying about margins and R&D is like worrying about the 120 companies that went out of business selling cars. As businesses mature, the technology content gets very high and it costs a lot. It’s not that companies don’t have good gross margins. There are a lot of companies with margins of 60% or more. But the ones that assemble IP and add 10% original content are not going to be very successful if they don’t differentiate, and they won’t be good customers long-term for the EDA vendors because 70% of those chips are memory and another 20% are IP that’s licensed from the outside. So they may only be doing 10% of the chip. This is why EDA revenue has been flat. If you look at the surviving car companies, they’ve been very profitable over time because there’s a high barrier to entry and it’s a fixed market.

SLD: But more pieces have to go together into something that’s coherent, and that’s more difficult than ever before, right?
Janac: I just met with a customer that spent $500 million on their platform and they have 180 IPs. They still make most of those IPs themselves, but integration is the issue.
Cheng: Integration isn’t any worse today than in the past.
Janac: It’s absolutely worse. And the reason is that you have an incredible amount of computing in smartphones, and that’s even trivial compared to what it’s going to be. You can’t afford to keep that device turned on except at times when you need it. One of the complexities of 20nm and 14nm is that you need a portion of the chip to do its job and then you shut it down. From a power perspective, you can’t afford to keep it on. And you don’t want it to be big, so you can’t afford a huge battery. It is very complex. You have frequency domains, power domains, power regions. You have as many as seven modems—WiFi, Bluetooth, CDMA, GSM and LTE.
Schirrmeister: What customers are telling us is that getting to an acceptable confidence level in verification is a very difficult thing, driven by the integration of all the components they have. Given that you’re taping out a chip and you can’t make a change tomorrow—that’s the pivotal point where you have to have enough confidence. The integration challenges are huge.

SLD: The promise of stacked die is that if you have a base platform you can start shifting into vertical markets quickly because a lot of the integration is already done, right?
Janac: Yes. The application processors that are being made for phones can be shifted into dashboard control, automotive infotainment and home gateways. What’s also going to happen is that the low end of the SoC market is going to disappear because the costs are too high. You’ll get 3D silicon, where people are selling dies with specific functionality on trailing-edge processes. You’ll wind up with FPGA SoCs.
Sherwani: But that’s a good thing. You could build viable chip companies that are on trailing processes with known good die that we can put into 3D stacks. You don’t have to push them all the way to 22nm. There’s no need for that. A lot of people will stay on 65nm, and that will justify keeping those fabs alive for a long time. It actually helps with the overall investment we need to put into 14nm.

SLD: Are the specialty fabs that are coming online capable of doing all this integration work?
Sherwani: They don’t need to. The interposer technology we have today doesn’t have to be much better. At 22nm you’ll see many people bringing 3D chips buying known good die from a bunch of people and putting these MCM-style 3D chips together. That will lead to many companies, which we consider sub-optimal today, becoming viable. And I don’t think these small SoC companies will disappear. They will start doing specialty silicon.
Janac: They will be the known-good-die companies.
Sherwani: Yes. They will be working with GlobalFoundries and TSMC at 65nm. They don’t have to run at 1.2GHz. They can run at 300MHz and be just fine. And you don’t have this area constraint. So area constraints and power constraints can be reduced. Today you have one chip and something that is 1.2GHz can run fine at 100MHz. Not everything is being pushed to that level.
Janac: And then you’re moving from 2D integration to 3D integration. That opens up a whole bunch of opportunities that are untapped today.
Sherwani: Just because of 3D, there are huge opportunities. I also think that IC design and computing will completely change if we can change the memory. The idea in the past was to dumb down the memory because you could pull the gross margin into the microprocessor. After 25 years of dumbing down the memory we do have standard interfaces, but memory isn’t doing much. When you look at 3D memory, it has 20X the performance of DDR3. It is one-sixth the power and one-tenth the space of DDR memory. A new era of intelligent memory will do a lot more than just keeping the bits. It will become very close to the processor, which changes the processor design. And many new applications are possible. If the architecture changes and memory and processors are very close together, many new things can happen. That is what you will see in the next five to seven years. You will be able to put terabit memories on top of processors in the same 3D package.

By Ed Sperling
Synopsys’ Eric Huang predicts that USB will save the planet. Probably not, but the first video is certainly worth watching. It doesn’t look like they washed the spoon after the dog licked it. Yuck.

Mentor’s Robin Bornoff looks at thermal bottlenecks—a term that design engineers should get used to—inside of thermal interface materials. What’s particularly noteworthy is how simply these problems can be fixed.

Cadence’s Richard Goering digs into the best practices for selecting commercially available verification IP. For the past half-dozen years vendors have been giving this stuff away with their IP. But it is becoming so complex—and time-consuming to develop—that they’re now starting to make a business of it.

DeepChip’s John Cooley says Magma users are asking Synopsys to keep Talus alive once the acquisition goes through. What’s particularly interesting is that people are using their real names and company affiliations in this appeal, which gives you some idea of where these tools have made inroads.

Synopsys’ Karen Bartleson issues a call for experts who can serve on standards committees. Maybe they should start naming these standards after the people who work on them, like they do in government.

Speaking of names, Mentor’s Colin Walls looks at the introduction of IPv6, which has long been viewed as the solution to Internet address limitations. Also interesting is what happened to some of the previous IP versions, which seem to have evaporated. So what’s in a name? More—lots more.

Cadence’s Team Verify looks at the formal and ABV focus of the upcoming DVCon show at the end of this month. Stay tuned for more on this conference.

Mentor’s Mike Jensen delivers part three of his epic on analog modeling, this installment shedding light—literally—on the model definition process.

Synopsys’ Helen Thibieroz (accent marks missing) unfurls 10 tips for improving performance of HSPICE simulation. Print this one out and hang it on your computer.

And in case you missed the most recent issue of Low-Power Engineering, here are some noteworthy blogs:

–Synopsys’ Cary Chin looks at solar smartphones, which will allow you to work indefinitely—as long as there’s enough light.

–Mentor’s Barry Pangrle details the history of power formats and why we are where we are.

–Cadence’s Luke Lang digs into virtual domains and why they’re so important for complex power architectures.

–Tensilica’s Chris Rowen applies Steve Jobs’ philosophy to advanced computational imaging and video analysis.

–And Apache Design’s Margaret Schmitt advocates effective thermal and power management—and a good plan for implementing it—to deal with some interesting advancements in electronics.

By Ed Sperling
Cadence’s Frank Schirrmeister compares the state of system-level design to predictions made 10 years ago. A key finding: IP re-use solved one of the big system-level problems identified at the end of the last century.

Synopsys’ Karen Bartleson is hosting a trivia game throughout 2012. Prizes are $40 Amazon gift cards. Given Amazon’s just-announced earnings, this may qualify as a corporate charity write-off for Synopsys.

Mentor’s Robin Bornoff looks at the reasons why thermal interface materials go bad and what to look out for to prevent bottlenecks or, worse, complete meltdowns.

DeepChip’s John Cooley is soliciting comments for the FTC on the proposed Synopsys acquisition of Magma in light of previous concerns that were raised when Synopsys bought Avanti in 2002. But are those claims still relevant? Mike Demler offers up a completely different viewpoint, also in DeepChip. He says that Magma shareholders should be thrilled by the offer.

Cadence’s Richard Goering focuses on a white paper that shows verification performance is more than just raw simulation speed. There are some notable pointers to how to speed up the simulation process.

Tom De Schutter, writing in Synopsys’ TLMCentral, is running a competition for sensor device modeling. The deadline for submissions is in 16 days. Start coding.

Mentor’s Colin Walls addresses an engineer’s concerns about real-time signal processing with Android and other OSes.

And in case you missed the most recent System-Level Design newsletter, here are some standout blogs:

–Mentor’s Jon McDonald looks into how differences of opinion can affect design.

–Synopsys’ Achim Nohl addresses the question of what makes one model better than another.

–Cadence’s Frank Schirrmeister expounds on the importance of software in hardware designs.

–Sonics’ Frank Ferro pulls back the covers on the reasons why SoC design is suddenly much more interesting to a lot more people.

–Arteris’ Kurt Schuler adds meat to the argument that the time to invest in semiconductors is during a downturn.

–eSilicon’s Doug Ridge draws a parallel between the odd mix known as turducken and SoC design.

–Methodics’ Simon Butler digs into why IP distribution is such a big problem.

–And Atrenta’s Tiffany Sparks looks at some electronic designs that literally can change lives.

By Ed Sperling
Synopsys signed a definitive agreement to buy Magma Design Automation for $507 million, or $7.35 per Magma share, strengthening its hand in both the analog and digital tools and yield management markets.

Magma had been struggling for years, but over the past several years had expanded its portfolio to include advanced digital tools,analog design automation, one of the thorniest issues for shrinking features at each new process node, and into the manufacturing yield arena, where it struck an alliance with Applied Materials involving CAD and inspection systems for faster yield ramp.

John Chilton, senior vice president of marketing and strategic development at Synopsys, said that the real benefit of this acquisition is faster time to market for customers. “What we get is the ability to accelerate development,” he said. “We really are getting more requests for more technology. Deep-submicron CMOS is very complex in terms of materials, the number of transistor and the parasitics. Tools have to do more.”

He noted that Synopsys could have developed these capabilities internally, but it would have taken longer and cost more money than what it will achieve by buying Magma.

Phil Bishop, corporate vice president of worldwide marketing at Magma, said the combination makes a lot of sense. “On the digital side, we have both been working to advance customers to 28nm. The second piece is analog, and we have products that are extremely complementary to Synopsys and which have been doing very well in the market.”

Interestingly, Magma was the last completed IPO before the 2001 recession. Apache Design filed for an IPO in May, but was purchased by ANSYS before the actual public offering.

Both companies will continue to operate independently until the deal is finalized.

By Ed Sperling
System-Level Design sat down to discuss 2.5D stacked die with Vassilios Gerousis, senior architect at Cadence; Drew Wingard, CTO at Sonics; Kurt Shuler, director of marketing at Arteris; Kalar Rajendiran, senior director of marketing at eSilicon, and Hamid Savoj, technology fellow at Magma. What follow are excerpts of that discussion.

SLD: It sounds like the biggest hurdle is the business infrastructure. Is that accurate?
Gerousis: Yes. It’s the economics and business that are holding things up.
Savoj: That’s a big challenge, but it’s not the only one. The tools and other things will come over time.
Shuler: What we’re implying is that there’s going to be a platform approach where you have one key part somewhere in the stack you’re going to re-use, like an LTE co-processor. But it’s taken awhile for people to go from everything homegrown to having a platform approach even within a company. The mindset that has to change so you can do it for multiple pieces of silicon—and multiple pieces of silicon they may be purchasing from somewhere else—is huge.
Wingard: The business change is about taking advantage of partitioning. With respect to the way designs are being partitioned today, 2.5D is already practical. You can save cost, form factor, reduce power, apply new thermal properties by doing 2.5D today. If you want to get even more benefit, now you have to deal with other issues. But people do know how to do a lot of this stuff. The basics about taking standard parts and taking that version that isn’t already packaged in medium- to high-volume production has been done for awhile.

SLD: Is it really cheaper though?
Gerousis: The iPhone was built from multiple parts from different companies. My assumption is that the next iPhone will be a stack. It will be DRAM on top of the other parts.
Savoj: It will be a packaging solution.
Gerousis: It will be more like a niche product being sold in the market at a cheaper price. The more consumers can buy it, the more the price will go down.

SLD: Will the risk go up or down in 2.5D?
Savoj: As you create more partitions between analog and digital and memory your risk goes down. In a 28nm [planar] chip, if your analog part doesn’t work it doesn’t yield. But if you can separate that into three different pieces and you’re using an older part for analog, then that’s no longer a consideration. That helps yield and reduces risk.

SLD: But if something goes wrong doesn’t the cost of failure—and therefore the risk—actually go up?
Shuler: The more times you touch it the more risk you incur.
Gerousis: But people do that already today. They take multiple chips and integrate them. You may have additional risk, but it won’t be the same. Putting analog on 28nm is riskier than using analog at 65nm.
Wingard: If I’m a semiconductor company and you, the OEM, agree to pay as much money for a six-die stack as you would have paid for six separate die, it’s a win. Unfortunately, the OEMs know that when things get integrated they get cheaper. That’s where the risk/reward equation needs to be considered very carefully. I don’t pay the sum of the piece parts. There are some application-level exceptions where the benefit of form factor reduction is sufficient to change that equation, but by and large you pay less for integration.
Rajendiran: That’s just one aspect of it. The other aspect is time to market. Form factor affects unit cost. Every chip you do is not going to be cheaper, but the basic assumption is that most of the chip already has been pre-verified. This will save an enormous amount of time in functional verification. One of the challenges is that when you stack die a lot of things will break, so the risk will shift. But if you don’t use pre-verified pieces in a tile-based approach, you will actually increase the risk.

SLD: Verification goes down but validation goes up, right? The challenge is how is all of this stuff being used together.
Wingard: That validation was still required. You shift work from one venue to another. My view of how good system designers work is that they’re masters of abstraction. They don’t even know it. But there’s some part of the system that they did before that worked, and what’s new shouldn’t impact that. You spend all your energy on the new stuff. If you need to go down to the transistor level to figure out what the risk is, then you tunnel down. What’s interesting, though, is what corners were cut the last time? A chip that was cut into a piece with a whole operating system view and drivers so it looks like a plug-in model at the software stack level, then it should work. We have not been good as an industry at that.

SLD: And it may be harder to get to embedded software in a stack.
Wingard: The challenges of debug are daunting.
Savoj: There could be some advantages to that. If you have a part that’s already done and memories are available then you just work on the digital part. You can use an emulator to map your system to an FPGA and then start developing your software.
Wingard: And assuming the emulator works fast enough to make the mixed signal part work. There are a bunch of partitioning decisions you have to make.
Savoj: But even today when people want to do software development they do a chip that’s not as fast. The teams are working to getting the best speed and power, and then they put it all together.

SLD: But if you go into a 2.5D stack with Wide I/O, won’t you get a significant boost in performance and lower power?
Shuler: Yes, you’re removing a constraint on both of those.
Wingard: But even if you use an interposer, with Wide I/O you’re dealing with a 50-micron thin piece of silicon. That’s just fundamentally harder. Most of the rest of the 2.5D is using regular wafers. Wide I/O defines the move to 3D. You have to bite off some of the problems to get there.

SLD: Who benefits from 2.5D within our industry?
Gerousis: System integrators.
Shuler: Yes. They’re getting something that uses less power, less board space, and they won’t have to pay the same for separate chips.
Wingard: But does Foxconn become the assembly house? The original SoC was everything on one piece of silicon. Now it’s everything in one package. Maybe they put the die together. It sure looks like 2.5D reduces pressure on the SoC and the PCB. You can accelerate integration in the same package.

By Ed Sperling
System-Level Design sat down to discuss 2.5D stacked die with Vassilios Gerousis, senior architect at Cadence; Drew Wingard, CTO at Sonics; Kurt Shuler, director of marketing at Arteris; Kalar Rajendiran, senior director of marketing at eSilicon, and Hamid Savoj, technology fellow at Magma. What follow are excerpts of that discussion.

SLD: With stacked die we’re not just dealing with how the system works. It’s how the parts interact, right?
Wingard: The guys who were building the system already had that worry. This is where we are in the transition. We’re building the same kind of chips we were building before and we’re packaging them in a nicer way and a better electrical or thermal environment. It doesn’t have to introduce complexity. It’s only when we’re trying to take advantage of that and we change the partitioning that all these interesting things start to happen. We’ve got these expensive die that work fine on a PCB, but they can be ruined the moment you try to attach them.

SLD: And then isn’t there a problem with testing them?
Gerousis: Test becomes a bigger problem, which is why we have a partnership with Imec to develop a methodology for test.
Savoj: You have to make sure on each layer that you have a good part, and when you stack them up you have to make sure the overall system works. So you need a hierarchical testing ability where you can do it as one layer or as a system. That’s a challenge.
Wingard: You can’t afford to do all of the testing once you put the die together.
Gerousis: Once you have an assembled chip, how do you access the nth die? Those are the structures we have deal with, from the back-end PIM.

SLD: Isn’t the network involved in the test?
Wingard: It could be. If you look at what’s going on in the JEDEC world, everyone points to wide I/O as being the driver for the TSV. When two chips go together, wide I/O is the first thing anyone talks about. In wide I/O, it’s being handled by the memory guys. There are a couple balls dedicated for that, but they’re not going to tell you how it works. Don’t expect to hook up DRAMs from two different companies and expect it to work.
Shuler: We’re on the low-power committee there and it’s totally being driven by the memory guys. When you talk to the folks creating SoCs, you get memory dies from a number of companies and they may be pre-attached. If not, you connect them to your own. Who’s responsible for what and how you test it is uncertain. And one little speck of dust can kill everything.
Rajendiran: MCM is the traditional way of doing things. The ones who used to do them in volume were the graphics guys. They had older technology they couldn’t get to market so they put it together in high volume. The real question is whether this will go broad-based. Will it be limited to two or three dies from the same company or will it use many partners. We are doing chips where one die is coming from one company and another die is coming from another company, and we are being asked to put them together. If this picks up, and we believe it will, it will go broader-based than just memory and something else. That’s a big change. It may be memory and PHY and a processor and more. Standards have to come in and testing needs to be figured out. There will be a tipping point, and once the tipping point happens people will make the decision to do this.

SLD: What’s driving all of this?
Gerousis: What’s accelerating 3D today is memory. People are looking at integrating single or multiple memories with logic. That’s what’s accelerating this.
Savoj: It’s also the analog piece. No one wants to re-do analog. There’s a race to move along digital, but to transfer your analog libraries to digital takes a long time. If you can separate the two and use an older generation of analog stacked on the latest node of digital that’s going to help quite a bit.
Wingard: Some of the most mature technologies come out of the MEMS space. Because the mechanisms they use in MEMS, they need multiple dies used in different ways. They’ve been playing with ways of putting those together for some time, and they’ve managed to make those very reliable and very low cost. They don’t have a lot of connections, but they have done a lot of work there.

SLD: The business implications are quite interesting, too.
Shuler: It could commoditize a lot of things, as well as create a space for an intermediary who can put together a lot of pieces from other vendors and make sure it works. It could really tear apart the value chain.
Rajendiran: One thing that has consistently happened is a continuous push into finer and finer geometries. So if this really takes off, what happens to the foundries? That reduces the need to do a 28nm or 20nm chip.
Wingard: The idea of pushing all that analog stuff off to someone else is a really attractive approach. But I don’t understand what those analog chips look like. Am I really going to pick individual PHYs to build up a larger system? I don’t think that works economically. So now you’ve got some mixed-signal components that you use for mobile and communications. The analog guys have as much challenge as the digital guys. The technology can do a lot of things, but economically that will be a challenge.
Rajendiran: You won’t pick individual blocks. But that’s also why there is a standard products business where people sell SerDes. What if you use that as a tile? We were already doing that at the PCB level.
Savoj: It will be interesting to see if you can separate the analog from the digital. Right now companies are rushing to get a digital chip out. If you can separate that, will a company need to do all the pieces itself? If not, then you can go for the best solution in the market and you can assemble the whole thing in one shot.
Wingard: What are the fundamental things that change as we move to 2.5D? We get to the point where the scale is smaller. The bumps are smaller than we had with a package-on-package bump. That means the total number of traces goes up a lot, and that has some real implications of what might be possible. If you have a four-lane 10-gig PHY, that’s still a well-constrained interface. Would you do something different if the cost of a pin between them was 1/10th or 1/100th as much? That’s where partitioning gets very interesting. Once you’ve built your interposer it doesn’t matter if you’ve got 10 or 1,000 wires on it. It’s a little more to test, but incrementally it’s cheap. How would you engineer your analog function differently if you knew it was only going to be used in a 2.5D?
Gerousis: Things will evolve. If you get the 3D IC adopted faster you’re going to see a lot of IP done specifically for a 3D IC. The analog will be done specifically for that. The only thing you will not be able to do is take the PLL out. That must be inside the logic chip.
Wingard: But your clock and power management might well be inside this package.
Gerousis: Absolutely. You can put it on the 3D stack.
Shuler: Can you get rid of some of the PHYs that are used for inter-chip connectivity?
Wingard: That’s what wide I/O does.
Rajendiran: The large and midsize system OEMs that have deeper pockets can really differentiate themselves with this. They have latitude in terms of how they define wide I/O. The third-party IP guys have to implement their IP in tiles so they will need to define a common denominator. How do you sell to multiple people? We can pick up third-party IP and integrate it, or we can go to system OEMs and have a discussion about customizing the IP. This is like when we had workstations. Everyone had their own version. IBM had one. Silicon Graphics went crazy over wide I/O. Sun was more controlled and did it at the circuit level. We will come to a point where system OEMs will use this as leverage at the system level. Right now they’re doing differentiation in software. This will give them the edge back on the hardware side.

By Ed Sperling
System-Level Design sat down to discuss 2.5D stacked die with Vassilios Gerousis, senior architect at Cadence; Drew Wingard, CTO at Sonics; Kurt Shuler, director of marketing at Arteris; Kalar Rajendiran, senior director of marketing at eSilicon, and Hamid Savoj, technology fellow at Magma. What follow are excerpts of that discussion.

SLD: Is the push to 2.5D stacking really a simple evolution, or is this transition going to be more difficult than we realize?
Gerousis: There are few things we have not tried before. The silicon interposer is not just another interconnect. Another issue is RC extraction. There is no diffusion, which means there is no ground. We don’t know how to calculate the RC values. What is the reference point? Those are challenges we haven’t dealt with.
Shuler: Most of our customers are looking out at 3D logic and memory. We really haven’t seen too many questions surrounding 2.5D interposers. In 3D there are a lot of questions about the interconnects and how you can communicate through many pins and connections.
Wingard: I looked at one of our customer’s design recently. It’s an eight-layer stack, with lots of memories, and one of the layers is an interposer layer. It’s there because the through-silicon via technology isn’t ready for real high-volume production. One of the uses of the interposer is as a redistribution layer so they can get bond wires into those things in the middle. In some stacks where people were using spacers they will start using interposers instead. That solves a real practical problem. It’s real, it’s here, and it’s being driven by form factor more than performance.
Savoj: We have a few customers doing real 3D. We have taped out many chips. There is interest in 2.5D, but there is a lot of activity already in 3D. These are memory-based.
Rajendiran: 2.5D is here and real. There is a business need driving it, too. A few years ago everybody created IP blocks, which worked fine at the older technology nodes. Right now you have a lot of IP, but it’s in existing chips. Meanwhile, the risk has been going up for custom-design chips so that if you make a mistake it’s now a multimillion dollar mistake. This is a perfect storm, and 2.5D is a nice intermediate step to solve this. Maybe your SerDes is at 90nm and your ARM processor is at 28nm. But you can put them all together and get them out in a reasonable amount of time and not have to spend too much time on verification. In the past, the compelling business-risk ratio for this kind of thing wasn’t there. It is there now.

SLD: Was the delay in getting to stacking of die cost or technology?
Wingard: The delays in getting to 3D are substantial and well-documented. One of the challenges is the lack of standards. The idea that you’re going to layer one thing on another requires standards. You need to know the size of the connections, the verticals of the connections and how thin the wafers can be. But 2.5D doesn’t have any of that. It’s the mental equivalent of a PCB.

SLD: Xilinx already is touting 2.5D. What’s different about that?
Wingard: Theirs is less focused on form factor and more on scalability. But that’s what makes 2.5D so practical now. The work that the flash industry did on proving how to stack and do these intermediate wire bonds in massive volumes at low cost means that changing that layer for interposers is pretty minor. There are some characterization problems that require you to figure out what you’re going to build before you actually build it. But compared to making 3D work, this is much easier and very practical.
Rajendiran: The interposer is closing the gap between what you can do on a chip and a PCB. 2.5D is an easy solution.
Gerousis: Some of our customers are using 2.5D for high-performance processors. You have a lot of wattage, and that creates heat. And you want to link it to a memory. It becomes a practical environment for high heat and high wattage. 2.5D is a better environment than package on package. The other thing associated with it is that 2.5D affects performance of devices. If you put the TSV in a silicon chip, you’re not interacting with other active devices. You can connect to the package through a silicon interposer.
Wingard: The thermal benefits of using silicon as your interposer are really well known. Not only do we get the scale benefits, where the interposer can be closer to what we do on regular high-volume IC manufacturing these days, but we also get the thermal benefits. Even if we stack these on top of each other, the interposer in the middle has the same expansion coefficient as the die on each side. So it becomes a much more reliable package, as well. There are real benefits thermally, as well. These interposers help pull heat off the high-power application processor.
Shuler: Do customers have enough information to make a decision about whether to use a standard PoP and the cost ramifications of using 2.5D?
Rajendiran: That’s one of the things value-chain producers do. We’re part consultancy. We’ve built up a knowledge base over the past 10 years. It doesn’t make sense all the time, and we have the cost details to be able to make the decision of when it does or doesn’t make sense. If you have a regular structure chip, it may make sense to break it into tiles because yield improves. It varies, but not all customers would understand that. Big customers have so many chips that they’ve done with standard methodologies that it makes it easier. For smaller companies, one chip may have been done by one guy while another was done by somebody else.

SLD: Are the tools there?
Savoj: The biggest problem today is dividing system-level design into layers. How do you partition? What model goes where? If you’re stacking them, how are you going to distribute power? Which one is going to have more power? You’re going to have more heat in there. All of these things are new. We haven’t done them in the past. And the floor planning side is going to be very challenging.
Wingard: That’s doing real system-level design with flexible boundaries between the layers in a stack. But what we’re seeing mostly right now is a small amount of custom design and lots of re-use standard logic or previous-generation chips. For that class of design we’re in pretty good shape. The electrical environment in a 2.5D chip is way better than package on package. Thermally we’ve got lower-induction connections. There are lots of things that are much better. But there are all the materials handling challenges. This is a whole different kind of deal where you ship known good die. We need to think about the business relationships, too.
Gerousis: There are enhancements you need to do to the tools, but if you can enable some interactions between chips so the footprint on the top matches the footprint on the bottom of the chip.

By Ed Sperling

Sonics rolled out a new rapid-configuration environment for network-on-chip technology called StudioXE. The new tool relies on a system-level design approach to simplify deployment and changes at any point in the flow.

Open-Silicon struck a deal with memory maker Micron to explore opportunities around Micron’s new Hybrid Memory Cube, focusing initially on data networks and high-performance computing.  Open-Silicon also is working with GlobalFoundries on 28nm super-low-power technology, which combines body biasing with high-k/metal gate technology.

Magma likewise struck a deal with GlobalFoundries for the same process, this one for its Talus signoff reference flow tools.

By Ed Sperling
System-Level Design sat down to discuss where the hidden costs are in design with Ran Avinun, marketing group director for system design and verification at Cadence; Ken Brock, senior product marketing staff member at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Bo Gao, new product program director of design technology at Cypress Semiconductor, and Bob Smith, vice president of marketing and business development at Magma. What follows are excerpts of that conversation.

SLD: Is the increasing productivity from tools solving some of the employee issues of overwork?
Gao: No. You can run things today anywhere in the world. But if you’re running continually for years, it can be very stressful.
Avinun: If you have more automation and can do better planning and management, will that reduce the stress?
Gao: It may help, but the pressure is growing. I talked with engineers who are planning for cost reduction of a chip that hasn’t even taped out. It’s a treadmill.
Smith: When there’s so much competition it’s hard to slow down. Being always connected is stressful. In the early 1990s the Internet wasn’t even there. It is taking a toll, but I don’t know how to measure it.
Brock: It’s taking a toll, but it is also allowing for global design. If you want to get a hold of one particular person in a design you can do that. It might be three in the morning, but you can ask why they did something. That can save a tremendous number of errors. There’s a real positive to having that level of communication and to being able to do around-the-clock design. And on a complex design that can be very difficult if you have a lot of interaction. There’s a certain way we’ve structured IP to be more productive, such as running the characterization farms. It can be somewhat planned.
Avinun: It may just be our industry, too. I don’t see the same stress in other industries. In the 1990s and early 2000s there were a lot of VCs in this industry.
Rajendiran: Every industry goes through that. It’s a lifecycle. We are in a mature industry. The semiconductor industry is 50 years old and it’s going to be $300 billion this year. But if you take the memory and the flash chips out that number drops significantly. The bulk of it is mass production. The first 15 years of the semiconductor industry it was growing 30%. It hasn’t grown anywhere near that number in recent years. Consumerization has caused the fragmentation of the market. So has globalization.
Gao: The industry is not consumer-driven anymore. The semiconductor industry drives the consumer market. But if you look at all of these wonderful consumer devices today, how much of these devices are you actually using? You may be using 10% or 20%, and after a few years it’s obsolete. We’re really wasting a lot of energy, and it costs a lot of money.
Brock: And we’re trying to differentiate. The art form is to find the particular needs of a market segment. As you make the segments smaller and smaller you can design something for that particular segment, but it creates a lot of work for everyone.
Gao: That is true, and you have to do it because if you don’t, someone else will. But too many forces have come together too quickly.
Avinun: What you’ll see is more and more companies shipping full systems, including software. That will provide more margin for all of us and it will reduce the stress we have because we’ll be able to hire more people. If you look around, the companies that are doing well are Apple, Google and Cisco. They all have software and systems. The companies that will survive are doing more than just shipping silicon.
Brock: You need to include Samsung in that. They have figured out how to integrate IP and how to turn out full products.

SLD: Are there also hidden costs in some of the physical effects that are showing up at advanced nodes, such as power?
Smith: Some of it we expected. As you push above 1GHz you need to look at all the inductive effects on power rails. That has to be analyzed. If you’re doing a 400MHz chip that probably isn’t necessary. Or you can guard-band the chip and throw away area. You can design around it, but it’s more expensive.
Brock: And when you’re finishing off that chip, the power network has an impedance. You have to manage that impedance or your power grid sings. Things come up oscillating. From an EDA standpoint that’s a really tough issue to model. We’re seeing it on the IP side. People need D-caps all over the place.
Avinun: There is no way to accurately predict the power you get at the end. You can make educated guesses, but you can’t say what the final power will be. This impacts the packaging, the power supplies, and many other things.
Rajendiran: Today there are so many different modes and it’s not thoroughly tested for all the possible enumerations because there’s no time. You may have a standard USB, but it doesn’t always behave the same. When someone does the simulation, you may not test everything. There are too many combinations and too little time.
Brock: Now that we have this ability to do power down and power modes, people are using them. But if you have five blocks that can each be at three different voltages and you have last minute changes on the design, not everything is going to be tested.

By Ed Sperling
System-Level Design sat down to discuss where the hidden costs are in design with Ran Avinun, marketing group director for system design and verification at Cadence; Ken Brock, senior product marketing staff member at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Bo Gao, new product program director of design technology at Cypress Semiconductor, and Bob Smith, vice president of marketing and business development at Magma. What follows are excerpts of that conversation.

SLD: So what’s changed?
Smith: There used to be a design platform. If you go back to the good old days of ASICs, all the IP was there, it was all integrated into the process, and you knew you could get the chip out the door. Now we have all these full-custom guys who do everything from scratch. The ASIC is waning because of that. People now want to go to the ASSP-COTS (commercial off-the-shelf) model and they don’t know how to do all of this stuff. So an eSilicon comes in and builds the bridge between the people who used to have the platform and people who want to take advantage of COTS. And then you find out you forgot a PVT (process-voltage-temperature variation). You have to deal with discontinuities, rush charges and rip up specs. A lot of these things can be planned for, but a lot of them can’t.
Gao: The other issue is that the lifespan of chips is so short that quite often you can’t even get your ROI back. You have to make chips that can last years instead of just a few months.
Smith: The whole industry is moving to software because it’s so expensive and risky.
Avinun: When people think about cost they think about silicon. Now it starts to include software. If you need to spend four months after you get the silicon back from the lab working with software it has the same impact as if it was hardware.
Gao: We hear a lot of stories like this. Venture capitalists will give a team $10 million to tape the chip out, but after that it may take another $15 million for the software.
Brock: We have processors along with a full software stack, including codecs for voice. It’s a simple building block but to get theater sound out of cheap speakers you need DSP algorithms on the processor. If that all comes integrated—plus, by having the benchmarks in there you know you have the bandwidth and the right amount of power—it also gives you the system requirements. Knowing that works all the way through the stack helps mitigate the risk of those surprises that pop out. In addition, engineers hate to deliver bad news.

SLD: Because we now deal with the hardware and software stacks, what’s the hidden cost in terms of time and mistakes in lack of effective communication between different engineering disciplines?
Avinun: Most companies probably don’t know this cost. Even if it’s all in one building, the hardware team may be sitting on the first floor and the software team may be on the third floor. They don’t talk to each other. In other cases, they may be reporting to the COO, and he can’t bridge those two. If you go back 10 years ago, the focus was on silicon. In the next 10 years there will still be a realization that hardware is important, but integration at the hardware-software level will become equally as important. Teams will need to be reorganized. We’ve started to see that in some companies.
Brock: It’s managing the teams, as well. There needs to be someone on the hardware team whose job is to talk to the software people, and there needs to be someone on the software team whose job is to talk to the hardware people. Otherwise you get these data silos. And that communication has to go on within the development side. But, of course, those are the first people who get chopped in a budget cut.
Rajendiran: I hired a guy a long time ago who had a masters in electrical engineering and he was told he had to decide whether to take a hardware job or a software job. He ended up taking a software job because it’s harder to do it right. If you have software that’s well written it can be very effective and very efficient. But most of the software that’s written isn’t like that. You can do a very good job implementing something in hardware that is usually more efficient than software. Still, if you look at the cost of developing a chip, the hardware part pales in relation to the whole chip.

SLD: So what has to change?
Rajendiran: One of the changes we’re seeing is the revival of older process-based chips. We’re seeing 180nm and 130nm chips. They’re all proven. You build them up, combine them with a 40nm chip, and then put it in the same package. This is a big change, and it took many years to happen. Silicon in package isn’t a new concept, but people did that in the past because they missed their market window and wanted to add something else. The complexity and the risk are becoming huge, so with a system in package they can still get all the benefits of a new chip with some of the benefits of proven technology.
Brock: Can you do that in plastic?
Rajendiran: In some cases, but it’s not the same for every product.
Brock: That’s one of the things we’re seeing demand for and it’s affecting the power issues. If you can stay in a cheap plastic package and less than 2 watts, it’s a major price difference. If you have to go to ceramic there’s a giant cost increase. If you’re not planning for that ahead of time, you need a heat sink or a fan.
Gao: A lot of our products go into PCs. When you add software and firmware and drivers you think it’s okay from one laptop to the next, but when you actually move to the next one it breaks. The differences may be minor, but it’s enough to cause problems all over the place. And if you want to shift from one manufacturer to another, you have to do a lot of testing to make sure it all works.
Avinun: One of our customers talked about testing on hundreds of different products from software vendors and laptop vendors. There are trends to deal with some of those hidden costs at the IP level, which is why verification IP has become so important. IP re-use is becoming more important. There is a need to make sure the IP is qualified to work in certain environments.

SLD: It goes even beyond that. Software is never verified at the level of hardware.
Avinun: And when we define IP today, we include software and some of the drivers. The lower layers are integrated through the software stack. How do you integrate 10 layers of a software stack. And in general, it’s important to start IP integration early.
Smith: There’s the human side of this, too. Everyone is being asked to do more in less time with the same or fewer people. We hear about people getting up at 3 in the morning to make sure a certain run was okay. But is there a hidden cost in burnout? We may be pushing things so hard that the workforce is burning out.
Gao: Some of our guys are working day and night. They push really hard. That’s causing employee burnout and causing family problems. There’s a lot more work than in the past.
Brock: And it’s a hidden cost. People don’t want to talk about it. People used to have one job. Now they have two or three jobs and they’re making mistakes.
Gao: You used to work in the office and go home. Now you have the ability to work anywhere.