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Manufacturing Challenges 3D NAND Deployment

Thursday, August 31st, 2017

Jim Feldhan, president of Semico Research and veteran semiconductor analyst, shares his views on the challenges of moving from 2D planar to 3D NAND flash.

By John Blyler, Editor-in-Chief, Electronic Systems Design

3D NAND flash is touted as the eventual replacement for bit density limited 2D planar NAND flash. Its arrival into the mainstream memory market has been delayed by several years but should commence toward the end of 2017.  The delay has been caused by a steeper than expected learning curve in the manufacturing process. To understand why, Electronic Systems Design spoke with Jim Feldhan, founder and president of Semico Research Corp. What follows is a portion of that interview. – JB

Blyler: What are the general trends in NAND flash technology?

Jim Feldhan

Feldhan: 3D NAND is an evolutionary, architectural change that was needed to deal with the scaling limitations faced by planar 2D NAND memory. One major benefit of 3D NAND is that it will be manufactured on slightly older and less expensive process nodes.

Blyler: What unique costs are incurred for the manufacturing of 3D NAND Flash?

Feldhan: Depending upon the architecture, manufacturing at higher process nodes like 40nm can save money in terms of lithography requirements. However, since a common practice is to make 32 to 48 vertical layers or more in the 3D design, a significant increase can occur in etch costs. Holes must be etched between the different stacked layers to serve as inter-connections between the vertical layers.

Even though 3D NAND go back to older, higher process nodes for the lithography, the bit density is still increased via vertical stacking. The trick has been to fine tune the etch processes so that the yields remain good while achieving lower costs. Like any new process technology, it takes a while to get up that learning curve to maximize the yield.

Blyler: Increasing the need for additional etching should be good news to the semiconductor capital equipment companies.

Feldhan: Yes. With 3D NAND, you’ll have an array that is more like a cube or a three dimensional chess board with interconnections and wires going horizontally and vertically through the matrix. That is why companies like Applied Materials and Lam Research are thrilled since memory manufacturers will have to buy 5 or 10 times the amount of etch tools.

On the technology side, there has been interesting things with the resist, specifically, they can do several etches with the same coating of resist. More specifically, new materials on the resist allows for multiple etches without recoating. This process will save both time and money. [Editor’s Note: A resist is a thin layer used to transfer a circuit pattern to the semiconductor substrate which it is deposited upon.]

Blyler: Is 3D NAND more reliable than planar?

Feldhan: One of the original questions was how reliable is 3D NAND flash. The relaxed lithography node means you are not squeezing everything together so cross-talk is less. Also, 3D NAND has substantially more interconnections with vertical architecture that might provide you with access to more redundant cells. These redundand cells could be used if or when other cells fail. As 3D NAND has only been out for a few years, I haven’t really seen any lifecycle test data. But what I hear from Samsung and Micron is that 3D NAND is getting good acceptance from their customers. That’s impressive as many of the early customers are in data center applications that are really particular about failure rates.

Blyler: How does the Intel-Micron Optane differ from other 3D NAND flash technologies?

Feldhan: The Intel-Micron technology is called 3D Xpoint. They’ve described it as changing the physical properties of the material, which sounds more like a phase-change technology than a 3D NAND architecture. Further, the description made it seem different from the phase-change technology announced by IBM many years ago. Apparently, Intel-Micron have spent quite a bit of time working on a new material that they think solves all the problems faced by the original phase-change memory devices.

Blyler: So the Intel-Micron 3D Xpoint technology seems like it will be competing with 3D NAND flash. Is that correct?

Feldhan: Well, the XPoint platform is a different technology than with what everyone else is doing on 3D NAND. But Intel is doing both approaches, as I understand it. Their fab in China is gearing up for 3D NAND in production. My estimation would be that the Xpoint is a new technology and probably has a much higher bit cost, which would explain why they are focusing on SSDs and more so on the enterprises and server farm apps.

Blyler: Let’s return to 3D NAND manufacturing issues. At some point, won’t that technology need to move to the latest process nodes and/or contain ever-increasing layers to stay competitive with the bit cost?

Feldhan: Yes, they will eventually have to move to finer levels of lithography or be able to continue to go up in vertical layers. Or some type of combination. When the major manufacturers rolled out the first 3D NAND, they were saying it would be scalable, i.e., 24 layers at first, then 32 layers to 48 layers and etc. But I haven’t seen them progress as quickly as they mentioned. So I think they are now more focused on maximizing yield and reliability. [Editor’s Note: At the 2016 IEDM conference, SK Hynix discussed stacking technologies that could potentially enable over 256 memory cell layers.But it wasn’t clear when those levels would be reached.]

Blyler: When will 3D NAND become a mainstream memory technology?

Feldhan: On the plus side, the cost of 3D NAND is reaching equivalence with 2D planar NAND. Over the last year or so, NAND flash memory prices have been driven upward from tight supply and strong demand (see Figure). These aggregate average selling prices (ASP) are average prices for all densities and technologies.  As 3D NAND production comes down the manufacturing learning curve, the cost per bit for 3D NAND will fall and 2D NAND will have to match the price to remain viable in the market. Ultimately, 3D NAND will have the lowest cost per bit and will supplant 2D NAND especially in the large density parts.

NAND Pricing

Figure: With a tightening supply and strong demand, prices for all NAND devices are climbing. Before too long, 3D NAND will be on par with 2D planar memory. (Courtesy of Semico Research).

Blyler: Thanks, Jim.

Blog Review – Feb. 18 2014

Tuesday, February 18th, 2014

Grand prizes in Paris design; variability pitfalls; snap happy; volume vs innovation

By Caroline Hayes, senior editor

One of the most visually arresting blogs this week is from Neno Horvat at Dassault Systèmes. A fashion parade of projects set against the backdrop of Hôtel National des Invalides, in Paris. The occasion? The Festival de l-Automobile International (FAI) and the Creativ Experience award and the Grand Prix for research into the intelligent car.

Using a blog as a real community jumping point and information service, Shelly Stalnaker’s blog directs us to fellow Mentor Graphics author, Sudhakar Jilla article about the variability pitfalls of advanced nodes design and manufacturing.

Happy, snappy days are conjured up in the blog by ARM’s rmijat, in which he recounts his smartphone photography presentation at Electronic Imaging Conference. One of the week’s most detailed blogs, he takes us through the history of the camera phone to computational photography and future prospects.

Jack Harding, eSilicon, left Las Vegas a richer man, not from a big win, but by reflecting on the prospect of how few companies can bring to market the ICs needed for all the innovation that CES promised.

Tuesday, January 14th, 2014

Gabe Moretti, Contributing Editor

One of the conclusions that can be reached from the contents of the 2014 forecasts I collected for Chip Design (see http://chipdesignmag.com/sld/blog/2014/01/07/eda-industry-predictions-for-2014-part-1/ and http://chipdesignmag.com/sld/blog/2014/01/09/eda-industry-predictions-for-2014-part-2/)

Is that developing 14 nm process manufacturability and its EDA support is taking longer than expected.

The EDA industry has been stellar in solving logic problems.  As long as the only necessary thing was a new algorithm EDA responded in time and with superior solutions.  But this time physics got in the way.  I do not mean theoretical physics.  This would “just” require new algorithms, or may be new data management schemes.  I am talking about the boundary of what is physically possible with ultraviolet light.  Semiconductor manufacturing has reached the limit of what is possible to do with existing machines.  And going to X-rays technology is a huge investment both in time and money.  And a nagging question remains: can semiconductor material be reliably manipulated at 10 nm or smaller sizes?  What are the limits to commercial feasibility?

Although engineers and scientists think about what is possible, business managers think about what is sellable.  The harsh reality for all the scientists and engineers employed in EDA and semiconductors is that if the company does not make money there is no work.  And if there is no work there is no paycheck!

Yet much still needs to be done, a mountain of products need to be invented, designed, and produced, if nothing else to make the Internet of Things (IoT) real.  Thus we need to become even more creative.  It is not just a matter of manufacturing more transistors on the same die.  It is a matter of developing very complex systems while working within the boundaries of present day availability.  It is time to think in systems terms, not just on one product terms.  Packaging, hardware/software tradeoffs, physical communication channels, bus protocols, those will be the important issues facing architects and developers.

I am convinced that the fundamental question facing system companies today is not when can I use the latest process technology but how can I use present processes more efficiently.  We have not, I am sure, reached the limit of low power circuitry at 90, 65, or 45 nanometer processes, let alone 22 nm.  There is much room for creativity and in fact discovery.  Real men do not use the latest process any more.  To begin with there is now a significant presence of women in our industry that have shown not only to be equal but better in significant number than men.  And by unit numbers alone, electronic products built with “older” processes are far greater in number and produce more revenue world-wide than those produced with the latest technology.  I may enjoy my 4G phone but I love my programmable oven.

From SEMICON West 2013: Luc Van den hove of imec

Wednesday, August 14th, 2013
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John Blyler interviews Luc Van den hove, CEO of imec.