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Blog Review – Monday, July 27 2015

Monday, July 27th, 2015

IoT for ADAS; ESC 2015 focuses on security; untangling neural networks; what drives new tools; consolidation conundrum; IoT growth forecast; three ages of FPGA

Likening a business collaboration to a road trip may be stretching a metaphor that would make Jack Kerouac blush, but David McKinney, Intel, presses on as he explains Intel and QNX’s ADAS solution, based on Intel IoT for automobiles. He includes some interesting links and a video to inform the reader.

A review of ESC 2015 shows that Chris Ciufo is not only ahead of the curve, advocating embedded security, but also not one to pass by a freebie at a show. He relates some of the highlights from the first day of the Santa Clara event.

Neural network processors hold promise for computer vision, believes Jeff Bier, BDTI. His blog explains what work is needed for the scale of computation the industry expects.

Posing an interesting question, Carey Robertson, Mentor Graphics, asks what prompts the development of new tools. He blends this with helpful information about the newly launched Calibre xACT extraction tool, without too much “hard sell”.

“It works!” is the triumphant message of the blog co-authored by Jacek Duda and Steve Brown, Cadence. Reporting from this month’s workshop where Type-C USB was put through its paces.

What to do with wireless IP is asked and answered by Navari Nandra, Synopsys. He explains what can be done and how it can contribute to the IoT.

The SoC market is consolidating fast, says Rupert Baines, UltraSoC, on an IP Exteme blog. This poses two challenges that he believes licensed IP can simplify.

A common proposition is to move from Intel to ARM, and Rich Nass, ARM presents a well-rounded blog on how to make the transition, with some input from WinSystems hardware and software experts.

Forget consumer, the future of the IoT growth is in enterprise, reports Brian Fuller, ARM, observing analyst IDC’s webinar on which parts of the IoT will be lucrative and why.

Recalling the talk by Xilinx Fellow, Dr. Steve Trimberger, Steve Leibson, explains the three ages of the FPGA, with a link to a video on the history of the technology.

Caroline Hayes, Senior Editor

Blog Review – Monday July 13, 2015

Monday, July 13th, 2015

Gary Smith, remembered; ARM Micro:bit collaboration begins; IoT friend or foe; ITA tariff call; Russia recognises Indian American scientist’s IGBT contribution; DDR4-3D DIMMs uncovered

A popular man, who came to be Mr EDA, Gary Smith, is remembered by Graham Bell, Real Intent. Gary passed away peacefully after a short illness, aged 74 earlier this month. Graham remembers his early career, some personal milestones and his route to his eponymous EDA consultancy and much affection from fellow engineers, journalists and others who met him.

The long-awaited BBC Micro:bit initiative between ARM and the BBC has been finalised. Gary Atkinson, ARM details the educational, inspirational project, and includes a short video.

We all know the IoT, but should it be viewed as a friend or foe, asks Alyssa, Dassault Systemes. Her blog includes advice on how to spot the difference.

Advocating a final program for the Information Technology Agreement (ITA), John Neuffer, SIA, offers consul on a tariff-elimination staging plan, to boost semiconductor sales.

It takes all sorts, as my gran used to say, but this variation is rarely celebrated. Nazita Saye, Mentor Graphics, celebrates the award of Russia’s top technology award to an Indian American scientist, B Jayant Baliga, for his work on IGBTs in the 1980s – better late than never.

You can hear the rustle of datasheets, reading Marc Greenberg’s blog, Synopsys. He delves into the Samsung DDR4-3D stacked DIMMs, using TSVs. He takes an engineer’s (rather than marketing) approach, seeking out these treasures and some sound advice on why it matters.

Caroline Hayes, Senior Editor

Blog Review – Monday, June 22 2015

Monday, June 22nd, 2015

Yonsei Uni team up for 5G; Hold that thought; now catch it; ARM and UNICEF; Industry and Education breathe life into EDA; Connected driving clears the road ahead

Researchers at Yonsei University have demonstrated a real-time, full-duplex LTE radio system at IEEE Globecom in Austin, Texas, using a novel antenna approach and working with National Instruments SDR platforms and LabVIEW graphical programming environment, reports Steve Leibson, Xilinx.

“Hold that thought” takes a new turn, as an anonymous blogger at Atmel describes the MYLE TAP, a wearable ‘thought catcher’. The touch-activate and voice-powered device automatically converts thoughts into actions. An interesting prototype or a recipe for disaster if it falls into the wrong hands?

Charity doesn’t always begin at home, sometimes it’s a warehouse in Copenhagen, Denmark. Dominic Vergine, ARM, visited the UNICEF global procurement hub and considers what wearable technology can provide, building on the low-tech, wearable technology of the MUAC band to test for malnutrition.

Building on a presentation at DAC 2015, Richard Goering, Cadence, considers how to academia and industry can work together to revitalize EDA.

The road ahead is smooth for the connected car, reports John Day, Mentor Graphics, if you are driving a Jaguar Land Rover (JLR), anyway. He examines the connected car technology that can identify and share data on potholes, broken manholes and other hazards.

Sloth is a deadly sin, especially in IP software development, warns Tom De Schutter, Synopsys, as he examines how laze in automotive testing can be absolved with virtual prototypes as an alternative to hardware, making earlier, broader, more automated software testing available.

Caroline Hayes, Senior Editor

Power shift reflects the need for a new way of thinking

Monday, June 15th, 2015

Handheld and smart devices are driving a methodology shift in power analysis, writes Caroline Hayes. Mentor Graphics has recognised the need to calculate power values earlier in the design cycle, and has introduced the Veloce Power Application software to its portfolio to help SoC designers shave time off development and testing.

There is an increase in switching power for logic and memory, observes Vijay Chobisa, Product Marketing Manager, Mentor Graphics, which is increasing dynamic power demands. This can lead to problems, such as the same chip overheating when used in difference phones and applications, due to ‘environment discrepancies’.

Vijay Chobisa, Product Marketing Manager, Mentor Graphics

As mobile devices are used for gaming, GPS and streaming video applications, the power consumption has to be adequate to allow for high-end applications, such as high resolution videos to run. According to Chobisa, there is a wrong way and a right way to design an SoC’s power analysis to ensure it is up to the task.

“A functional test bench is not appropriate for power,” he says, explaining how a functional test bench can be used to calculate power, using extrapolation technology to find the power for an SoC. The problem is that it shows the power peak early in the test. “Run an OS (Android, Linux or Windows) in live mode, and the real power is in a different location,” he continues. Not only that, but the power peak is much higher than the test bench. Yet, today’s applications need the performance capability to run 100 to 200 million cycles, allowing system design engineers to see the power problems.

The Power Application is part of Mentor Graphics ecosystem of hardware, Double Maximus and Quattro

What is the alternative? “Emulation is not right, either,” says Chobisa, due to the visibility it affords. “Visibility is needed for all design modes,” he says “-that, and scalability”. Simulation is not the solution either, as it does not have the speed capability for 100 to 200 million cycles, confirms Chobisa.

This leads to Veloce Power Application, introduced just before DAC. It runs on Veloce OS and which adds an activity plot, to reflect a real switching scenario, and a Dynamic Read Waveform API (Application Program Interface) to the existing UPF (Unified Power Format) and SAIF (Switching Activity Interchange Format) applications. The Dynamic Read Waveform API replaces file-based analysis flow.

Another advantage, points out Chobisa, is that it has RTL and gate-level support. “The RTL support is early,” says Chobisa, “providing the power budget and trade-off early in the SoC design”. Referring to gate level support, Chobisa notes that this is later but gives more accurate power.The Power Application software runs emulations and generates activity and SAIF files. These files, together with a power library tool calculate the Watt of power consumed for an activity.

When the emulation is run, a FSDB (File System DataBase) is supplied to the power analysis tool. It is large enough to supply data on the activity for every clock and node in the design. This is a new flow, says Chobisa, explaining that it eliminates the file transfer and file creation and produces a significant improvement in speed.

Information from the Power Switching Activity Plot is transferred to power analysis tools, for a more accurate power calculation at the system level.

“Benchmark numbers show that it can read designs of 24 to 72 million cycles at a two to 4.25x improvement in speed,” he says, “reducing one month into one week”.The first Veloce Power Application ecosystem partner is ANSYS with PowerArtist.
The collaboration addresses energy-efficient IP and SoC designs. Integration with ANSYS PowerArtist is available to mutual customers on a limited basis. Full production release is scheduled for early Q4 2015.

Caroline Hayes, Senior Editor

Blog Review – Monday, June 08, 2015

Monday, June 8th, 2015

DAC duo announce DDA; Book a date for DAC with ARM, Ansys, Cadence; Synopsys and Xilinx; True FPGA-based verification

Announcing a partnership with Cadence Design Systems at DAC 2015, Dennis Brophy, Mentor Graphics teases with some details of Deug Data API (DDA). Full details will be unveiled at a joint presentation at the Verification Academy Booth (2408) on Tuesday at 5pm.

Amongst demonstrations of an IoT sub-system for Cortex-M processors, ARM will show a new IP tooling suite and the ARM Cordio radio core IP. There will be over a dozen partners, reports Brenda Westcott, ARM, in the Connected Community Pavillion and the ARM Scavenger Hunt. (DAC June 7 – 11, ARM booth 2428).

As if justifying its place at DAC 2015, Ravi Ravikumar, Ansys, explains how the show has evolved beyond EDA for SoCs. The company will host videos on automotive, IoT and mobile, and presentations from foundry partners. (DAC June 7 – 11, Anysys booth 1232).

If you are interested in the continuum of verification engines, DAC is the place to be this week. Frank Schirrmeister, Cadence, summarizes the company’s offerings to date, with a helpful link to a COVE (Continuum of Verification Engines) article, and provides an overview of some of the key verification sessions at the Moscone Center. (DAC June 7 – 11, Cadence booth 3515).

Back with FPGA prototyping system, HAPS, Michael Posner, Synopsys, invites visitors to DAC to come see the Xilinx UltraScale VU440-based HAPs. As well as proudly previewing the hardware software development support, he also touches on the difficulties of mapping ASICs to FPGAS.

More Xilinx-DAC news, as Doug Amos’s guest blog at Aldec, announces the era of true FPGA-based verification. He believes the end of big-box emulation is nigh, following the adoption of Xilinx’s Virtex UltraScale devices in its HES-7 (Hardware Emulation Solution, seventh generation) technology.

Caroline Hayes, Senior Editor

Blog Review – Monday May 18, 2015

Monday, May 18th, 2015

Zynq detects pedestrians; ARMv8-A explained; Product development demands test; Driving connectivity; Celebrating Constellations; Chip challenges

The helpful Michael Thomas, ARM, advises readers that there is The Cortex-A Series Programmer’s Guide for ARMv8-A available and introduces what is in the guide for a taster of the architecture’s features.

The Embedded Vision Summit gives many bloggers material for posts. The first is Steve Leibson, Xilinx, who includes a video Mathworks presented there, with a description if a real-time pedestrian detector running on a Zynq-based workflow, using MathWorks’ Sumulink and HDL Coder.

Another attendee was Brian Fuller, Cadence, who took away the secrets to successful product development, which he sums up as: test, test, test. (He does elaborate beyond that in his detailed blog, reviewing Mike Alrdred of Dyson’s keynote.

Anticipating another event, DAC, Ravi Ravikumar, Ansys, looks at the connected car and the role of design in intelligent vehicles.

Also with an eye on DAC, Rupert Baines, UltraSoC has a guest blog at IP-Extreme, and praises the Constellations initiative, with some solid support – and some restrained back-slapping.

Continuing a verification series, Harry Foster, Mentor, looks at the FPGA space and reflects on how the industry makes choices in formal technology.

A guest blog, at Chip Design, by Dr. Bruce McGaughy, ProPlus Design Solutions, looks at what innovative chip designs mean for chip designers. His admiration for the changing pace of design is balanced with identifying the drivers for low power design to meet the IoT portable phase.

Why do we need HDCP 2.2 and what do we need to do to ensure cryptography and security? These are addressed, and answered, by VIP Experts, Synopsys, in this informative blog.

By Caroline Hayes, Senior Editor

Blog Review – Monday, May 04 2015

Monday, May 4th, 2015

Steve Leibson, Xilinx, reports on an interesting academic program to ‘look at, poke, modify, and experiment with’ the MIPS RISC processor RTL using a simplified Imagination Technologies microAptiv processor core. The MIPSfpga program provides university CS and EECS departments access to a fully-validated, current generation MIPS CPU. There are also plans for the Imagination University Programme to expand this university program to the PowerVR graphics processors and FlowCloud IoT technology.

Two ARM server hardware platform used in cloud-based set-top box systems are explained in detail by Karthik Ranjan, ARM. The blog looks back at early cable TV systems and looks ahead to the IoT and cloud use in virtual network functionality (VNF) ahead of the VNF world Congress in San Jose this week.

In praise of an overlooked object-oriented language, Ruby, Michael Cizl, IP Extreme, presents a strong case and urges readers to rethink their choices.

Excitement is growing for the advent of Windows 10. Rambus speculates on the inclusion of a universal sensor driver set for environmental, biometric, proximity and motion sensing. Adam Shah, IDG, speculates on what this will mean for functionality for devices running the OS.

Wrestling with power, the panel of experts at the Electronic Design Processes Symposium, discussed if the industry needs to rethink tackling power for IoT devices in particular. Brian Fuller, Cadence, reports from the Monterey event.

Distilling a report from IHS Automotive, John Day, Mentor Graphics, identifies apps and trends that smartphones will bring to the in-car experience, from Apple to Android, with a graph of consumers’ preferences from Bluetooth for hand-free use, touchscreen to an auxillary hook to add an MP3 player or phone.

Returning to a familiar blog-topic, Michael Posner, Synopsys, compares hybrid prototyping vs prototyping bridges, using the company’s latest DesignWare Hybrid IP Prototyping Kits as a starting point for the IP prototyping discussion.

Caroline Hayes, Senior Editor.

Blog Review – Monday April 06, 2015

Monday, April 6th, 2015

It’s always tricky looking at blogs on April 1 st. So much technology, so many gags. I didn’t fall for Microsoft UK’s April Fool that Bing can read nerve pulses and brain waves to improve your web search, or HTC’s Rok the Sok, a smart tag which pairs socks in the wash and alerts the wearer when the sock is wearing thin. Many people downloaded Microsoft’s MS-DOS for Windows phones, and loved the joke. The most ‘successful’ or most reported, was CERN’s claim to have found The Force and that it was using it, Star Wars-style to reheat coffee in a mug and return books to a bookshelf while remaining seated. I won’t be at GSA Silicon Summit to get a chance to check McKenzie Mortensen’s claim that IPextreme’s Warren Savage has cut his long hair into a Silicon Valley ‘short back and sides’ – could it another April Fool?

I decided to narrow down my Blog Review search to genuine ones only (I hope!)

Three boards and three ways to write code are discussed by Thomas Aubin, Atmel, interviewed by David Blaza, ARM, ahead of the ARM Embedded Computing Board resource guide.

The pressure to be smart is examined by Matthew Hall, Dassault Systemes. He has latched on to the findings of the Aberdeen Group, that engineering groups must communicate and collaborate to predict system behavior ahead of testing.

Laman Sahoo, Arrow Devices, identifies three sources of confusion for Object Oriented Programming, to take the ‘oops!’ out of OOP.

The reports of the death or slowing down of Moore’s Law are exaggerated, concludes Brian Fuller, in his interview with Suk Lee, Senior Director, Design Infrastructure Marketing division, Cadence, ahead of the TSMC Technology Symposium. In conversation, Fuller pushes Lee on the progress of process development down to 7nm as well as FinFET development.

Ahead of the Embedded Vision Conference, Jeff Bier, BerkeIey Design Technology, looks at how academia and industry respond to neural networks.

3D printable heatsinks are examined by Robin Bornoff, Mentor Graphics, using FloTHERM, and FloMCAD.

Larry Lapides, VP of sales at Imperas, discusses security on connected devices using MIPS CPUs.

A biblical theme is adopted for an Eastertime post by Ramesh Dewangan, Real Intent. The David and Goliath struggle of large and small EDA companies is reported from the Confluence 2015, where one panel was ‘The paradox of leadership: Incremental approach to Big Ideas’, and ‘How to build the technology organisations of tomorrow’.

An interesting smartphone app by Philips to control lighting via WiFi is explored by Ashish D, Intel, but using an Intel Edison board.

Caroline Hayes, Senior Editor

Blog Review – Tuesday March 10, 2015

Tuesday, March 10th, 2015

An interesting and informative tutorial on connecting Ardino to the Internet when ‘in the wild’ is the topic that caught ARM’s Joe Hanson’s interest.

Sharing the secrets of SoC companies that accelerate the distributed design process, Kurt Shuler, Arteris, considers the interconnect conundrum.

Never one to shy away from the big question, Richard Goering, Cadence Design Systems, asks what is the key to IC design efficiency. He has some help, with panel members from the DVCON 2015 conference, organised by the Accellera Systems Initiative.

Contemplating NXP’s acquisition of Freescale, Ray Angers, Chip Works, and, with a series of bar charts and dot-graphics, deems the Euro-American couple a good match.

Experiencing an identity crisis, Jeff Bier, Berkley Design, is looking forward to attending Embedded Vision Summit, in May, and particularly, it seems, to the keynote by Mike Aldred, the lead robotics developer at Dyson.

The multi-lingual Colin Walls is brushing up on his Swedish as he packs for ESC (Embedded Conference Scandinavia) this week. He will speak at three sessions – Dynamic Memory Allocation and Fragmentation in C and C++, Power Management in Embedded Systems and Self-Testing in Embedded Systems, which he previews in this blog.

Delighted at Intel’s call for 3D IC, Zvi Or-Bach, MonolithIC 3D, argues that the packaging technology for SoCs, using data and graphics from a variety of sources.

Blogging from Mobile World Congress, Martijn van der Linden, NXP, looks at what the company is developing for the Internet of Things, including the connected, Tesla, car concept from Rinspeed.

Anyone looking into serial data transfers to replace parallel data transfer, can discover more from the blog, posted by Saurabh Shrivastava, Synopsys. The acceleration of PCI Express based systems’ verification and the difference power states of the interface has never been more relevant.

Blog Review – Monday, February 23, 2015

Monday, February 23rd, 2015

Next week may be a test for the German language skills of Colin Walls, Mentor Graphics, as he returns to Nuremberg for Embedded World 2015, where he will be presenting papers at the conference. He previews both How to Measure RTOS Performance and Self-Testing in Embedded Systems. And issues an invitation to drop by the company booth.

Another heads-up for Embedded World from Chris A Ciufo, eecatalog, who discusses heterogeneous computing, and not only how it can be applied, but what is needed for effective execution.

After seven years, start-up Soft Machines was ready to unveil its VISC (Variable Instruction Set Computing) CPU cores at Cadence’s Front-End Design Summit. Richard Goering unpicks the innovation that could revive performance/W scaling to boost power and performance.

A heart-warming case study from Artie Beavis, Atmel, shows how ARM-based wearable technology is being put to good use with the Unaliwar Kanega wristwatch, for the elderly.

Patient Michael Posner is not going to let something like gate counts flummox him. He explains not only the nature of logic cells – with some help from Xilinx – but always flags up a warning and advice for any prototype attempting to map RTL code.

Dark silicon, the part of a device which shuts down to avoid over-heating, is getting darker. Zvi Or-Back, MonolithIC 3D, believes his company’s architecture can throw light on a semiconductor industry that is on the brink of being derailed by the creep of dark silicon.

By Caroline Hayes, Senior Editor.

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