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Blog Review – Monday, January 19 2015

Monday, January 19th, 2015

Test case for lazybones; Mongoose in space, heads for Pluto; solar tracker design; new age shopping; IoT insight – the real challenge

The size of SoCs, security around EDA tools and the effort needed to test tool issues are all hurdles that can be mounted, asserts Uwe Simm, Cadence. His comprehensive post explains how the Test Case Optimizer (TCO) – a small generic (as in no special tools required or design styles are required) – can strip down simulation source files and reduce overal source input data size by over 99%.

After a stellar break, NASA’s New Horizons spacecraft reached Pluto. Not only does it have the ashes of astronomer Clyde Tombaugh, the discoverer of Pluto, it has a Mongoose on board – in the form of a MIPS-based Mongoose-V chip. Alexandru Voica, Imagination, tells us more about the rad-hard device manufactured by Synova.

An interesting project, and a worthy one too, is relayed in the blog post by John McMillan (Mentor Graphics). Cool Earth Solar designs and develops solar products and uses PADS to develop some of the monitoring hardware for the equipment that tracks the sun, and transmits data for the project.

A subject close to my heart, shopping, is explored by David McKinney, Intel, who has a guest blog from Jon Bird, Y&R Labstore. How to harness the data that make up shopping patterns, without freaking out shoppers. A startling obvious observation is “Retailers must first and foremost be shopper-centric” but what does that mean in the digital age and the Internet of Things era?

Demonstrating a helpful nature, David Blaza, ARM, points us to a report by McKinsey, about the Internet of Things. As well as Blaza’s observation relating to ARM’s Cortex-M devices on the edge of the IoT and ARM Cortex-A at the hub and gateway level, I was struck by Joep Van Beurden’s observation that the IoT is not about prices or power but connecting the hardware in a smart way to the cloud.

By Caroline Hayes, Senior Editor

Blog Review – Monday, January 12, 2015

Monday, January 12th, 2015

New year resolutions from ARM, IP Extreme; CES highlights from Cadence, Synopsys, ARM partners; Mentor looks back at 2014; Imagination looks ahead

It wouldn’t be a January Blog Review without a mention of resolutions. Jacob Beningo, ARM, is disappointed that DeLoreans and hover boards are not filling the skies as predicted in Back to the Future, but he does believe that 2015 should be the year of sound, embedded software development resolutions.

A challenge is thrown down by McKenzie, IP Extreme, to ensure the company meets its new year resolution to update its blog. If you find that the company has missed posting a blog by midnight Wednesday (Pacific time) you can claim a $100 voucher for a chop or restaurant of your choice.

It wouldn’t be the week after CES, if there were no mentions of ‘that show’. Michael Posner, Synopsys, looked beneath the cars, entertainment devices and robots to focus on sensors (and to mention DesignWare Sensor and Control Subsystem, which designs them).

Brian Fuller, Cadence, interviews Martin Lund, senior vice president for Cadence’s IP Group, at CES. Lund has some interesting observations about audio and video demos at the show and insight into the role of IP.

ARM was everywhere at CES, and Brad Nemire, ARM, has some great videos on his blog, with demos of partners’ devices, and also a link to a Bloomberg interview with CEO Simon Segars.

International finance was not covered at CES, but the mobile money payment services described in the blog by Catherine Bolgar, Dassault Systemes has a lot of ‘CES criteria’, connectivity, innovation and commercial applications, as well as the Vegas connection with cash. It is an enlightening view of how technology can help those without deemed to expensive to reach and service by conventional banking institutions.

Looking back at 2014, Vern Wnek, Mentor, considers the overall winner of the longest running EDA awards, the Technology Leadership Awards, Alcatel-Lucent. The award winnning project was the 1X100GE packet module includes 100Gb/s of total processing power and signals operating at 6/12/28GHz.

A world without wired cables, is the vision of Alexandru Voica, Imagination, who checks just how close a cable-free life is; encouraged with some introductions from the company, of course.

By Caroline Hayes, Senior Editor.

Blog Review – Monday December 22 2014

Monday, December 22nd, 2014

Women in engineering; Santa’s CFD plan; VIP list; Cadence focus at CES 2015; Microsoft Band teardown; DDR 4 disruption; celebrate energy efficiency

A daughter’s enjoyment in toy trains and train tracks is the source of inspiration for a genuinely concerned blog by Keith Hanna, Mentor. Why aren’t more girls studying engineering? He takes his parental knowledge and knowledge of engineering to ponder the question.

Computational fluid dynamics also provides a back-up plan for Father Christmas – just in case the premier sleigh develops a fault (bug?) on the night of the 24 th! Gilles Eggenspieler, Ansys and helper elves, have designed a new sleigh and his blog has the graphics to demonstrate effectiveness. He has even thoughtfully added in wind shield factor and stealth mode.

Things to remember about memory VIP: VIP Experts at Synopsys, advise of a technical seminar: Strategy to Verify an AXI/ACE Compliant Interconnect (1 of 4) – just in case the Christmas TV schedules lets you down this year.

Looking ahead to the 2015 CES, Jacek Duda, Cadence, gives a glimpse of what Cadence will show in Las Vegas, reflecting the company’s focus on system solutions, including a TIP/DIP combination for mobile devices (and next year’s Christmas presents?).

Tear-downs are always fun and David Maidment, ARM, takes a look inside a Microsoft Band and have taken a look inside. He uncovers the treasure trove of an ARM Cortex-M4-based Kinetis K24 microcontroller for wearable devices.

Self-confessed candidate for the naughty list, Nazita Saye, Mentor Graphics, finds an excuse to celebrate the energy saving that electronics devices enjoy with a list of must-haves and a snap of the office Christmas tree.

Double data rate memory is set to turn the industry on its head, predicts Brian Fuller, Cadence. His blog cites Kevin Yee, Cadence product marketing director, and speculates on economics as well as the physics of the memory form.

Merry Christmas, happy new year and keep on blogging!

Blog Review – Monday, December 15 2014

Monday, December 15th, 2014

Rolling up her sleeves and getting down to some hard work – not just words, Carissa Labriola, ARM, opens a promised series of posts with an intelligent, and through analysis of the Arduino Due and there is even the chance to win one. This is a refreshingly interactive, focused blog for the engineering community.

It’s coming to the end of the year, so it is only to be expected that there is a blog round-up. Real Intent does not disappoint, and Graham Bell provides his ‘Best of’ with links to blog posts, an interview at TechCon and a survey.

There is a medical feel to the blog by Shelly Stalnake, Mentor Graphics, beginning with a biology text book image of an organism to lead into an interesting discussion on parasitic extraction. She lists some advice – and more importantly – links to resources to beat the ‘pests’.

Always considerate of his readers, Michael Posner, Synopsys, opens his blog with a warning that it contains technical content. He goes on to unlock the secrets of ASIC clock conversion, referencing Synopsys of course, but also some other sources to get to grips with this prototyping tool. And in the spirit of Christmas, he also has a giveaway, a signed copy of an FPGA-Based Prototyping Methodology Manual if you can answer a question about HAPS shipments.

Another list is presented by Steve Carlson, Cadence, but his is no wishlists or ‘best of’ in fact it’s a worst-of, with the top five issues that can cause mixed-signal verification misery. This blog is one of the liveliest and most colorful this week, with some quirky graphics to accompany the sound advice that he shares on this topic.

Blog Review – Monday December 08 2014

Wednesday, December 10th, 2014

Industry forecasts sustained semi growth; EVs just go on and on; Second-chance webinar; Tickets please; Play time; Missed parade

By Caroline Hayes, Senior Editor

Bringing 2014 to a close on an optimistic note, Falan Yinug, director, Industry Statistics & Economic Policy, Semiconductor Industry Association (SIA) tries to understand the industry’s quirky sense of timing while reporting that the World Semiconductor Trade Statistics (WSTS) program revised its full-year 2014 global semiconductor sales growth forecast to 9% ($333.2 billion in total sales) an increase from the 6.5% it forecast in June. It also forecasts that positive sales trend to continue with a 3.4% increase in sales in 2015 ($344.5 billion in total sales) and beyond, with $355.3 billion in 2016.

First road rage, now range anxiety. Apparently it is a common ailment for EV (electric vehicle) drivers. John Day, Mentor Graphics, takes heart from a report by IDTechEx which says that a range extender will be fitted to each of the 8million hybrid cards produced in 2025 and predicts the introduction in 2015 of hybrid EVs with fuel cell range extenders and multi-fuel jet engines to increase driver options.

It’s hardly a stretch to find someone who remembers using public transport before MIFARE ticketing, but Nav Bains, NXP looks at the next stage for commuters using a single, interoperable programming interface for commuters to tap NFC mobile devices to provide the ticketing service.

More time-warp timings, as Phil Dworsky, ARM, tells of a webinar entitled Avoiding Common Pitfalls in Verifying Cache-Coherent ARM-based Designs, which has been and gone but can be watched again, simply by registering. He even lists the speakers (Neill Mullinger and Tushar Mattu, both Synopsys) and lists what you missed but what you can catch again in the recorded webinar.

Enamoured with e code, Hannes, Cadence, directs people who just don’t get it to the edaplayground website, with links to a video for e-beginners.

Recap of what you missed, impactful blogs from the last 3 months
Perhaps frustrated that no-one seems to have notice, Michael Posner, Synopsys, patiently outlines some of his favourite blog posts from the last couple of months. He wants to draw your attention to prototyping in particular (it features heavily in the list) as well as abstract partitioning and the joy of vertical boards.

Blog Review – Monday Nov. 10, 2014

Monday, November 10th, 2014

John Haslet Hall, remembered; Cadence reminds us IoT is not so easy; ARM reaches out; Verification Academy learns to network; Sneeze please, you’re on Ansys simulation software.

John Haslet Hall (July 11, 1932 – October 30, 2014) is remembered by Graham Bell, Real Intent. The co-founder of Intersil was responsible for many milestone in our industy.

Panelists at the Cadence Mixed-Signal Technology Summit recognised the need for an ecosystem, process tools and IP and some co-operation. Richard Goering transcribes the insightful comments in his blog.

Offering a peek into his social calendar, Paul Rako, explains how a dinner with Bob Martin, Atmel, opened his eyes to ARM being more than just hardware IP. After checking with David Mathis, he shares some of Bob Martin’s thoughts, hints and tips on the architecture.

As the number of IPs integrated into SoCs increases, the Verification Academy clearly has a role to play and Matthew Ballance directs readers to how they can access its resources bringing old and new schools of thought together.

It’s true, your mother did know best, confirms Gilles Eggenspieler. I learned that “sniffs and sneezes spread diseases, catch them in your hank-er-chee-s” but a 21 st century teaching method is the simulation created by FAA Center of Excellence at Purdue University, using Ansys software to study pathogen travel in airplane cabins. Fascinating – but gross!

Blog Review – Monday Oct. 20, 2014

Monday, October 20th, 2014

OCP-onwards and upwards; infotainment in Paris; lend a hand to ARM; Cadence anticipates 10nm FinFET process node.

By Caroline Hayes, Senior Editor

An online tutorial from Accellera Systems Initiative, “OCP: The Journey Continues” is a five-part tutorial spanning the past, present and future of the OCP (Open Core Protocol) IP interface socket standard. Drew Wingard draws it to our attention, as one of the presenters, discussing OCP in SoC designs, such as verification IP support, TLM 2.0 SystemC support and IP-XACT support is Herve Alexanian, Sonics and himself as well as Steve Masters, Synopsys and Prashant Karandikar, Texas Instruments.

Elektrobit and Nuance have integrated voice with natural language understanding (NLU) in the virtual cockpit in Audi’s TT Roadster which is being shown at the Paris Motor Show. John Day, Mentor Graphics marvels at the results and speculates on its practical uses.

A plea from ARM’s Brad Nemire, to the community which celebrates its first anniversary this month. He invites comment on the community and proposed changes, all designed to make the community interactive and responsive. He promises the survey will only take five minutes of your time.

An informative review of technical presentations at the recent TSMC Open Innovation Platform (OIP) Ecosystem Forum prepares the reader of 10nm FinFET process node. Richard Goering Cadence, includes some graphics from two keynotes for those who could not make the Forum, with some warnings of what it will mean for design.

Low Power Is The Norm, Not The Exception

Friday, September 26th, 2014

Gabe Moretti, Senior Editor

The issue of power consumption took front stage with the introduction of portable electronic devices.  It became necessary for the semiconductor industry and thus the EDA industry to develop new methods and new tools to confront the challenges and provide solutions.  Thus Low Power became a separate segment of the industry.  EDA vendors developed tools specifically addressing the problem of minimizing power consumption, both at the architecture, the synthesis, and the pre-fabrication stage of IC development.  Companies instituted new design methodologies that focused specifically on power distribution and consumption.

Today the majority of devices are designed and fabricated with low power as a major requirement.  As we progress toward a world that uses more wearable devices and more remote computational capabilities, low power consumption is a must.  I am not sure that dedicating a segment to low power is relevant: it makes more sense to have a sector of the industry devoted to unrestricted power use instead.

The contributions I received in preparing this article are explicit in supporting this point of view.

General Considerations

Mary Ann White, Director of Product Marketing, Galaxy Design Platform, at Synopsys concurs with my position.  She says: “Power conservation occurs everywhere, whether in mobile applications, servers or even plug-in-the-wall items.  With green initiatives and the ever-increasing cost of power, the ability to save power for any application has become very important.  In real-world applications for home consumer items (e.g. stereo equipment, set-top boxes, TVs, etc.), it used to be okay to have items go into standby mode. But, that is no longer enough when smart-plug strips that use sensors to automatically turn off any power being supplied after a period of non-usage are now populating many homes and Smart Grids are being deployed by utility companies. This trend follows what commercial companies have done for many years now, namely using motion sensors for efficient energy management throughout the day.”

Vic Kulkarni, Senior VP and GM, RTL Power Business Unit, at Apache Design, Inc., a wholly-owned subsidiary of ANSYS, Inc. approached the problem from a different point of view but also points out wasted power.

“Dynamic power consumed by SoCs continues to rise in spite of strides made in reducing the static power consumption in advanced technology nodes.

There are many reasons for dynamic power consumption waste – redundant data signal activity when clocks are shut off, excessive margin in the library characterization data leading to inefficient implementation, large active logic cones feeding deselected mux inputs, lack of sleep or standby mode for analog circuits, and even insufficient software-driven controls to shut down portions of the design. Another aspect is the memory sub-system organization. Once the amount of memory required is known, how should it be partitioned? What types of memories should be used? How often do they need to be accessed? All of these issues greatly affect power consumption. Therefore, design must perform power-performance-area tradeoffs for various alternative architectures to make an informed decision.”

The ubiquity of low power designs was also pointed out by Guillaume Boillet, Technical Marketing Manager, at Atrenta Inc.  He told me that: “Motivations for reducing the power consumed by chips are multiple. They range from purely technical considerations (i.e. ensuring integrity and longevity of the product), to differentiation factors (i.e. extend battery life or reduce cost of cooling) to simply being more socially responsible. As a result, power management techniques, which were once only deployed for wireless applications, have now become ubiquitous. The vast majority of IC designers are now making a conscious effort to configure their RTL for efficient power partitioning and to reduce power consumption, in particular the dynamic component, which is increasingly becoming more dominant at advanced technology nodes.”  Of course experience by engineers has found that minimizing power is not easy.”  Guillaume continued: “The task is vast and far from being straight-forward. First, there is a multitude of techniques which are available to designers: Power gating, use of static and variable voltage domains, Dynamic Voltage and Frequency Scaling (DVFS), biasing, architectural tradeoffs, coarse and fine-grain clock gating, micro-architectural optimizations, memory management, and light sleep are only some examples. When you try combining all of these, you soon realize the permutations are endless. Second, those techniques cannot be applied blindly and can have serious implications during floor planning, timing convergence activities, supply distribution, Clock Tree Synthesis (CTS), Clock Domain Crossing management, Design For Test (DFT) or even software development.”

Low power considerations have also been at the forefront of IP designs.  Dr. Roddy Urquhart is Vice President of Marketing at Cortus, a licensor of controllers, noted that: “A major trend in the electronics industry now, is the emergence of connected intelligent devices implemented as systems-on-chip (SoC) – the ‘third wave’ of computational devices.  This wave consists of the use of locally connected smart sensors in vehicles, the emergence of “smart homes” and “smart buildings” and the growing Internet of Things.  The majority of these types of devices will be manufactured in large volumes, and will face stringent power constraints. While users may accept charging their smartphones on a daily basis, many sensor-based devices for industrial applications, environmental monitoring or smart metering rely on the battery to last months or even a number of years. Achieving this requires a focus on radically reducing power and a completely different design approach to the SoC design.”

Architectural Considerations

Successful power management starts at the architectural level.  Designers cannot decide on a tactic to conserve power once that system has already been designed, since power consumption is the result of architectural decisions aimed at meeting functional requirements.  These tradeoffs are made very early in the development of an IC.

Jon McDonald, Senior Technical Marketing Engineer, at Mentor Graphics noted that: “Power analysis needs to begin at the system level in order to fix a disconnect between the measurement of power and the decisions that affect power consumption. The current status quo forces architectural decisions and software development to typically occur many months before implementation-based power measurement feedback is available. We’ve been shooting in the dark too long.  The lack of visibility into the impact of decisions while they are being made incurs significant hidden costs for most hardware and software engineers. System engineers have no practical way of measuring the impact of their design decisions on the system power consumption. Accurate power information is usually not available until RTL implementation, and the bulk of power feedback is not available until the initial system prototypes are available.”

Patrick Sheridan, Senior Staff Product Marketing Manager, Solutions Group, at Synopsys went into more details.

“Typical questions that the architect can answer are:

1) How to partition the SoC application into fixed hardware accelerators and software executing on processors, determining the optimal number and type of each CPU, GPU, DSP and accelerator.

2) How to partition SoC components into a set of power domains to adjust voltage and frequency at runtime in order to save power when components are not needed.

3) How to confirm the expected performance/power curve for the optimal architecture.

To help expand industry adoption, the IEEE 1801 Working Group’s charter has been updated recently to include extending the current UPF low power specification for use in system level power modeling. A dedicated system level power sub-committee of the 1801 (UPF) Working Group has been formed, led by Synopsys, which includes good representation from system and power architects from the major platform providers. The intent is to extend the UPF language where necessary to support IP power modeling for use in energy aware system level design.”  But he pointed out that more is needed from the software developers.

“In addition, power efficiency continues to be a major product differentiator – and quality concern – for the software manager. Power management functions are distributed across firmware, operating system, and application software in a multi-layered framework, serving a wide variety of system components – from multicore CPUs to hard-disks, sensors, modems, and lights – each consuming power when activated. Bringing up and testing power management software is becoming a major bottleneck in the software development process.

Virtual prototypes for software development enable the early bring-up and test of power management software and enable power-aware software development, including the ability to:

- Quickly reveal fundamental problems such as a faulty regulation of clock and voltages

- Gain visibility for software developers, to make them aware of problems that will cause major changes in power consumption

- Simulate real world scenarios and systematically test corner cases for problems that would otherwise only be revealed in field operation

This enables software developers to understand the consequences of their software changes on power sooner, improving the user-experience and accelerating software development schedules.”

Drew Wingard, CTO, at Sonics also answered my question about the importance of architectural analysis of power consumption.

“All the research shows that the most effective place to do power optimization is at the architectural level where you can examine, at the time of design partitioning, what are the collections of components which need to be turned on or can afford to be turned off. Designers need to make power partitioning choices from a good understanding of both the architecture and the use cases they are trying to support on that architecture. They need tooling that combines the analysis models together in a way that allows them to make effective tradeoffs about partitioning versus design/verification cost versus power/energy use.”

Dr. Urquhart underscored the importance of architectural planning in the development of licensable IP.  “Most ‘third wave’ computational devices will involve a combination of sensors, wireless connectivity and digital control and data processing. Managing power will start at the system level identifying what parts of the device need to be always on or always listening and which parts can be switched off when not needed. Then individual subsystems need to be designed in a way that is power efficient.

A minimalist 32-bit core saves silicon area and in smaller geometries also helps reduce static power. In systems with more complex firmware the power consumed by memory is greater than the power in the processor core. Thus a processor core needs to have an efficient instruction set so that the size of the instruction memory is minimized. However, an overly complex instruction set would result in good code density but a large processor core. Thus overall system power efficiency depends on balancing power in the processor core and memory.”

Implementation Considerations

Although there is still a need for new and more powerful architectural tools for power planning, implementation tools that help designers deal with issues of power distribution and use are reaching maturity and can be counted as reliable tools by engineers.

Guillaume Boillet observed that: “Fine-grain sequential clock gating and removal of redundant memory accesses are techniques that are now mature enough for EDA tools to decide what modifications are best suited based on specific usage scenarios (simulation data). For these techniques, it is possible to generate optimized RTL automatically, while guaranteeing its equivalence vs. the original RTL, thanks to formal techniques. EDA tools can even prevent modifications that generate new unsynchronized crossings and ensure proper coding style provided that they have a reliable CDC and lint engine.”

Vic Kulkarni provided me with an answer based on sound an detailed technical theory that lead to the following: “There are over 20 techniques to reduce power consumption which must be employed during all the design phases from system level (Figure 1), RTL to gate level sign-off to model and analyze power consumption levels and provide methodologies to meet power budgets, at the same time do the balancing act of managing trade-offs associated with each technique that will be used throughout the design flow Unfortunately there is NO single silver bullet to reduce power!

Fig. 1. A holistic approach for low-power IP and IP-based SoC design from system to final sign-off with associated trade-offs [Source: ANSYS-Apache Design]

To successfully reduce power, increase signal bandwidth, and manage cost, it is essential to simultaneously optimize across the system, chip, package, and the board. As chips migrate to sub-20 nanometer (nm) process nodes and use stacked-die technologies, the ability to model and accurately predict the power/ground noise and its impact on ICs is critical for the success of advanced low-power designs and associated systems.

Design engineers must meet power budgets for a wide variety of operating conditions.  For example, a chip for a smart phone must be tested to ensure that it meets power budget requirements in standby, dormant, charging, and shutdown modes.  A comprehensive power budgeting solution is required to accurately analyze power values in numerous operating modes (or scenarios) while running all potential applications of the system.”

Jon McDonald described Mentor’s approach.  He highlighted the need for a feedback loop between architectural analysis and implementation. “Implementation optimizations focus on the most efficient power implementation of a specific architecture. This level of optimizations can find a localized minimum power usage, but are limited by their inability to make system-wide architectural trade-offs and run real world scenarios.

Software optimizations involve efforts by software designers to use the system hardware in the most power efficient manner. However, as the hardware is fixed there are significant limitations on the kinds of changes that can be made. Also, since the prototype is already available, completing the software becomes the limiting factor to completing the system. As well, software often has been developed before a prototype is available or is being reused from prior generations of a design. Going back and rewriting this software to optimize for power is generally not possible due to time constraints on completing the system integration.

Both of these areas of power optimization focus can be vastly improved by investing more in power analysis at the system level – before architectural decisions have been locked into an implementation. Modeling power as part of a transaction-level model provides quantitative feedback to design architects on the effect their decisions have on system power consumption. It also provides feedback to software developers regarding how efficiently they use the hardware platform. Finally, the data from the software execution on the platform can be used to refine the architectural choices made in the context of the actual software workloads.

Being able to optimize the system-level architecture with quantitative feedback tightly coupled to the workload (Figure 2) allows the impact of hardware and software decisions to be measured when those decisions are made. Thus, system-level power analysis exposes the effect of decisions on system wide power consumption, making them obvious and quantifiable to the hardware and software engineers.”

Figure 2. System Level Power Optimization (Courtesy of Mentor Graphics)

Drew Wingard of Sonics underscored the advantage of having in-depth knowledge of the dynamics of Network On Chip (NOC) use.

“Required levels of power savings, especially in battery-powered SOC devices, can be simplified by exploiting knowledge the on-chip network fabric inherently contains about the transactional state of the system and applying it to effective power management (Figure 3). Advanced on-chip networks provide the capability for hardware-controlled, safe shutdown of power domains without reliance on driver software probing the system. A hardware-controlled power management approach leveraging the on-chip network intelligence is superior to a software approach that potentially introduces race conditions and delays in power shut down.”

Figure 3.On-Chip Network Power Management (courtesy of Sonics)

“The on-chip network has the address decoders for the system, and therefore is the first component in the system to know the target when a transaction happens. The on-chip network provides early indication to the SOC Power Manager that a transaction needs to use a resource, for example, in a domain that’s currently not being clocked or completely powered off. The Power Manager reacts very quickly and recovers domains rapidly enough that designers can afford to set up components in a normally off state (Dark Silicon) where they are powered down until a transaction tries to access them.

Today’s SOC integration is already at levels where designers cannot afford to have power to all the transistors available at the same time because of leakage. SOC designers should view the concept of Dark Silicon as a practical opportunity to achieve the highest possible power savings. Employing the intelligence of on-chip networks for active power management, SOC designers can set up whole chip regions with the power normally off and then, transparently wake up these chip domains from the hardware.”


The Green movement should be proud of its success in underlying the importance of energy conservation.  Low Power designs, I am sure, was not one of its main objective, yet the vast majority of electronic circuits today are designed with the goal of minimizing power consumption.  All is possible, or nearly so, when consumers demand it and, importantly, are willing to pay for it.

Blog Review – Monday Sept. 22 2014

Monday, September 22nd, 2014

Intel Developer Forum urges us to snap to it; Software sustains its price and value; STEM – from girl to womanhood; ARM shares tools of the PSoC trade.
By Caroline Hayes, Senior Editor

Happy snapper, Agnes Kwan, Intel, reports on the RealSense snapshot intelligent camera system that can add dimensional information, such as “Just how high was that cliff I climbed?” Even better, it can blur features, or figures – Agnes suggests this is for photo-bombers, the curse of our self-indulgent digital age.

A constitution for the embedded designer is proposed by Rich Rejmaniak, Mentor Graphics. He points out that software development is one of life’s cold hard truths, like death and taxes, there are no shortcuts. He lays out a comprehensive set of rules to bear in mind to make life easier.

A very personal blog from Chris Wolfe, Ansys as she looks at women in engineering, pinpoints an often overlooked reason why girls are not taking part in STEM subjects – confidence. Not just academic but physical – this blog could double up as a social commentary. Although it raises many questions, there is not enough space in the blogsphere for all the answers.

In a generous gesture, Mark Saunders, ARM, shares a link to a Cypress PSoC 4 and PSoC 5LP ARM Cortex Code Optimization application note. He even points out why it is a good resource, covering as it does performance optimization and code size and its relevance to PSoC 5LP engineers.

Blog Review – Monday Sept. 15, 2014

Monday, September 15th, 2014

Video has a CAST of one; RTL clean-up as a simple chore; Detroit spins out roadmap; it’s all about ‘I’
By Caroline Hayes, Senior Editor.

The affable Warren Savage, IP eXtreme, opens a new season of five-minute chats and interviews CAST COO Nickos Zervas, who explains about the role of Greece and a duty to customers.

Using the analogy of the latest household gadget, Graham Bell, Vice President, Marketing, Real Intent, explains how the company’s autoformal tool, cleans up the RTL code in a design.

Invigorated from the Intelligent Transportation Society in Detroit John Day, Mentor Graphics steers his way through the road ahead for the automotive industry.

It sounds like the way to annoy Kris Flautner is to ask “What does the I in IoT stand for?” Apparently he is asked this a lot, but he patiently and clearly explains both the Internet’s role and also the challenges for connectivity and security, ahead of ARM TechCon 2014.

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