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Blog Review – Monday, November 16, 2015

Monday, November 16th, 2015

ARM TechCon 2015 highlights: IoT, mbed and magic; vehicle monitoring systems; the road ahead for automotive design

It’s crunch time for IoT, announced ARM CEO Simon Segars at ARM TechCon. Christine Young, Cadence reports on what Segars believes is needed to get the IoT right.

Posing as a ‘booth babe’, Richard Solomon, Synopsys, was also at ARM TechCon demonstrating the latest iteration of DesignWare IP for PCI Express 4.0. As usual, there are pictures illustrating some of the technology, this time around switch port IP and Gen2 PCI, and quirky pictures from the show floor, to give readers a flavor of the event.

Tracking the progress of mbed OS, Chris Ciufo, eecatalog, prowled the mbed Zone at this year’s ARM TechCon, finding IoT ‘firsts’ and updates of wearables.

Enchanted by IoT, Eric Gowland, ARM, found ARM TechCon full of wonder and magic – or, to paraphrase Arthur C Clark, technology that was indistinguishable from magic. There are some anecdotes from the event – words and pictures – of how companies are using the cloud and the IoT and inspiring the next generation of magicians.

Spotting where Zynq devices are used in booth displays, might become an interesting distraction when I am visiting some lesser shows in future. I got the idea from Steve Leibson, Xilinx, who happened upon the Micrium booth at ARM TechCon where one was being used, stopping to investigate, he found out about free μC/OS for Makers.

Back to Europe, where DVCon Europe was help in Munich, Germany (November 11-12). John Aynsley, Doulos, was pleased that UVM is alive and well and companies like Aldec are realising that help and support is needed.

Identifying the move from behavior-based driver monitoring systems to inward-looking, camera-based systems, John Day, Mentor Graphics, looks at what this will use of sensors will mean for automakers who want to combine value and safety features.
Deciding how many functions to offer will be increasingly important for automakers, he advises.

Still with the automotive industry, Tomvanvu, Atmel, addresses anyone designed for automotive embedded systems and looks at what is driving progression for the inevitable self-driving cars.

Caroline Hayes, Senior Editor

Blog Review – Monday, October 26, 2015

Monday, October 26th, 2015

Counting gates til the chickens come home to roost; Bio lab on a desk; Twin city goes digital; Back to the Future Day; Graphics SoC playground; Wearables get graphic

Something is troubling Michael Posner, Synopsys, when is a gate not a gate? He discusses the FPGA capacity of Xilinx’s UltraScale FPGAs and tries to find the answer. He also describes his Heath Robinson style light controlled chicken feeder he has installed in the chicken coop.

A desktop biolab sounds like something in a teenage boy’s room, but Amino is the ‘brainchild’ relates Atmel of Julie Legault. The Arduino-based bio-engineering system enables anyone to grow and take care of living cells. The mini lab allows the user to genetically transform an organism’s DNA through guided interactions. The Arduino-driven hardware monitors the resulting synthetic organism which needs to be fed nd kept warm. For those old enough to remember the Tamagotchi craze – it just moved up a gear.

3D computer models of buildings and cities take on a new role, demonstrated by Dassault Systèmes, whose 3DEXPERIENCity continuously generates the city as a digital twin city. Ingeborg Rocker explains how the IoT is used by the multi-dimensional data model which integrates population density, traffic density, weather, energy supply and recycling volumes data in real time to support city planners.

Recent acquisitions in the industry are analysed by Paul McLellan, Cadence Design Systems. Beginning with the acquisition of Carbon Design Systems by ARM, McLellan puts the deal in a market and engineering context. He moves on to the acquisition by Lam Research of KLA-Tencor and Western Digital which has bought SanDisk.

Putting the AMD R-Series through its paces, Christopher Hallinan, Mentor Graphics, delights in the versatility of the SoC, as discovered with Mentor Embedded Linux. He gives real-life examples of algorithms and how the visuals apply to industrial and scientific applications.

Celebrating a noteworthy date Back to the Future Day – October 21 2015 – Tobias Wilson-Bates, Georgia Tech, looks at how time travel has been portrayed in fiction. It gets philosophical: “One way to think about future speculations is to imagine that there are all these failed futures that co-exist with a present reality” but Marty would approve.

The acceptance of Mali-470 GPU to the wearables camp is complete. Dan Wilson, ARM, explains how the GPU is exploiting its OpenGL ES 2.0 graphics standard and power consumption for wearable and IoT applications.

Caroline Hayes, Senior Editor

Blog Review – Monday, September 28 2015

Monday, September 28th, 2015

ARM Smart Design competition winners; Nordic Semiconductor Global Tour details; Emulation alternative; Bloodhound and bridge-building drones; Imagination Summit in Taiwan; Monolithic 3D ‘game changer’; Cadence and collaboration; What size is wearable technology?

Winners of this year’s ARM Smart Product Design competition had no prior experience of using ARM tools, yet managed, in just three months to produce a sleep Apnea Observer app (by first prize winner, Clemente di Caprio), an amateur radio satellite finder, a water meter, an educational platform for IoT applications and a ‘CamBot’ camera-equipped robot, marvels, Brian Fuller, ARM.

This year’s Nordic Semiconductor Global Tech Tour will start next month, and John Leonard, ARM has details of how to register and more about this year’s focus – the nRF52 Series Bluetooth Smart SoC.

Offering an alternative to the ‘big box’ emulation model, Doug Amos, Aldec, explains FPGA-based emulation.

Justin Nescott, Ansys, has dug out some great stories from the world of technology, from the UK’s Bloodhound project and the sleek vehicle’s speed record attempt; and a story published by Giz Mag about how drones created a bridge – with video proof that it is walkable.

A review of the 2015 Imagination Summit in Taiwan earlier this month is provided by Vicky Hewlett. The report includes some photos from the event, of attendees and speakers at Hsinchu and Taipei.

It is with undeniable glee that Zvi Or-Bach, MonolithIC 3D announces that the company has been invited to a panel session titled: “Monolithic 3D: Will it Happen and if so…” at IEEE 3D-Test Workshop Oct. 9th, 2015. It is not all about the company, but a discussion of the technology challenge and the teaser of the unveiling of a ‘game changer’ technology.

A review of TSMC Open Innovation Platform (OIP) Ecosystem Forum, earlier this month, is presented in the blog by Christine Young, Cadence. There are some observations from Rick Cassidy, TSMC North America on Thursday, on automotive, IoT and foundry collaboration.

How big is wearable, ponders Ricardo Anguiano, Mentor Graphics. Unwrapping a development kit, he provides a link to Nucleus RTOS and wearable devices to help explain what’s wearable and what’s not.

A brief history of Calypto Design Systems, recently acquired by Mentor Graphics, is discussed by Graham Bell, RealIntent, and what the change of ownership means for existing partners.

Beginning a mini series of blogs about the HAPS-80 with ProtoCompiler, Michael Posner, Synospys, begins with a focus on the design flow and time constraints. He provides many helpful illustrations. (The run-on piece about a visit to the tech museum in Shanghai shows how he spends his free time: seeking out robots!)

Caroline Hayes, Senior Editor

Blog Review – Monday, September 14, 2015

Monday, September 14th, 2015

MonolithIC 3D identifies IoT drive; Trio advise Accellera Work Group on SoC definition; Shape-shifters on the catwalks; Weathering the storms of design challenges; IP subsystems ahead of OIP; AMD SoCs find their calling; Cadence keeps lines of communication open

Ahead of the IEEE S3S Conference, Zvi Or-Bach, MonolithIC 3D looks at the wafer demands for cheaper IoT development. His illustrated preview of some of the papers gives some insight into the discussions that lie ahead.

The clock is ticking for further technology contributions to the Accellera Portable Stimulus Working Group. Ahead of the deadline, September 16, Tom Fitzpatrick, Mentor Graphics, adds some background to the announcement that Mentor, Cadence and Breker have joined the group, offering portable test and stimulus expertise, in the definition of an SoC verification standard with IP and re-use opportunities.

Sportswear designer, Chromat, held its Spring/Summer 2016 runway show at MADE Fashion Week, with models wearing responsive garments that transform shape based on the wearer’s body temperature, adrenaline or stress levels. The experimental Adrenaline Dress, says Ayse Ildeniz, was powered by Intel’s Curie Module. There was also the Aeros Sports Bra which can respond to changes in perspiration, respiration and body temperature to adjust body temperature.

Design challenges that can make a real difference are highlighted by Brian Fuller, ARM, as he profiles the winning project in the inveneo solar power Micro Data Center Design Challenge 2015. The Micro Weather Station is explained inside and out and makes fascinating reading.

An interesting preview of his talk about the concept of IP subsystems at TSMC’s OIP (Open Innovation Platform) is given by Navraj Nandra, Synopsys. He uses examples of wearable and automotive technology to show the role of the foundry, as well as design and integration challenges.

Trying to figure out where the smart set goes if it’s not into a smartphone, automotive design or consumer device, Chris Ciufo, eecatalog, champions the power of AMD’s G-Series SoCs for “everything else”, especially thin client computer and some arresting digital signage.

All relationships rely on good communication, so Christine Young, Cadence, explains how to simplify the design flow between schematic and layout engineers. Instead of checking versions, she recommends some of the sound advice given by Karim Khalfan, director of application engineering at ClioSoft.

Caroline Hayes, Senior Editor

Blog Review – Monday, August 31, 2015

Monday, August 31st, 2015

HPC for cancer analysis; body power: game on for animation; DDR challenges; aviation fascination; packaging checks; Arrow explains USB3.1; IDF meets IoT

It would take 5.6Exabytes to synchronize the data of the 14million cancer patients worldwide, just once, points out Kristina Kermanshahche, Intel. She explains how Intel’s HPC is a helping scientist access and share data, with relationships such as Pan-Cancer Analysis of Whole Genomes, and at the German Cancer Research Centre (DKFZ) and the European Molecular Biology Laboratory (EMBL).

Distasteful things like a body’s sweat could charge phones, speculates Catherine Blogar, Dassault Sytemes. She speaks to some experts in wearable and implantable engineering for some futuristic power advice.

Some helpful tips on creating animation is offered by Laura Mengot, ARM, in her blog. Although the software used is Autodesk Maya and Unity, Mengot says that the detailed, illustrated theories are applicable to any 3D engine and game engine.

Ely Tsern, Rambus, identifies five trends in server memory and speculates on DDR4 capability in particular, and even beyond to DDR5.

Welcoming the RTCA/DO-254 (Design Assurance Guidance For Airborne Electronic Hardware) standard, Graham Bell, Real Intent, delves into what it means for verification tools.

Reminiscing about a European design classic, Nazita Save, Mentor Graphics, remembers Concorde. Pre-CAD modification and with no CFD software, how did they do it?

While end users may love smaller package sizes, they are a headache for manufacturers. IC Packaging Pros, Cadence, discuss layout tools for validating and verifying, with some easy-to-follow advice.

Four bloggers contribute to the latest update to USB3.0. Anand Shirahatti, Thejus Shanbhogue, Kanak Singh, Deepak Nagaria, Arrow, discuss the implementation and verification challenges – with a link to a USB3.0 vs USB3.1 USB cheat sheet thrown in.

Richard Solomon appears confused as to what day it is, but makes up for it with a round up of what’s what at this year’s IDF, from characters encountered, travel tips to his own takeaways from this month’s event in San Francisco.

Blog Review – Tuesday, August 18, 2015

Monday, August 17th, 2015

Where will the future of embedded software lead; Manufacturing success; DDR memory IP – a personal view; Untangling the IoT protocols; The battle of virtual prototyping; Accellera SI update; Smart buildings; SoC crisis management

The rise of phones, GPS, tablets and cars means embedded software increases in complexity, muses Colin Walls, Mentor Graphics. He traces the route of hardware and software in simple systems to ones that have to work harder and smarter.

Managing to avoid sounding smug, Falan Yinug reports on the SIA (Semiconductor Industry Association) paper confirming the semiconductor industry is the USA’s most innovative manufacturing industry, and looks at its role in the economy.

Less about being a woman in technology and more about the nitty gritty of DDR controller memory IP, Anne Hughes, DDR IP Engineering, Cadence talks to Christine Young.

Fitting protocols like CoAp and IPSO smart objects in the IoT structure can be daunting, but Pratulsharma, ARM, has written an illustrated blog that can lead readers through the wilderness.

Clearly taken with the Battlebots TV show, Tom De Schutter, Synopsys, considers how to minimise design risks to avoid destruction, or at least behave as intended.

A considered view of the Accellera Sytems Initiative is given by Gabe Moretti, Chip Design Magazine. He elaborates on what the UVM standardization will mean for the wider EDA industry.

Where the IoT is used, and how, for smart buildings, is examined by Rob Sheppard, Intel.

Alarming in his honesty, Gadge Panesar, Ultrasoc, says no-one know how SoCs operate and urges others to be as honest as he is and seek help – with some analytics and IP independence.

Blog Review – Monday, July 27 2015

Monday, July 27th, 2015

IoT for ADAS; ESC 2015 focuses on security; untangling neural networks; what drives new tools; consolidation conundrum; IoT growth forecast; three ages of FPGA

Likening a business collaboration to a road trip may be stretching a metaphor that would make Jack Kerouac blush, but David McKinney, Intel, presses on as he explains Intel and QNX’s ADAS solution, based on Intel IoT for automobiles. He includes some interesting links and a video to inform the reader.

A review of ESC 2015 shows that Chris Ciufo is not only ahead of the curve, advocating embedded security, but also not one to pass by a freebie at a show. He relates some of the highlights from the first day of the Santa Clara event.

Neural network processors hold promise for computer vision, believes Jeff Bier, BDTI. His blog explains what work is needed for the scale of computation the industry expects.

Posing an interesting question, Carey Robertson, Mentor Graphics, asks what prompts the development of new tools. He blends this with helpful information about the newly launched Calibre xACT extraction tool, without too much “hard sell”.

“It works!” is the triumphant message of the blog co-authored by Jacek Duda and Steve Brown, Cadence. Reporting from this month’s workshop where Type-C USB was put through its paces.

What to do with wireless IP is asked and answered by Navari Nandra, Synopsys. He explains what can be done and how it can contribute to the IoT.

The SoC market is consolidating fast, says Rupert Baines, UltraSoC, on an IP Exteme blog. This poses two challenges that he believes licensed IP can simplify.

A common proposition is to move from Intel to ARM, and Rich Nass, ARM presents a well-rounded blog on how to make the transition, with some input from WinSystems hardware and software experts.

Forget consumer, the future of the IoT growth is in enterprise, reports Brian Fuller, ARM, observing analyst IDC’s webinar on which parts of the IoT will be lucrative and why.

Recalling the talk by Xilinx Fellow, Dr. Steve Trimberger, Steve Leibson, explains the three ages of the FPGA, with a link to a video on the history of the technology.

Caroline Hayes, Senior Editor

Blog Review – Monday July 13, 2015

Monday, July 13th, 2015

Gary Smith, remembered; ARM Micro:bit collaboration begins; IoT friend or foe; ITA tariff call; Russia recognises Indian American scientist’s IGBT contribution; DDR4-3D DIMMs uncovered

A popular man, who came to be Mr EDA, Gary Smith, is remembered by Graham Bell, Real Intent. Gary passed away peacefully after a short illness, aged 74 earlier this month. Graham remembers his early career, some personal milestones and his route to his eponymous EDA consultancy and much affection from fellow engineers, journalists and others who met him.

The long-awaited BBC Micro:bit initiative between ARM and the BBC has been finalised. Gary Atkinson, ARM details the educational, inspirational project, and includes a short video.

We all know the IoT, but should it be viewed as a friend or foe, asks Alyssa, Dassault Systemes. Her blog includes advice on how to spot the difference.

Advocating a final program for the Information Technology Agreement (ITA), John Neuffer, SIA, offers consul on a tariff-elimination staging plan, to boost semiconductor sales.

It takes all sorts, as my gran used to say, but this variation is rarely celebrated. Nazita Saye, Mentor Graphics, celebrates the award of Russia’s top technology award to an Indian American scientist, B Jayant Baliga, for his work on IGBTs in the 1980s – better late than never.

You can hear the rustle of datasheets, reading Marc Greenberg’s blog, Synopsys. He delves into the Samsung DDR4-3D stacked DIMMs, using TSVs. He takes an engineer’s (rather than marketing) approach, seeking out these treasures and some sound advice on why it matters.

Caroline Hayes, Senior Editor

Blog Review – Monday, June 22 2015

Monday, June 22nd, 2015

Yonsei Uni team up for 5G; Hold that thought; now catch it; ARM and UNICEF; Industry and Education breathe life into EDA; Connected driving clears the road ahead

Researchers at Yonsei University have demonstrated a real-time, full-duplex LTE radio system at IEEE Globecom in Austin, Texas, using a novel antenna approach and working with National Instruments SDR platforms and LabVIEW graphical programming environment, reports Steve Leibson, Xilinx.

“Hold that thought” takes a new turn, as an anonymous blogger at Atmel describes the MYLE TAP, a wearable ‘thought catcher’. The touch-activate and voice-powered device automatically converts thoughts into actions. An interesting prototype or a recipe for disaster if it falls into the wrong hands?

Charity doesn’t always begin at home, sometimes it’s a warehouse in Copenhagen, Denmark. Dominic Vergine, ARM, visited the UNICEF global procurement hub and considers what wearable technology can provide, building on the low-tech, wearable technology of the MUAC band to test for malnutrition.

Building on a presentation at DAC 2015, Richard Goering, Cadence, considers how to academia and industry can work together to revitalize EDA.

The road ahead is smooth for the connected car, reports John Day, Mentor Graphics, if you are driving a Jaguar Land Rover (JLR), anyway. He examines the connected car technology that can identify and share data on potholes, broken manholes and other hazards.

Sloth is a deadly sin, especially in IP software development, warns Tom De Schutter, Synopsys, as he examines how laze in automotive testing can be absolved with virtual prototypes as an alternative to hardware, making earlier, broader, more automated software testing available.

Caroline Hayes, Senior Editor

Power shift reflects the need for a new way of thinking

Monday, June 15th, 2015

Handheld and smart devices are driving a methodology shift in power analysis, writes Caroline Hayes. Mentor Graphics has recognised the need to calculate power values earlier in the design cycle, and has introduced the Veloce Power Application software to its portfolio to help SoC designers shave time off development and testing.

There is an increase in switching power for logic and memory, observes Vijay Chobisa, Product Marketing Manager, Mentor Graphics, which is increasing dynamic power demands. This can lead to problems, such as the same chip overheating when used in difference phones and applications, due to ‘environment discrepancies’.

Vijay Chobisa, Product Marketing Manager, Mentor Graphics

As mobile devices are used for gaming, GPS and streaming video applications, the power consumption has to be adequate to allow for high-end applications, such as high resolution videos to run. According to Chobisa, there is a wrong way and a right way to design an SoC’s power analysis to ensure it is up to the task.

“A functional test bench is not appropriate for power,” he says, explaining how a functional test bench can be used to calculate power, using extrapolation technology to find the power for an SoC. The problem is that it shows the power peak early in the test. “Run an OS (Android, Linux or Windows) in live mode, and the real power is in a different location,” he continues. Not only that, but the power peak is much higher than the test bench. Yet, today’s applications need the performance capability to run 100 to 200 million cycles, allowing system design engineers to see the power problems.

The Power Application is part of Mentor Graphics ecosystem of hardware, Double Maximus and Quattro

What is the alternative? “Emulation is not right, either,” says Chobisa, due to the visibility it affords. “Visibility is needed for all design modes,” he says “-that, and scalability”. Simulation is not the solution either, as it does not have the speed capability for 100 to 200 million cycles, confirms Chobisa.

This leads to Veloce Power Application, introduced just before DAC. It runs on Veloce OS and which adds an activity plot, to reflect a real switching scenario, and a Dynamic Read Waveform API (Application Program Interface) to the existing UPF (Unified Power Format) and SAIF (Switching Activity Interchange Format) applications. The Dynamic Read Waveform API replaces file-based analysis flow.

Another advantage, points out Chobisa, is that it has RTL and gate-level support. “The RTL support is early,” says Chobisa, “providing the power budget and trade-off early in the SoC design”. Referring to gate level support, Chobisa notes that this is later but gives more accurate power.The Power Application software runs emulations and generates activity and SAIF files. These files, together with a power library tool calculate the Watt of power consumed for an activity.

When the emulation is run, a FSDB (File System DataBase) is supplied to the power analysis tool. It is large enough to supply data on the activity for every clock and node in the design. This is a new flow, says Chobisa, explaining that it eliminates the file transfer and file creation and produces a significant improvement in speed.

Information from the Power Switching Activity Plot is transferred to power analysis tools, for a more accurate power calculation at the system level.

“Benchmark numbers show that it can read designs of 24 to 72 million cycles at a two to 4.25x improvement in speed,” he says, “reducing one month into one week”.The first Veloce Power Application ecosystem partner is ANSYS with PowerArtist.
The collaboration addresses energy-efficient IP and SoC designs. Integration with ANSYS PowerArtist is available to mutual customers on a limited basis. Full production release is scheduled for early Q4 2015.

Caroline Hayes, Senior Editor

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