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Blog Review – Monday, June 26, 2017

Monday, June 26th, 2017

This week, hot on the heels of DAC, a review of the Austin event; Intel administers a dose of precision medicine; Challenges for drivers; How to choose between a GPU or FPGA and a blockchain reaction for the IoT

DAC 2017 took place in Austin, Texas, and Paul MeLellan, Cadence Design Systems, was there and has collated a wide-ranging report, with day-by-day news, including bats and bagpipes from the 54 th incarnation of the event.

Writing from a very personal viewpoint, Bryce Olson, Intel, advocates precision medicine, and looks at Intel’s scalable reference architecture to speed up the research and answers in medical care.

Vehicle safety is critical, and Stephen Pateras, Mentor Graphics, looks at self-test and monitoring in autonomous cars, using the Tessent MissionMode architecture. He explains in a clear, detailed manner, the IC test capabilities and simulation for self-driving cars.

Still with vehicle design, Robert Vamosi, Synopsys, flags up the security hazards around the connected car as sensors proliferate and hackers ramp up their assaults. He advocates software security and the communication protection afforded by the IEEE 802.11p protocol.

A handy white paper is brought to our attention by Steve Leibson, Xilinx, for those deciding whether a GPU is better than an FPGA in cloud computing, machine leaning, video and image processing applications.

I learned a couple of things from Christine Young, Maxim Integrated this week. One is that there is a job title of ‘chief IoTologist’, the other was to put the term ‘blockchain’ into context for the IoT. She reports from the IoT World Conference about how blockchain, using advanced cryptography, provides a “tamper-proof distributed record of transactions” and how the IoT Alliance is occupied in developing a shared blockchain protocol as a common identifier to secure IoT products.

Starstruck John Blyler, looks at the reality behind the stardust and conducts an interview with Dr Clifford Johnson, physicist at University of Southern California and script adviser for the National Geographic Channel’s TV program, Genius, about Albert Einstein.

Blog Review – Monday, June 12, 2017

Monday, June 12th, 2017

This week, we find traffic systems for drones and answers to the questions ‘What’s the difference between safe and secure?’ and ‘Can you hear voice control calling?’

An interesting foray into semantics is conducted by Andrew Hopkins, ARM, as he looks at what makes a system secure and what makes a system safe and can the two adjectives be interchanged in terms of SoC design? (With a little plug for ARM at DAC later this month.)

It had to happen, a traffic system designed to restore order to the skies as commercial drones increase in number. Ken Kaplan, Intel, looks at what NASA scientists and technology leaders have come up with to make sense of the skies.

Voice control is ready to bring voice automation to the smart home, says Kjetil Holstad, Nordic Semiconductor. He highlights a fine line of voice-activation’s predecessors and looks to the future with context-awareness.

More word play, this time from Tom De Schutter, Synopsys, who discusses verification and validation and their role in prototyping.

Tackling two big announcements from Mentor Graphics, Mike Santarini, looks at the establishment of the outsourced assembly and test (OSAT) Alliance program, and the company’s Xpedition high-density advanced packaging (HDAP) flow. He educates without patronizing on why the latter in particular is good news for fabless companies and where it fits in the company’s suite of tools. He also manages to flag up technical sessions on the topic at next month’s DAC.

Reporting from IoT DevCon, Christine Young, Maxim Integrated, highlights the theme of security in a connected world. She reviews the presentation “Shifting the IoT Mindset from Security to Trust,” by Bill Diotte, CEO of Mocana, and In “Zero-Touch Device Onboarding for IoT,” by Jennifer Gilburg, director of strategy, Internet of Things Identity at Intel. She explores a lot of the pitfalls and perils with problem-solving.

Anticipating a revolution in transportation, Alyssa, Dassault Systemes, previews this week’s Movin’On in Montreal, Canada, with an interview with colleague and keynote speaker, Guillaume Gerondeau, Senior Director Transportation and Mobility Asia. He looks at how smart mobility will impact cities and how 3D virtual tools can make the changes accessible and acceptable.

Caroline Hayes, Senior Editor

Blog Review – Monday, May 22, 2017

Monday, May 22nd, 2017

This week’s collection looks at what’s needed for autonomous cars; Qt tackles flaky tests, Sonics seeks wonderment, and blogs for design advice

Just as drivers choose their cars to meet their needs, so driverless cars need an assortment of processors, argues Intel’s Kathy Winter. She likens the designer’s toolbox to a golf bag with something for every dilemma encountered.

Reporting from the bi-annual GENIVI meeting in Birmingham, England, Andrew Pattersen, Mentor Graphics, learns that big data ownership could be a bone of contention in the next business model for the automotive industry.

Autonomous automotive development requires a thorough understanding of a variety of protocols for automation, electronics control and software. Jaspreet Singh Gambhir, Synopsys, explains how verification offerings can accelerate design.

It is always fun to hear about design mishaps and Sudhir Sharma, ANSYS, entertains with some he has come across to explain why digital twins and physics-based simulation not only meets design objectives but can save costs and boost profitability.

Where’s the wonder?, wonders Randy Smith, Sonics, marveling at why more people were impressed at the Machine Learning Developers Conference as he learned about Wave Computing’s dataflow for deep learning.

Consistency is key for Frederik Gladhorn, Qt, as he investigates a metric infrastructure for what he calls flaky tests, which hamper a design’s progress, with some practical advice and examples.

Speaking directly to anyone struggling with multiple layer design, Parul Agarwal, Cadence Design Systems, has some thoughts and advice on how to use a multi-layer bus. The blog is illustrated with some useful images as a practical guide for anyone struggling with layer patterns.

Caroline Hayes, Senior Editor

Blog Review – Monday, April 24, 2017

Monday, April 24th, 2017

This week’s blogs are concerned with AI and intelligent, connected vehicles, sometimes both. There are quests to find the facts behind myths and searches for answers for power management and software security too.

Is an effective tool for verification, the stuff of legends? Gabe Moretti, Chip Design Magazine, seeks the truth behind Pegasus – no, not the winged horse, the more earthly verification engine from Cadence.

A power strategy is one thing, but a free trial adds a new dimension to energy management. Don Dingee, Sonics, elaborates on the company’s plan to bring power to the masses, using hardware IP and ICE-Grain Power architecture.

If you are unsure about USB, Senad Lomigora, ON Semiconductor’s blog should help. It looks at what it’s for, why we can’t get enough of USB Type C, USB 3.1, connectors and re-drivers.

Every vehicle’s ADAS relies on good visuals, observes Jim Harrison, guest blogger, Maxim Integrated, and good connectivity. He looks at the securely connected autonomous car, and then homes in on explained how Maxim Integrated exploits GMSL, an alternative to Ethernet, in its MAX96707 and MAX96708 chips, to create an effective in-car communication network.

Still with the connected car, Pete Decher, Mentor Graphics, is fresh from the Autotech Council meeting in San Jose. The company’s DRS360 Autonomous Driving Platform launch was high on the list of discussion topics, along with the role of artificial intelligence (AI) in the future of driving.

Still with AI, Evens Pan, ARM provides an in-depth blog on Chinese start-up, Peceptin’s enabled embedded deep learning. The case study is fascinating and well reported in this comprehensive essay.

Making any software engineer feel insecure about software security is an everyday occurrence, helping them out is a little more out-of-the-ordinary, so if it refreshing to see a post from the editorial team, Synopsys, letting the put-upon software engineer know there is a webinar coming soon (May 2) to enlighten them on the Building Security In Maturity Model (BSIMM), with a link to register to attend.

Caroline Hayes, Senior Editor

Blog Review – Monday, April 10, 2017

Monday, April 10th, 2017

This week, there are traps and lures in the IoT, as discussed by ARM and Maxim Integrated; Xilinx believes a video tutorial is a good use of time; Get cosy with SNUG for some insight; and ON Semiconductor is keeping an eye on you

Beware of delivery men bearing IoT gifts, warns, Donnie Garcia, ARM, who also looks at trap doors and NXP’s Kinetis KBOOT bootloader to foil a new attack vector and advertise a related webinar on April 25.

Nagging parents had the right idea, decides Russ Klein, Mentor Graphics, remembering entreaties to turn off lights, and whose energy saving advice he now applies to SoCs and embedded systems, with the help of the Veloce emulator.

Gabe Moretti, Chip Design, gets a bit saucy, trying to figure just what is Portable Stimulus. He gets down to the nitty gritty with how the Accellera System Initiative can help, but still believes some areas need to attended to. Let’s hope the industry pays heed.

More warnings from Kris Ardis, Maxim Integrated, and connected devices. While a Jacquard print may not be to everyone’s taste, the idea of protecting the IoT and its data has universal appeal.

The appeal of Agile design is not lost on Randy Smith, Sonics, who writes about the concept and Agile software development. He deftly dives into advances in Agile hardware design and IC methodology for Agile techniques – keeping every design engineer on their toes.

A visit to ISC West, the security expo, has made Jason Liu, ON Semiconductor, think about surveillance systems, as he throws a spotlight on one of the company’s introductions.

14 minutes does not sound like a long time to pack in all you need to know about Zynq UltraScale+ MPSoCs and Vivado Design Suite, but Steve Leibson, Xilinx points readers towards an interesting, informative video, which he describes as a fast and painless way to see the development tools used in a fully operation system.

It sounds like a self-satisfied neck-warmer, but SNUG (Synopsys User Group) events can be informative. Tom De Schutter attended the one in Silicon Valley and relates what he learned from the technical track with experts from ARM, NVIDIA, Intel and Synopsys about prototyping latch-based designs, ARM CPU and GPU increasing densities and more besides.

Striving to improve the lot of IoT designers, John Blyler, Embedded Systems, talks to Jim Bruister, SOC Solutions, about markets, licensing, open source and five elements that will drive improvement.

Compiled by Caroline Hayes, Senior Editor

Blog Review – Monday, March 27, 2017

Monday, March 27th, 2017

How AI can be used for medical breakthroughs; What’s wired and what’s not; A new compiler from ARM targets functional safety; Industry 4.0 update

A personal history lesson from Paul McLellan, Cadence Design Systems, as he charts the evolution from the beginning of the company, via the author’s career and various milestones with different companies and the trials of DAC over the decades.

Post Embedded World, ARM announced the ARM Compiler 6. Tony Smith, ARM, looks at its role for functional safety and autonomous vehicles.

A review of industrial IoT at Embedded World 2017 is the focus for Andrew Patterson’s blog. Mentor Graphics had several demonstrations for Industry 4.0. He explains the nature of Industry 4.0 and where it is going, the role of OPC-UA (Open Platform Communication – Unified Architecture) and support from Mentor.

What’s wired and what’s wireless, asks David Andeen, Maxim Integrated. His blog looks at vehicle sub-systems and wired communications standards, building automation and wired interface design and a link to an informative tutorial.

There are few philosophical questions posed in the blogs that I review, but this week throws up an interesting one from Philippe Laufer, Dassault Systemes. The quandary is does science drive design, or does design drive science? Topically posted ahead of the Age of Experience event in Milan next month, the answer relies on size and data storage, influenced by both design and science.

Security issues for medical devices are considered by David West, Icon Labs. He looks at the threats and security requirements that engineers must consider.

A worthy competition is announced on the Intel blog – the Artificial Intelligence Kaggle competition to combat cervical cancer. Focused on screening, the competition with MobileODT, using its optical diagnostic devices and software, challenges Kagglers to develop an algorithm that classifies a cervix type, for referrals for treatment. The first prize is $50,000 and there is a $20,000 prize for best Intel tools usage. “We aim to challenge developers, data scientists and students to develop AI algorithms to help solve real-world challenges in industries including medical and health care,” said Doug Fisher, senior vice president and general manager of the Software and Services Group at Intel.

Caroline Hayes, Senior Editor

Determining a Fair Royalty Value for IP

Monday, March 13th, 2017

Gabe Moretti, Senior Editor

The legal case between Apple and Qualcomm made me ask: “What is a fair royalty a supplier can charge a user?”  The answer is not clear, since the product that uses the IP can benefit in many different way from the IP.  I asked a few questions to exponents of the IP business and I received answers that, even if they do not provide one solution, clear the issue significantly.

In this article I will cover answers from Robert (Bob) Smith, executive director of the ESD Alliance, Warren Savage, general manager of IP at Silvaco, Farzad Zarrinfar, Managing Director of Novelics, Mentor Graphics, and Grant Pierce, CEO of Sonics and also Chairman of the Board of the ESD Alliance.

I am publishing Grant’s response as a separate article with the title: “Behold the Intrinsic Value of IP “.

It must be noted that the ESD Alliance has launched a project called “IP Fingerprinting Initiative” using technology from Silvaco.

Chip Design (CD): Should royalties be fixed at a certain amount regardless of the sale price of the unit that use the licensed IP? Or, should royalties be a percentage of the price charged to the customer of the end product?

Robert Smith (RS): Royalties should be based on value provided. Value comes in many forms, such as how much of the functionality of the end product is provided by the IP, the risk and time-to-market reduction, and design and verification cost savings. There is no simple formula for IP royalties. In fact, they can be quite complicated.

Warren Savage (WS): Business models used for licensing royalties are ALWAYS a negotiation between the buyer and seller with each party striving to optimize the best outcome for their business. In some cases, the customer may be willing to pay more for royalties in exchange for lowering the upfront licensing costs. A different customer may be willing to invest more upfront to drive down the cost of royalties. Calculation of the actual royalty amounts may be based on a percentage of the unit cost or a fixed price, and each may have sliding scales based on cumulative volumes. Both parties need to derive the value that fits their own business model. The IP user needs to arrive at a price for the IP that supports the ROI model for the end product. The IP supplier needs to ensure that it receives sufficient value to offset its investment in IP development, verification and support. It is able then to participate in the success of the buyer’s product based (at least in part) on the value of the IP provided.

Farzad Zarrinfar (FZ): No. It will not be practical.  Royalty is a form of payment for IP licensing. Using royalty-based payment, IP providers can share the business risk and rewards with IP users.  Royalty is typically “negotiable” and is dependent to a variety of parameters such estimated volume, estimated product life, IP value, the amount of R&D invested in IP development, the business model for IP suppliers, competitive landscape for IP, and others. In reality, good relationships between IP users and IP providers are important in developing a win-win business model.  IP royalty is negotiable. However, some of the most utilized models are:

  • Royalty fee, as a percentage of end product selling price (i.e. the selling price of packaged IC)
  • Royalty fee, as a percentage of end-product cost (i.e. die cost)
  • Royalty fee, as a percentage of wafer revenue that the foundry generates
  • Royalty fee, as a portion of cost saving that IP providers offer to IP users.

CD: What is the intrinsic value of an IP?

WS: An IP has ZERO intrinsic value in of itself. The value is completely dependent on the application in which it is used, the ability of the IP to offset development costs and risks and the contributions it makes to the operation and success of the target product. For example, an IP that is developed and ends up sitting on the shelf has no value at all. In fact, its value is negative given the resources and costs spent on developing it. Size doesn’t matter. An IP that has hundreds of thousands of gates may command a higher price because the IP supplier needs to sell it for that price to recoup its investment in creating it.  A small IP block may also command a high price because it may contain technology that is extremely valuable to the customer’s product and differentiates it significantly from the competition. The best way to think about intrinsic value is to think of it in the context of value delivered to the customer. If there is no apparent difference in this regard between an IP product from two or more suppliers, then the marketplace sets the price and the lowest cost supplier wins.

FZ: It depends from various situations such as;

The value could be related to the cost saving for IP user. In the slide below, several cost savings have been calculated.

The value could be related to the time-to-market saving or the saving for IP implementation. These will impact “build vs buy” decisions.


How many times can the owner of the IP charge for its use in the same system to the same customer?

WS: This again is a negotiation determined by the buyer and seller. As long as both parties receive what they perceive as fair value, there is no magic number.

FZ: If I understand your question correctly, the typical licensing model is “step-function” or “flat”. In step-function, IP providers offer a licensing fee for “First-Use”, “first-re use”, and “second re-use & beyond”. Therefore, the more designs customers do, proportionally, more IP builders generate revenue. In addition, royalty revenue for differentiated IPs offer scalable business for IP providers. Therefore, more successful and higher volume the chip supplier gets, will also benefit IP provider by royalty.

Royalty can be paid in several forms. Following are several popular royalty payments:

  • Per parts
  • Per wafer
  • Buy out
  • Buy down
  • Royalty with Cap
  • Royalty with step function

It is also important to structure a solid tracking system to track and verify the proper value of paid royalty. In this case, as President Ronald Reagan said “I trust you, but I need to be able to verify”.

CD: How can the owner of the IP protect it from illegal use by customers?[NVC1]

WS: This is the great problem we have in the IP industry today. Approximately 99% percent of IP is delivered to customers in source code form and IP companies rely on the good faith of their customers to use it within the scope of the license agreement. However, there is a fundamental problem. Engineers rarely know what the usage terms and restrictions of the agreement their company has with the IP supplier, so it is quite easy for a semiconductor company to be in violation—and not even know it. New technologies are coming into play, such as the IP fingerprinting scheme that the ESD Alliance is promoting. Fingerprinting is a “non-invasive” approach that protects both IP suppliers and their customers from “accidental reuse.”

RS: IP suppliers can utilize The Core Store (www.the-core-store.com) at no charge to showcase their products and register “fingerprints” of their technology. Semiconductor companies can use this registry to detect IP usage within their chips by means of “DNA analysis” software available through Silvaco.


[NVC1]Warren and Bob changed the question a bit.

Blog Review – Monday, February 27, 2017

Monday, February 27th, 2017

Intel and the IoT at Mobile World Congress; Hardware rally cry; Space race; UVM update; Keepng track of heritage with archaeological tools

It’s Mobile World Congress this week, in Barcelona, Spain (February 27 to March 2). Alison Challman, Intel, rounds up some of the IoT highlights at the show, encompassing automated driving, the smart city and smart and connected homes.

Putting some pep into hardware design, Dave Pursley, Cadence, advocates hardware designers adopt a higher level of abstraction and then synthesizing to RTL implementations via high-level synthesis to get happy.

Lamenting the slow pace of space electronics technology compared with commercial products, Ross Bannatyne, Vorago Technologies, reports on the company’s ARM Cortex-M0 MCU in the SpaceX Falcon 9, which headed for the International Space Station.

Reflecting on the development of UVM1.2, Tom Fitzpatrick, Mentor Graphics, charts the progress of the Universal Verification Methodology (UVM) and how the to tackle compatibility with earlier versions. More can be discussed at this week’s DVCon US at the company’s booth.

Exploring Android, using Qt tools is the topic explored by Laszlo Agocs, Qt, with example of how to develop Android TV Vulkan content. His blog is a guide to building a qtbase for Android, targeting the 64-bit architecture of the Tegra X1-based NVIDIA Shield TV, using QtGui, QtQuick modules.

Digital preservation captures physical, important sites, which may be at risk, or lost completely, through earthquakes, floods, the passage of time and human threats. Alyssa, Dassault Systemes, has found some examples by CyArk that is preserving sites and how virtual reality headsets can make the sites accessible.

Caroline Hayes, Senior Editor

Blog Review – Monday, February 13, 2017

Monday, February 13th, 2017

Among this week’s topics: two important announcements: the OpenFog Consortium and IEEE Standard for the Functional Verification Language e; a panel discusses the Internet and beyond; Mentor Graphics applies IoT to PCB design; FASTR accelerates the connected car and why USB is not as easy as 123

The importance of IP blocks is a given, but Rocke Acree, ON Semiconductor, explains how selection also has to consider technology and support tools. The company has collaborated with Hexius Semiconductor to qualify analog IP blocks to reduce design cycles and development time.

There are specific constraints, challenges and design requirements for PCBs designed for the burgeoning IoT market. John McMillan, Mentor Graphics has created a two-part blog focused on this topic.

Doing a quickstep around the topic of USB, Eric Huang, Synopsys, explores verification and FPGA prototyping for best results. He recommends some design rules, a test site, then curiously, throws in some political comment, a film review and dance-related jokes to end the blog.

It may not be an understatement by Rhonda Dirvin, ARM, to say that the day the OpenFog Consortium announced its reference architecture is the day we have all been waiting for. Hyperbole? Possibly not, as it defines how secure, interoperable products should be built – just what the connected world needs. She helpfully includes a link to the architecture, and a heads-up on a presentation at Mobile World Congress in Barcelona, Spain (Feb 27 to March 3).

If there is an award for Most Apt Acronym, the Future of Automotive Security Technology Research (FASTR) consortium, must be a contender. The uncredited Rambus blog reviews the brief history of the consortium, and discusses its recent manifesto, looking at why it is need for a secure, connected vehicle industry.

2017 begins with the publication of IEEE Std 1647 2016, the IEEE Standard for the Functional Verification Language e. of 2017. Efrat Shneydor, Cadence Design, looks at the enhancements which have been made and proficiently summarizes the highlights.

Generic connectivity is not enough – NASA has been designing, building and launching satellite systems with the goal of providing connectivity throughout the world. The concept and realities of the Internet of Space is the panel discussion topic, reported by John Blyler, Chip Design Magazine.

Caroline Hayes, Senior Editor

Blog Review – Monday, January 23, 2017

Monday, January 23rd, 2017

This week’s blogs show the human face of automated driving; and why energy should be taken seriously. There is lift-off for SpaceX to bring more satellite comms and a poetic turn, in the style of Rudyar Kipling’s classic poem.

There is a human element to automated driving, namely Human Machine Interface (HMI) and Jack Weast, Intel, uses his second blog post to examine how and why it can be used. He promises more in part three into the company’s research.

Energy is a serious business, says Grant Pierce, Sonics, and the electronics industry must shoulder some responsibility for power savings. The company, with Semico Research is conducting a survey and wants your help into understanding today’s and tomorrow’s power requirements.

Boosting the satellites to provide point-to-point communications, the SpaceX Falcon 9 rocket put the first 10 Iridium NEXT satellites into Low Earth Orbit (LEO), equipped with Xilinx space-grade Virtex-5QV FPGAs to implement the satellites’ On Board Processor (OBP) hardware. Steve Liebson, Xilinx, includes a link to a video describing the constellation and the launch.

Celebrating the relationship with Ericsson, Dassault Systèmes’ Olivier Ribet, looks at how the latter’s Networked Society will transform the way we interact with the world around us and meet technology challenges, such as 5G, IoT and the cloud.

Moving to 10nm and lower process geometries pushes the boundaries of FinFET and the custom layout flow and this means trouble ahead, warns Graham Etchells.

A touch of culture, with a poem “wot I wrote” by Keith Hanna, Mentor Graphics. He deftly tackles Computational Fluid Dynamics (CFD) as Rudyard Kipling might.

Image data and the mysteries of how to create, access and use a Qimage to greatest effect is detailed by Laszlo Agocs, Qt, with three case studies to illustrate what can be done.

A sharp video addressing the interconnect verification challenges is hosted by Nimrod Reiss. Cadence’s Corrie Callenbach has found and highlighted the video.

Caroline Hayes, senior editor

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