By Ed Sperling
Synopsys completed the acquisition of Extreme DA. Synopsys said the acquisition will extend its push into static timing analysis and multicore software development. Synopsys also said its USB 3.0 IP has more than 40 design wins. Sounds like we’re going to start seeing this stuff in real products soon.

eSilicon and MIPS have taped out a 28nm 1.5GHz three-processor cluster using GlobalFoundries’ 28nm SLP process. MIPS provided the RTL for its Coherent Processing System, while eSilicon performed the synthesis, timing-driven layout and optimization.

Sonics teamed up with Munich-based Lantiq to create the next-generation network for the digital home. This stuff is certainly getting easier and much, much faster. Remember what it was like to set up a home network 10 years ago?

X-FAB, the analog/mixed signal foundry, qualified Cadence’s physical verification system for all process nodes. The foundry works on geometries ranging 1 micron to 0.18 micron.

By Ed Sperling
Cadence won a deal with Taiwan-based Sunplus Technology, which has adopted Cadence’s TLM flow for its next-gen SoCs. Sunplus makes chips for TVs, set-top boxes and DVD players.

MIPS won a deal with Loongson Technology Corp.—a Beijing-based company formed through the Beijing Municipal Government, the Institute of Computing of the Chinese Academy of Sciences and the Loongson development team—to use its cores for everything from high-end computing, cloud servers to embedded applications in the industrial control, smart meter, automotive, GPS and mobile markets.

TSMC’s net sales were down slightly again in July—2.9% compared with June and 3.4% compared with July 2010. Of that amount, about 0.4% can be accounted for by Global Unichip, which is no longer included in TSMC’s numbers.

Processor sales appear to be booming. Intel declared a quarterly cash dividend of 21 cents per share. Given that Intel’s stock is trading at about $20 per share, that’s a hefty dividend.

By Ed Sperling
Ansys completed its $314 million cash acquisition of Apache, less than two months after it was announced. Ansys, whose strength is primarily in simulation software, should be particularly well positioned for 2.5D and 3D stacked die with Apache’s low-power modeling tools.

Cadence bounded way back last quarter, reporting Q2 revenues of $283 million compared to $227 million in Q2 of 2010, and net income of $27 million, down from $49 million in the same period last year. The net income/revenue discrepancy is partly due to a repurchase of debt. On a non-GAAP basis, net income was $32 million in Q2 vs. $18 million Q2 of 2010. The company expects revenues to grow to $280 million to $290 million this quarter.

Mentor Graphics’ embedded in-vehicle infotainment (IVI) platform is now in compliance with the GENIVI alliance, a collaboration between auto companies and the consumer electronics industry. The platform is available for both Intel’s Atom and ARM architectures.

LG Electronics has inked a deal to use Tensilica’s HiFi Audio DSP and its software codecs for HDTV. This is an interesting win, particularly from the standpoint of which companies didn’t get the contract.

Lauterbach has added debugger support for MIPS’ MK14K cores, which should help decrease debug time on SoCs using this version of MIPS processors. Lauterbach already supports a bunch of other MIPS processors.

By Ed Sperling
Apache Design Solutions was snapped up by Ansys, just three months after it announced plans to go public with a $75 million offering. The last EDA company to go public was Magma in 2001, which raised $63 million. Ansys has been focused on simulation software. Adding a power analysis component to its lineup should be quite interesting.

Synopsys rolled out reprogrammable non-volatile memory IP at 180nm process technologies. The NVM ranges from few-time programmable to multiple-time programmable, RFID and erasable programmable read-only memory.

AMIMON, the Israeli maker of wireless high-def chips, licensed MIPS’ M4K processor for its next generation transmitter and receiver chips.

Cadence donated its UVM World Web site to Accellera. The site was created in 2010 to serve as an open location for all UVM-related information.

By Ed Sperling
MIPS has positioned itself head-to-head with ARM in the Android world, adding yet another competitor. The other one is Intel’s Atom, of course. MIPS stake on this one involves a smartphone that passed the Android Compatibility Test Suite.

Moortec Semiconductor taped out its embedded temperature sensor IP using TSMC’s 40LP and 28HP processes and Synopsys’ custom design solution. Who says analog isn’t migrating down the process curve? Moortec is based in Plymouth, U.K. 8

TSMC’s net sales, which are a good indication of how the semiconductor industry is faring, were down 0.7% from April to May—basically flat—but they are still up 6.3% from last May, which was well into the recovery period. Revenue was up 12.2% in the same period compared with 2010.

GlobalFoundries, meanwhile, swapped out its top leadership team. Ajit Manocha will replace Doug Grose as acting CEO. James Norling will become executive chairman and Ibrahaim Ajami the vice chairman, while COO Chia Song Hwee—former CEO of Chartered Semiconductor, which was acquired by GlobalFoundries—will leave the company in August.

By Ed Sperling
Mentor Graphics boosted the capabilities of its Catapult high-level synthesis tool to support synthesis of transaction-level models. Catapult now works with Vista for virtual protyping and hardware implementation. This kind of capability at a high-level of abstraction is critical now that complex SoC designs include up to 100 million gates.

TSMC has adopted Apache’s power, thermal and stress analysis tools for its Reference Flow 12.0 and its Analog/Mixed Signal Reference Flow 2.0. This will be particularly important in 2.5D and 3D implementations, which TSMC says will begin showing up next year.

MIPS launched a rapid development program for Android applications running on the MIPS architecture. In this battle, numbers of apps are critical.MIPS also inked deals with Chinese apps developer Ingenic Semiconductor and Chinese fabless company Actions Semiconductor to collaborate on the next release of Android. And it inked a deal with Silicon Integrated Systems of Taiwan for an Android-based Internet TV platform.

Atrenta rolled out a new textbook on RTL design. This one may be long overdue, given the incredible complexity ahead.

On the financial front, Mentor reported its fiscal Q1 results, ended April 30, posting record revenues of $230 million, up from $180.6 million in the same period in 2010. The company posted a net loss of $2.4 million compared with a net loss of $23 million in 2010. The loss was attributed to non-cash charges from retiring convertible debt.

And Synopsys’s board authorized a stock buyback of up to $500 million. That should boost the share price, which has been hovering in the high end of the $20-to-$30 a share range for the past four months.

By Ed Sperling
Three of Carl Icahn’s nominees were elected to Mentor Graphics’ board of directors. The three new directors—Jose Maria Alapont, Gary Meyers and David Schechter—will now sit with the five other directors who will continue to serve on the board. Schechter is the managing director of Icahn Capital.

Cadence rolled out its OrCAD Capture Marketplace, which pulls together the PCB ecosystem into an online store and gives some background on the companies involved—something that may prove quite useful in a global market where one startup looks like another. Cadence also teamed up with TSMC for DFM services ranging from simulation models for litho-process checks to virtual CMP at 40nm and below. The goal is to detect CMP hotspots and fix them before tapeout.

Synopsys unveiled a dynamic resolution adaptation decoder for its ARC Sound processors aimed at the Chinese market. This is an interesting target market for Synopsys, and one that has huge potential. The decoder supports the Chinese National HD audio standard included in the Blu-ray spec. In addition, Synopsys received SATA-IO 6G certification for its host and device digital controllers.

MIPS has teamed up with Carbon Design Systems to create virtual platform models for MIPS cores. The move comes on the heels of another announcement involving MIPS licensing of Myriad Group’s virtual machine technology, which will be available to MIPS Android licensees. Myriad Group is based in Switzerland.

By Ed Sperling
Mentor Graphics sent a letter to shareholders urging them to ignore Carl Icahn’s proxy materials and pulling out all the stops in explaining Icahn’s underlying intentions and his nominees to the board of directors. The most interesting nominee in this group is Gary Meyers, former CEO of Synplicity. This one should keep you reading. Hold all calls.

Cadence swung solidly back into the black in Q1, reporting net income of $6 million on $266 million in revenue compared to a loss of $12 million in Q1 2010 on revenue of $222 million. CEO Lip-Bu Tan said demand was strong for products and services across all regions and that demand for the Verification Computing Platform was strong. Break out the champagne. Just don’t drive afterward. Cadence also rolled out the latest version of its Allegro PCB and IC packaging technology. This is version 16.5, by the way, so we figure it’s well tested.

Synopsys was touting the advances in its IC Compiler after one of its customers, HiSilicon, cut standby power consumption by up to 40% without affecting timing on blocks in a recently taped out design.

Sonics is distributing Synopsys‘ DDR memory controller IP, creating end-to-end memory subystems that use a NoC fabric and scheduler. This is an interesting move, and it will take on particular significance once the market turns to 2.5D stacking.

Tensilica’s audio IP core was awarded DTS Broadcast and Digital Media Player (DMP) certification, which is a big deal in the audio world. No other IP core vendors have it, which should say something. The certification is based on highly accurate pipeline-modeled instruction set simulation models of the audio DSPs. This should be coming to a home theater near you—assuming you actually get to spend time at home with a global semiconductor rebound now under way.

Witness the strong growth at MIPS. Q1 revenue was up 15% to $20 million, compared with $17.5 million in Q1 of 2010. Net income was $3.3 million vs. $3.1 million in 2010, reflecting an increase in R&D and marketing costs.
MIPS also announced that it now has the source code for Android 3.0, aka Honeycomb, which it is porting to the MIPS architecture.
The company also won a deal to provide SoCs to Taiwan’s ALi Corp. for the “triple play” market for voice, digital TV and broadband services.

By Ed Sperling
SoC ecosystems are changing. Quality and focus are replacing volumes of names as companies that fund them begin to narrow down which partners add the most value and which markets they need to target.

Establishing a ring of allies is nothing new, of course. IBM had its circle of most trusted software partners back in the 1970s when mainframes were the dominant computing platform, and Microsoft built its fortune on creating the longest list of applications developers in the PC industry—to the detriment of IBM’s OS/2 and various flavors of Unix. But in SoC development this kind of approach has been much less structured, in part because the relationship between companies was never as well defined and in part because disaggregation is, at least by historical standards, a relatively new phenomenon.

“What’s changed is that the ecosystem is not horizontal anymore,” said Art Swift, vice president of marketing at MIPS, which has been hiring experts from different segments such as networking and broadcast to understand which companies should be included in the new vertical push. “We’ve got a lot of spending around verticals right now. It’s about two to three times what it was two years ago, and last year it was up another 50%. We’re trying to understand how products are used and what is the software ecosystem that’s required. But it’s tied to a specific application. We’re no longer interested in the biggest and broadest ecosystem.”

That sentiment is being echoed across the semiconductor industry as companies begin to grapple with complexity and figure out what they do internally and what should be outsourced, either with IP or services.

“In the past the attitude was that you could integrate with our products if you want,” said Shay Benchorin, director of marketing for Mentor Graphics’ embedded software division. “That’s no longer the case. The question being asked now is how fast you can bring the customer to a full working system. It forces you to focus because you cannot do everything. The big realization for us has been that a horizontal solution won’t cut it anymore. The same thing is happening on the hardware side where silicon vendors now have to provide more software. And even inside the SoC the blocks are richer in content than they were in the past.”

He noted that the integration task is becoming much more difficult, which was the impetus for some recent bundling around Mentor’s Nucleus real-time OS. “From a consumer point of view this is good news. The price is going down as silicon integration increases. But the window of opportunity is shrinking.”

All the major EDA and IP companies are watching the same trend unfold. “At 28nm and below, we are no longer just looking at IP without a deep understanding of the process technology,” said Neil Hand, group director for product marketing in Cadence’s new business group. “There’s a whole chain of requirements and you need to make sure people can drive these requirements.”

Cadence has shifted its IP strategy away from relying on third parties because of that complexity. “It’s not practical working through these issues with an ecosystem,” Hand said. “Once you get away from the bleeding edge, you can go to an ecosystem approach. And we haven’t completely abandoned our open integration. But we are more selective. We have a second tier of partners that we use for collaborative development, but we also do a lot of stuff ourselves.”

Changes in 3D
The relationship between IP vendors and other companies is even fuzzier as the industry heads into 2.5D stacking using interposers and 3D stacking using through-silicon vias.

For one thing, the number of choices is skyrocketing. “Everyone is sourcing more IP,” said Ajay Lalwani, vice president of strategic sourcing at eSilicon. “The complexity is exploding and there’s no one-stop shop in IP. We’ve seen this in EDA tools where there is increasing specialization for analog, RF, and microprocessor core hardening. And we’ve seen it in the manufacturing supply chain. Over the course of the past 12 months we’ve added 20 new suppliers. Managing complexity is a big challenge, and that complexity means managing more ecosystem partners.”

The problem gets even worse in 2.5D and 3D, where there is the potential to fuse together almost any combination of chips and functionality, from analog to MEMS.

“We need to share knowledge about interfaces to make all of this work in 3D,” said Navraj Nandra, senior director of marketing for Synopsys’ DesignWare Analog and MSIP Solutions Group. “This changes the relationship. It literally requires a knowledge transfer through experts who can do the brokering translation between experts. There are few companies with expertise in various areas. We need people with modeling expertise and people who understand quality issues like thermal/electrical stress for 3D connections.”

The problem is that in a new field such as stacked die, there also needs to be a fair amount of experimentation. Companies learn from mistakes, but these are problems that are not easily outsourced. “It requires a lot of high touch with some very smart people,” Nandra said. “This expertise is not common, which is why we’re seeing middlemen in 3D. These are 3D experts working in startups. There are lots of people thinking about this on Sand Hill Road.”

Those experts may be necessary to overcome reluctance to share their corporate secrets, which will be essential in the development of new IP. By all accounts the amount of IP in designs is growing. Naveed Sherwani, president and CEO of Open-Silicon, said that last year the company was using five pieces of IP from two vendors in derivative chips. Now it is using 10 pieces of IP, valued at $5 million to $10 million.

“What we’re looking for is IP vendors who give more of a road map about what they’re doing,” Sherwani said. “Derivatives require planning. This is all becoming much more planning-oriented.”

Sherwani noted that Open-Silicon has always had an IP acquisition group, but now it requires much more work to ensure the IP will work in designs. The IP also is much more oriented toward vertical markets. “This is much more challenging at 28nm, though. There is more IP from different vendors using different nomenclatures, which means there is a higher chance of making a mistake.”

Conclusion
Ecosystems are certainly not going away, but they are maturing as the problems that need to be solved increase in complexity. That maturation puts more of a burden on all of the players in the ecosystems, and it means there will be a perpetual weeding out of those companies that don’t add real value to the companies that are at the center of that ecosystem and footing at least part of the cost of maintaining it.

People are only as good as their partners, and as those relationships become deeper the dependencies continue to grow. The growing consensus is that more companies will need better partners. The challenge is choosing your partners wisely.

By Pallab Chatterjee
The push toward mobility in consumer devices is having an impact on the entire component flow.

Mobile devices are dominated by two key factors—an overriding power constraint and very high data bandwidth. The power constraints are on the mobile device side and on the cloud-based support server side. The high data bandwidth issues are due to the limited processing power available and the need to switch between functions, rather than keeping a common memory load and multiprocessing of the data.

The power side for the mobile devices has been discussed in depth. The impact on the rest of the system is less well known. Because mobile devices have to process data on a limited power budget, the support for these devices—the carrier and connection network, and the computing cloud that the device is connected to—has to pick up the slack on the processing front. New custom chipsets and processor architectures are being created to address some high-volume connection tasks such as display view transcoding, security processing and authentication, and sensor/imaging data processing. These chips are making their way into the network connectivity side with multicore being the dominant format for network processors. Also on the networking side, the addition of dedicated, power-optimized AES encryption/decryption blocks allow for secure data traffic on a per block basis with mobile devices.

Also on the power side is the change to high-bandwidth interfaces such as 10G, 40G (organized as 4 lanes of 10G), and 100G (organized as 4 lanes of 25G). While it would appear these interfaces consume more power, the reality is that when implemented in pairs, the lower duty cycle and larger packet size enable low power. For the 100G interfaces, the ability to implement the 25-28G lanes with 32nm and below CMOS offers huge power savings, as the PHY/MAC pairs actually consume less dynamic and active power than 10G lanes implemented in 40nm processes.

The data bandwidth is one of the keys behind the multicore architectures of both mobile devices and server designs. To optimally process data, database access, still images, video content, audio content, gaming graphics, and sensor data (touch screen, gyroscope, GPS, etc.), separate processing engines are usually employed. This is a key driver for multicore where the task base can be continually loaded, and only the data sets get changed. In order to handle the diversity and volume of data sets to be processed, wide- and high-bandwidth data paths are needed. Servers have moved to deep memories architectures to support the cloud computing from smartphones and tablets.

Similarly, the data bandwidth of broadband and wireless are increasing. For broadband, there is a need to put more data per channel on existing lines. This is being done with new wide data architectures that support multiple lanes of SerDes driving the network. To handle the large variety of data that is being presented, new cross-point switch architectures as well as multicore internal bus architectures are changing. These new buses are both externally expandable and support individualized power and data management for each core on the bus.

These different architectures are responsible for the division in use model of the various available cores. Tensilica cores tend to be used in audio processing applications, MIPS and Freescale cores are used in network transaction and security processing, ARM cores are used a generalized CPUs for mobile devices, x86 architectures dominate the main server side and specialty DSPs abound on sensor processing. As the data consumption systems moves to being more mobile-centric, the whole ecosystem from servers to delivery is now shifting to a true ultra-thin client computing model.