By Ed Sperling
SoC ecosystems are changing. Quality and focus are replacing volumes of names as companies that fund them begin to narrow down which partners add the most value and which markets they need to target.

Establishing a ring of allies is nothing new, of course. IBM had its circle of most trusted software partners back in the 1970s when mainframes were the dominant computing platform, and Microsoft built its fortune on creating the longest list of applications developers in the PC industry—to the detriment of IBM’s OS/2 and various flavors of Unix. But in SoC development this kind of approach has been much less structured, in part because the relationship between companies was never as well defined and in part because disaggregation is, at least by historical standards, a relatively new phenomenon.

“What’s changed is that the ecosystem is not horizontal anymore,” said Art Swift, vice president of marketing at MIPS, which has been hiring experts from different segments such as networking and broadcast to understand which companies should be included in the new vertical push. “We’ve got a lot of spending around verticals right now. It’s about two to three times what it was two years ago, and last year it was up another 50%. We’re trying to understand how products are used and what is the software ecosystem that’s required. But it’s tied to a specific application. We’re no longer interested in the biggest and broadest ecosystem.”

That sentiment is being echoed across the semiconductor industry as companies begin to grapple with complexity and figure out what they do internally and what should be outsourced, either with IP or services.

“In the past the attitude was that you could integrate with our products if you want,” said Shay Benchorin, director of marketing for Mentor Graphics’ embedded software division. “That’s no longer the case. The question being asked now is how fast you can bring the customer to a full working system. It forces you to focus because you cannot do everything. The big realization for us has been that a horizontal solution won’t cut it anymore. The same thing is happening on the hardware side where silicon vendors now have to provide more software. And even inside the SoC the blocks are richer in content than they were in the past.”

He noted that the integration task is becoming much more difficult, which was the impetus for some recent bundling around Mentor’s Nucleus real-time OS. “From a consumer point of view this is good news. The price is going down as silicon integration increases. But the window of opportunity is shrinking.”

All the major EDA and IP companies are watching the same trend unfold. “At 28nm and below, we are no longer just looking at IP without a deep understanding of the process technology,” said Neil Hand, group director for product marketing in Cadence’s new business group. “There’s a whole chain of requirements and you need to make sure people can drive these requirements.”

Cadence has shifted its IP strategy away from relying on third parties because of that complexity. “It’s not practical working through these issues with an ecosystem,” Hand said. “Once you get away from the bleeding edge, you can go to an ecosystem approach. And we haven’t completely abandoned our open integration. But we are more selective. We have a second tier of partners that we use for collaborative development, but we also do a lot of stuff ourselves.”

Changes in 3D
The relationship between IP vendors and other companies is even fuzzier as the industry heads into 2.5D stacking using interposers and 3D stacking using through-silicon vias.

For one thing, the number of choices is skyrocketing. “Everyone is sourcing more IP,” said Ajay Lalwani, vice president of strategic sourcing at eSilicon. “The complexity is exploding and there’s no one-stop shop in IP. We’ve seen this in EDA tools where there is increasing specialization for analog, RF, and microprocessor core hardening. And we’ve seen it in the manufacturing supply chain. Over the course of the past 12 months we’ve added 20 new suppliers. Managing complexity is a big challenge, and that complexity means managing more ecosystem partners.”

The problem gets even worse in 2.5D and 3D, where there is the potential to fuse together almost any combination of chips and functionality, from analog to MEMS.

“We need to share knowledge about interfaces to make all of this work in 3D,” said Navraj Nandra, senior director of marketing for Synopsys’ DesignWare Analog and MSIP Solutions Group. “This changes the relationship. It literally requires a knowledge transfer through experts who can do the brokering translation between experts. There are few companies with expertise in various areas. We need people with modeling expertise and people who understand quality issues like thermal/electrical stress for 3D connections.”

The problem is that in a new field such as stacked die, there also needs to be a fair amount of experimentation. Companies learn from mistakes, but these are problems that are not easily outsourced. “It requires a lot of high touch with some very smart people,” Nandra said. “This expertise is not common, which is why we’re seeing middlemen in 3D. These are 3D experts working in startups. There are lots of people thinking about this on Sand Hill Road.”

Those experts may be necessary to overcome reluctance to share their corporate secrets, which will be essential in the development of new IP. By all accounts the amount of IP in designs is growing. Naveed Sherwani, president and CEO of Open-Silicon, said that last year the company was using five pieces of IP from two vendors in derivative chips. Now it is using 10 pieces of IP, valued at $5 million to $10 million.

“What we’re looking for is IP vendors who give more of a road map about what they’re doing,” Sherwani said. “Derivatives require planning. This is all becoming much more planning-oriented.”

Sherwani noted that Open-Silicon has always had an IP acquisition group, but now it requires much more work to ensure the IP will work in designs. The IP also is much more oriented toward vertical markets. “This is much more challenging at 28nm, though. There is more IP from different vendors using different nomenclatures, which means there is a higher chance of making a mistake.”

Conclusion
Ecosystems are certainly not going away, but they are maturing as the problems that need to be solved increase in complexity. That maturation puts more of a burden on all of the players in the ecosystems, and it means there will be a perpetual weeding out of those companies that don’t add real value to the companies that are at the center of that ecosystem and footing at least part of the cost of maintaining it.

People are only as good as their partners, and as those relationships become deeper the dependencies continue to grow. The growing consensus is that more companies will need better partners. The challenge is choosing your partners wisely.

By Pallab Chatterjee
The push toward mobility in consumer devices is having an impact on the entire component flow.

Mobile devices are dominated by two key factors—an overriding power constraint and very high data bandwidth. The power constraints are on the mobile device side and on the cloud-based support server side. The high data bandwidth issues are due to the limited processing power available and the need to switch between functions, rather than keeping a common memory load and multiprocessing of the data.

The power side for the mobile devices has been discussed in depth. The impact on the rest of the system is less well known. Because mobile devices have to process data on a limited power budget, the support for these devices—the carrier and connection network, and the computing cloud that the device is connected to—has to pick up the slack on the processing front. New custom chipsets and processor architectures are being created to address some high-volume connection tasks such as display view transcoding, security processing and authentication, and sensor/imaging data processing. These chips are making their way into the network connectivity side with multicore being the dominant format for network processors. Also on the networking side, the addition of dedicated, power-optimized AES encryption/decryption blocks allow for secure data traffic on a per block basis with mobile devices.

Also on the power side is the change to high-bandwidth interfaces such as 10G, 40G (organized as 4 lanes of 10G), and 100G (organized as 4 lanes of 25G). While it would appear these interfaces consume more power, the reality is that when implemented in pairs, the lower duty cycle and larger packet size enable low power. For the 100G interfaces, the ability to implement the 25-28G lanes with 32nm and below CMOS offers huge power savings, as the PHY/MAC pairs actually consume less dynamic and active power than 10G lanes implemented in 40nm processes.

The data bandwidth is one of the keys behind the multicore architectures of both mobile devices and server designs. To optimally process data, database access, still images, video content, audio content, gaming graphics, and sensor data (touch screen, gyroscope, GPS, etc.), separate processing engines are usually employed. This is a key driver for multicore where the task base can be continually loaded, and only the data sets get changed. In order to handle the diversity and volume of data sets to be processed, wide- and high-bandwidth data paths are needed. Servers have moved to deep memories architectures to support the cloud computing from smartphones and tablets.

Similarly, the data bandwidth of broadband and wireless are increasing. For broadband, there is a need to put more data per channel on existing lines. This is being done with new wide data architectures that support multiple lanes of SerDes driving the network. To handle the large variety of data that is being presented, new cross-point switch architectures as well as multicore internal bus architectures are changing. These new buses are both externally expandable and support individualized power and data management for each core on the bus.

These different architectures are responsible for the division in use model of the various available cores. Tensilica cores tend to be used in audio processing applications, MIPS and Freescale cores are used in network transaction and security processing, ARM cores are used a generalized CPUs for mobile devices, x86 architectures dominate the main server side and specialty DSPs abound on sensor processing. As the data consumption systems moves to being more mobile-centric, the whole ecosystem from servers to delivery is now shifting to a true ultra-thin client computing model.

By Ed Sperling
Mentor Graphics rolled out a new Eldo Premier SPICE simulator that it claims will improve performance by 20x and capacity by 10x. Support for the Questa mixed-signal verification environment will be added in the near future.

Cadence rolled out its DDR4 IP solution, building on the acquisition of Denali last year. The solution includes hard and soft PHY, controller IP, memory models, verification IP, tools and methodologies, as well as reference designs.

eSilicon inked a deal with TranSwitch to manage the supply chain for Transwitch products and to collaborate on cost optimization of new products. The deal is similar to one that eSilicon signed with Pixim last summer.

MIPS launched a new developer community for software developers working with Android, Linux and other applications for MIPS-based hardware. MIPS also said that Broadlight’s third-generation gigabit passive optical network processor family will be powered by the MIPS 74K core.

By Ed Sperling
Mentor Graphics rejected Carl Icahn’s proposed $17 a share, saying it undervalues the company. When Cadence initiated its takeover attempt in 2008 Mentor said it examined the regulatory risks associated with the two companies that would be potential buyers—Cadence or Synopsys—and said those risks still exist. It also determined “that this is not the time to put the company up for sale.”
Mentor also introduced its 3D stacked die strategy for design, verification and testing and expanded its low-power verification capabilities in TSMC’s Reference Flow 11.

Prepping its own 2.5D and 3D commitment, Cadence rolled out a Wide I/O memory controller core and integration environment for tablets and smart phones. Included are traffic reordering and low-power features.

Synopsys introduced its DC Explorer for early RTL exploration—tools that also will be critical at advanced nodes and for 3D stacking. This is a big deal for complex designs, and something all of the major EDA companies are working on. In addition, the company said it has developed a broad portfolio of PHY IP with TSMC, with a focus on low power and small area. And Synopsys gave a first glimpse into its cloud initiative during a keynote speech by CEO Aart de Geus at the Synopsys User Group meeting.

MIPS unveiled plans for a 64-bit processor architecture with simultaneous multithreading technology. This is an interesting idea because widens the address space while adding cache coherency across the cores.

Tensilica also introduced a new IP core that targets dataplane and digital signal processing for imaging, communications and networking. This one is interesting for similar reasons—very long instruction word instructions and cache memory prefetching—and up to 1GHz clock frequency using the 45nm process. Data bandwidth will increase by four times over previous generations.

By Ed Sperling
With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected.

This is easier said than done, however, for a number of reasons:

1. There are numerous types of IP, ranging from I/O to logic and memory.
2. Not all IP is of equal quality.
3. Not all IP is used the way it was intended, or even consistently from one chip to the next.
4. Re-use within companies of their own IP frequently doesn’t conform to any standards.

So far, standards efforts in this area have been relatively modest. The SPIRIT consortium introduced IP-XACT to document IP and provide tools to access meta data, but that’s a far cry from a consistent methodology for integrating IP.

“In the old days all you had to do was characterize the IP,” said Jean-Marie Brunet, director of product marketing for model-based DFM and place-and-route integration at Mentor Graphics. “Now you try to create context with lithography and stress. You need to instantiate the IP in corner cases and the surrounding context. It’s random at this point, which means there is not a lot of predictability.”

That becomes even more critical at future nodes. At 20nm, for example, double patterning makes IP even harder to characterize and re-use. And fill at 28nm and 20nm can have an effect on density, which in turn affects min/max values. That also has an effect on IP.

“These are problems for the IP creator and the SoC integrator,” said Brunet. “You almost need a ring around every IP, but that blows the area. And double patterning is not done the same way from the IDM to the foundry, so you need a situational solution for each version.”

There also has to be a better way of defining what is good IP. A piece of IP that functions perfectly in one design may not function the same way in all designs because of issues ranging from noise—a problem that has been particularly acute for RF and some analog IP—to electromagnetic interference, physical stress and exactly how the IP is used.

“The big issues we’ve found is that different IP is being delivered in different states of readiness and quality with a different understanding of what it means to actually be IP,” said Neil Hand, group director for product marketing in Cadence’s new business group. “Today when you deliver IP you do some amount of generalized skeleton code, floor planning and I/O placement. But there is a lack of consistency in this.”

He noted that at 70% to 90% IP content in SoCs, any amount of overhead in making IP come together and work properly is unacceptable. “What’s needed is to unify the delivery of IP. After that, everything falls into place.”

Verifying quality
Behind that delivery is a need to have more consistent quality, which means the IP can be used under a variety of circumstances and still work as planned.

“Integration is an issue, but the bigger problem from a customer standpoint is to figure out which IP is good and which IP is not good,” said Gideon Intrater, vice president of marketing and applications at MIPS. “The risk is huge. What you’re looking for is IP that is isolated enough from the rest of the system. With sensitive analog or RF you still want to be able to drop it into the chip and have enough rules in place for using that IP. But you also have to consider that the more aggressive the process technology, the more IP you put in a chip and the more power and power rails, which are noise—all of that is going to impact how the IP behaves.”

IP certainly needs to be tested once it’s in a design, but it also needs to be tested and properly characterized well before that. Large IP vendors typically build reference designs using worst-case scenarios to test the limits of their products. With Synopsys’ DDR3 and DDR4, for example, the company has built the memory into what Navraj Nandra, Synopsys’ senior director of marketing for DesignWare analog and MSIP IP, calls “cheap and nasty packages.”

“What we don’t know is how the customer will implement IP inside an SoC,” Nandra said. “But there is a lot you can do to mitigate potential issues if you know what they are.”

The largest merchant IP vendors—ARM, Synopsys and MIPS—all use this method of testing all possible configurations and developing data sheets for problems that can erupt along the way. Jack Browne, senior vice president of sales and marketing at Sonics and a former executive at MIPS, said that once an IP company has more than 20 customers and has developed more than 5 to 10 products, it has figured out the quality issues. “As customers do their second and third transaction with an IP company, they’ve got the quality issues worked out on their side, too.”

Internally developed IP and most custom-built analog IP rarely have that kind of information available, however. And as companies attempt to move their existing IP to the next process node, or when they attempt to use the old methods of putting in IP blocks as it becomes available, problems can erupt that no one ever considered.

“The interconnect ends up being the sticky point in chips,” said Kurt Shuler, director of marketing at Arteris. “If you use Wide I/O to memory on a mobile phone you get better bandwidth, but the question that has to be answered is where you put everything. You need to floor plan all the IP blocks earlier. And often the people doing the interconnect and the people doing the IP don’t understand the IP inputs as well as they need to.”

Future directions
The question now is just how much IP will be sold pre-integrated as subsystems or even as complete die for use in 3D stacking.

“The methodologies for putting subsystems together and SoCs together are not all that different,” said Ajoy Bose, chairman and CEO of Atrenta. “There is some methodology in place today, even if it involves homegrown solutions and scripts. What’s more of a challenge is trying to fit your own ideas into an existing situation.”

That’s been the problem with commercial IP from the start. It’s possible to write IP specifically for an SoC design that is smaller in area, uses lower power and has no proximity issues because it is developed for a specific design. But getting the design out the door on time using internally developed IP is impossible.

“Right now you create IP, sign off on that IP, you import the IP, validate it in an SoC and hand it off to implementation,” said Bose. “This is similar to what the enterprise software industry was doing with analysis, human resources and inventory. Then enterprise applications were created to connect all the software together into a single integrated package. We’re seeing the same trend in IP with the subsystem becoming more popular. It helps that the semiconductor companies are aligning themselves vertically, too. With each vertical they know the pieces that are used.”

In many cases this job will fall to value-chain producers such as eSilicon, Open-Silicon and Global Unichip, which are among the largest commercial IP integrators and testers. Kalar Rajendiran, eSilicon’s senior director of marketing, said his company has developed a four-step methodology for selecting, managing, integrating and testing IP. What’s important in this process is an understanding of how that IP performs in chips over time and for multiple customers.

“The really heavy lifting is in selecting the IP,” he said. “Choosing IP suppliers is very important. Once we qualify the IP we document it in a database with version control. We also audit the supplier’s methodology—what they use to develop and verify that IP—and we do a site visit to the IP supplier to meet with them. We’ve been doing this for 10 years. We have proof points about why not to go with certain supplier. In some cases it’s because they cause problem for other industry players.”

At this point those kinds of capabilities are a competitive advantage and problems on the integration and testing of IP loom large for many companies. That may change as the IP industry continues to consolidate and tools become available, but at that point the problem also may be less about integration than on customization of IP for specific needs.

Carl Icahn stepped up pressure on Mentor Graphics, offering $17 per share in cash for all outstanding shares. Mentor’s stock was trading above $15 a share last week and the company was weighing its options.

The stock could show some pop on its own. Mentor reported that revenues were up 30% in Q4 vs. the same period in 2009 and earnings were up 10% on a GAAP basis. On a non-GAAP basis, earnings were up a whopping 60%. For the year, revenues were up 14% and GAAP earnings were 25 cents a share, vs. a 23-cent loss in 2009.

Mentor threw its weight behind UVM 1.0, which is no surprise. Aside from the benefits of a standards-based verification methodology, it’s also a good competitive strategy.

Synopsys rolled out data converter IP for SMIC’s 65nm low-leakage process. The IP is aimed at battery-powered communications and digital TV devices.

Cadence won a couple of deals. Broadcom is using Cadence’s Palladium XP acceleration and emulation technology. And IMS CHIPS, based in Stuttgart, Germany, standardized on Cadence’s silicon realization technology for mixed-signal gate arrays.

MIPS inked a deal to distribute the OEM version of Imperas’ Open Virtual Platforms simulator, aka OVPsim, which will allow customers to develop instruction-accurate simulation for MIPS processor cores.

By Ed Sperling
A growing reliance on third-party IP is beginning to expand well beyond just IP blocks and into full subsystems, opening significant growth opportunities for companies competing in this market as well as enormous business and technical challenges.

The IP market is ripe for this kind of convergence. Complexity at advanced process nodes coupled with time-to-market demands has elevated third-party IP from an emergency fix inside most designs to a necessity. By some reports IP now accounts for up to 90% of an SoC design. What’s changing is that IP increasingly is being integrated with other IP, software and even hard IP, so it can be plugged into an SoC with far fewer integration problems associated with single IP blocks.

“What’s driving this are the tablet and smart phone markets,” said Prasad Subramaniam, vice president of design technology at eSilicon. “Those are the highest growth markets, and companies like ARM and MIPS are creating blocks around their cores to harden and pre-verify. We’re even seeing this happening with entire reference designs, which include those subsystems. In the past this was just a reference design. But there are a lot of OEMs—especially Asian companies—that don’t have the resources to do these designs from scratch, so they’re picking up the design and fixing whatever is necessary to get to market quickly.”

James Mac Hale, vice president of Asia operations at Sonics, had a similar view: “We’ve seen SoCs move from integrating cores to subsystems. The number of cores is going up, and so is the complexity and desire for re-use. The challenge is that once you combine all these subsystems, how do you design the overall system behavior. Each reacts differently on its own.”

Getting a handle on the changes in this market is no simple task, in part because this trend is just beginning to take shape and in part because of the breadth of what’s happening. Even defining IP can lead to arguments about what is and is not considered commercial intellectual property. Adding more pieces into the mix only confuses the definition.

Synopsys, for one, defines IP subsystems based upon function. That definition includes the integration of one or more pieces of IP with the software stack running on top of it, all of which is configured for a specific application. That could be an audio-based subsystem with an ARC processor, the necessary codecs, interconnects for such things as a headset or speakers, or it could be a USB subsystem with the controller, PHY, a software stack on the USB, integration services and verification IP, according to John Koeter, vice president of marketing for IP and systems at Synopsys.

“The majority of IP is still going through traditional sales channels,” said Koeter. By our best estimates, about 5% of the IP market today is made up of IP subsystems. Over the next three years we expect that to double or triple.”

Exactly what those subsystems evolve into, however, is anyone’s guess. “One way to look at this is that right now you have semiconductor IP like USBs or memory, and at the other end you have platform-based deisgn, which is architectural re-use but not IP,” said Mike Gianfagna, vice president of marketing at Atrenta. “The subsystem is what’s in between. What’s interesting about all of this is that a few years ago what we now consider a subsystem was a full chip.”

Business challenges and changes
As the market for subsystems grows it also will create significant fallout across the industry, which is why chipmakers, IP developers and tools companies all are scrambling to position themselves for this shift. Rather than just another form of outsourcing of pre-developed IP, the convergence of multiple IP blocks, development tools, software and even services threatens to shake up the power structure in this segment of the industry.

It’s not certain at this point who will lead the subsystems effort, and whether the leaders will emerge from existing IP vendors, software developers, tools companies, or some combination of all three that has yet to come together.

Neil Hand, group director for marketing inside of Cadence’s SoC realization group, believes that while foundries are well equipped to deliver IP the EDA companies are better equipped to deliver a subsystem. “This is the functional space, which is where EDA companies live,” Hand said. “They can combine IP with high-level synthesis and high-level modeling. It’s a natural direction for EDA companies to be working with IP.”

eSilicon’s Subramaniam believes it also could be the chip companies that ultimately sell the combined subsystems. “I see the chip companies becoming more like IP companies, particularly as 3D stacking evolves,” he said. “You might see memory companies initially, but it also could be analog companies or an RF company selling the subsystems.”

At least part of what will drive these changes is the push toward Wide I/O and the recognition that multicore and many-core strategies need to be re-evaluated. The initial idea behind multicore was that either software would be written in parallel or that virtualization would work when parallelization wasn’t possible. Despite the devotion of enormous resources to parallelization of software, the best that companies have been muster for many applications is to thread certain functions onto two or four cores. In a 16-core processor, that still leaves 12 cores idle.

Virtualization hasn’t worked out as planned, either, despite its success in the server world. The solution in enterprise IT departments has been to virtualize servers to improve utilization of the servers, which typically had been running at 5% to 15% of capacity, by most industry estimates. While that improved efficiency in large server farms with thousands of server racks, because it reduced cooling costs and the cost of powering the servers, the strategy is actually inefficient at the processor level because all the cores must be homogeneous and too many need to be in the “on” state to take advantage of this approach. Moreover, one of the limitations of multicore and many-core systems is the shared memory.

With wide I/O, more dedicated memory and heterogeneous cores sized for specific applications, performance can be ratcheted up significantly while simultaneously reducing power. That basically turns a core into a subsystem, and one that may or may not be independently designed by a third party and tweaked slightly for re-use.

“The tricky part is what happens near the interface,” Gianfagna said. “Timing, power and the performance of a subsystem, or even a block, are now affected by its neighbors. That means you have to re-check it in the context of full chip integration. We will need tools at the subsystem and the system level to do that. In my opinion, that’s a huge opportunity for EDA. It’s also a modeling and methodology challenge.”

Signal traffic also is affected. Sonics’ Mac Hale said connectivity is one of the top issues that needs to be addressed as IP is combined into subsystems. “We need much more flexible interfaces to deal with this,” he said. “System-level IP is becoming much more important these days, and that includes subsystems. We need to understand how different subsystems interact.”

Impact of 3D stacking
3D stacking and Wide I/O are expected to bolster sales of pre-integrated IP even more. While solving the issue of traffic bottlenecks, they also significantly raise the complexity of the interactions.

“It’s not really off-the-shelf subsystems,” said Cadence’s Hand. “They have to be tweaked by traffic patterns. Long-term there may be a whole memory subsystem, but right now it’s getting together pieces that work. That could include a Qualcomm baseband subsystem, which is incredibly complex. It also could be a compute subsystem that includes a processor and graphics chip. But while there is a demand for off-the-shelf IP that works together, customers are still wary
of taking everything off the shelf.”

In one respect this is a significant market shift. From an EDA tools perspective, however, it amounts to a tweak—at least for the moment.

Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics, said that whether it’s blocks or subsystems or even moving devices onto printed circuit boards, the basic idea hasn’t changed. As a result he believes many of tools at the back end of the design should work fine—at least until stacking of chips begins over the next couple years.

“At that point you’re going to be doing the kind of make vs. buy decisions that you’re doing now with third-party IP, but it could be a proven die instead of IP,” Buehler-Garcia said. “From an EDA perspective, until you are doing tradeoff analysis and tuning with the TSV (through-silicon via), the tools we have now will work with extra scripts.”

Conclusions
The push toward subsystems will continue unfolding over the next few years, driven by ever-increasingly complexity and an understanding of where companies truly add value and where they’re adding a function that is required by a particular market segment. That makes subsystems a design shortcut, and one that is particularly useful when the marketing department adds another requirement late in the design cycle.

“An IP subsystem becomes the bridge between the system-level design and the implementation,” said Synopsys’ Koeter. “You get a virtualized model of the IP subsystem, accelerated chip-level verification and you start seeing software integration of the stack.

It also becomes a business opportunity in its own right for companies that can build these flexible subsystems, and for those that can sell them in a coherent way.

“The market opportunity is for a catalog of proven silicon so you pick out what you want,” said Mentor’s Buehler-Garcia. “That is a quick way to get to market.”

By Ed Sperling
The global semiconductor industry appears to be picking up steam.

MediaTek adopted Mentor Graphics’ Calibre PERC for ESD and circuit reliability verification. Considering MediaTek’s strength in the Asian communications market, this is a significant win.

Sonics won a deal with Altair Semiconductor, which licensed its on-chip networks for 4G LTE chipsets using ultra low power.

MIPS won a deal with Mobile Devices of Taiwan for its m14Kc core, which will be used in wireless and mobile applications. Mobile Devices said the keys to the deal were performance, low power and code compression.

Synopsys announced fiscal Q1 results. Revenue was up 10.4% to $365 million, compared with $330 million in the same period in fiscal 2010. The company expects to post revenue of $386 million to $394 million for its fiscal Q2. On a non-GAAP basis, which the company believes is more accurate, profits were $68 million in Q1 vs. $62 million in the same period in fiscal 2010. It’s good to be the king.

TSMC isn’t doing too badly, either. The company announced a cash dividend of $3 a share. That’s three Taiwanese dollars, of course. There are 29.45 Taiwanese dollars to the U.S. dollar. It works out to about a dime a share. Still, it’s better than stockpiling cash. TSMC also is working with the National Taiwan University to develop a 40nm 3D TV chip.

By Ed Sperling
Mentor Graphics came under siege from corporate raider Carl Icahn, who claimed the company should be sold. Icahn’s group, which has bought up about 15% of Mentor’s stock, filed a proxy statement with the SEC to vote for its own officers on Mentor’s board. This could well be the most bizarre development in EDA history.

On a kinder and more productive note, Mentor won a deal with VIA Technologies, which makes low-power x86 processors. VIA is adopting the Calibre electrical rule checking product for electrostatic discharge analysis.

Synopsys is collaborating with Varian Semiconductor Equipment on process models for advanced logic and memory using Technology CAD models for cryogenic ion implantation. This is really interesting technology, but it makes it hard to explain at social gatherings what you do for a living.

Synopsys also introduced new technology for optimizing multicore systems. The company’s Platform Architect allows hardware-software partitioning and analysis well before the software is available. And it released a DDR memory controller that it claims has 30% lower latency and up to 15% higher throughput.

Apache Design Solutions rolled out its next-gen Chip Power Model for analyzing and optimizing the chip, the package and the system. This is a big step forward for advanced process nodes.

Tensilica introduced its DSP IP cores for LTE Advanced, which is the de facto 4G standard. Now you’ll be able to actually finish downloading mail before the cops pull you over and put your phone away.

Also in the LTE Advanced space, MIPS won a deal with Altair Semiconductor for its 4G LTE multithreaded processor IP.

A group of companies inside the SOI Consortium have created 20nm Ultra Thin Body Silicon on Insulator using fully depleted SOI. This is a major step forward for reducing current leakage. The wafers were provided by Soitec.

U.K.-based CSR is collaborating with TSMC on 90nm embedded flash process technology, IP and RF processes. Most of this stuff was being done at 180nm, so this is a two-node jump.

By Ed Sperling
Mentor Graphics won a couple of power-related deals. The Semiconductor Technology Academic Research Center (STARC)—a group of top Japanese companies that includes Fujitsu, Renesas and Panasonic—has successfully used its Tessent test methodology for low-power ICs. And Fujitsu is using Mentor’s Calibre Proprammable Electrical Rule Checker to protect against electrostatic discharge and to support multiple voltage domains.

STARC also joined forces with Cadence for a 32/28nm DFM flow.

Synopsys rolled out its DDR PHY compiler for multiple flavors of DDR2 and DDR3, complete with unlimited “what if” types of scenarios.

eSilicon has begun work on a 28nm test chip. That opens the door for mainstream chip design to step up to the next node. To put this in perspective, large IDMs have begun work at 22/20nm and 15/14nm.

Arteris won two deals. Pixelworks is using Arteris’ FlexNoC network-on-chip interconnect fabric and its memory scheduler for its video-processing SoCs. RIM, meanwhile, is using TI’s OMAP processor, which includes Arteris’ NoC technology.

On the financial front, MIPS’ Q2 revenue grew 44% year over year to $21.9 million. Net income was $6 million vs. $2.8 million last year. Even more important, license revenue increased 85%. Company executives attribute much of the growth to Android.

TSMC’s revenue rose 19.6% in Q4 of 2010, compared with the same period in 2009, but sequentially the results were down 1.9%. Net income was up 3.1% sequentially and 27.2% year over year. What’s particularly interesting is that 40nm wafers accounted for 21% of the total revenues, and 65nm accounted for another 31%. TSMC considers both to be advanced technology nodes and said this is the first time they’ve accounted for 52% of the total.