Cut, clarity, computer?

Diamonds are forever…or, at least, the effects of one particular diamond on quantum computing may be, according to a team that includes scientists from USC that built a quantum computer in a diamond.

The diamond is the first of its kind to include protection against decoherence—noise that prevents a computer from functioning properly. A demonstration of the technology showed the viability of solid-state quantum computers, which unlike earlier gas- and liquid-state systems, may represent the future of quantum computing because they can easily be scaled up in size. Comparatively, current quantum computers typically are very small but cannot yet compete with the speed of larger, traditional computers.

The multinational team included University of Southern California (USC) professor Daniel Lidar and USC postdoctoral researcher Zhihui Wang, as well as researchers from the Delft University of Technology in the Netherlands, Iowa State University and the University of California, Santa Barbara.

The diamond quantum computer system featured two quantum bits, or qubits, made of subatomic particles. As opposed to traditional computer bits that can encode distinctly either a one or a zero, qubits can encode a one and a zero at the same time. This property, called superposition, along with the ability of quantum states to “tunnel” through energy barriers, some day will allow quantum computers to perform optimization calculations much faster than traditional computers, researchers said.

Solid-state computing systems have existed before but the team said this was the first to incorporate decoherence protection: using microwave pulses to continually switch the direction of the electron spin rotation. “It’s a little like time travel,” Lidar said, because switching the direction of rotation time-reverses the inconsistencies in motion as the qubits move back to their original position. The team demonstrated its diamond-encased system did indeed operate in a quantum fashion by seeing how closely it matched “Grover’s algorithm.”

Preventing Simulator Deadlock

With chips of the future likely to have hundreds or even thousands of cores, predicting how these massively multicore chips will behave is no easy task. While software simulations work up to a point more accurate simulations typically require hardware models: programmable chips that can be reconfigured to mimic the behavior of multicore chips.

Researchers from MIT’s Computer Science and Artificial Intelligence Laboratory (CSAIL) recently presented a new method to do just that: improve the efficiency of hardware simulations of multicore chips and guarantee that the simulator won’t go into “deadlock”—a state in which cores get stuck waiting for each other to relinquish system resources, such as memory.

This method is expected to make it easier for designers to develop simulations and for outside observers to understand what those simulations are intended to do.

Hardware simulations of multicore chips typically use FPGAs. However, chip architects using FPGAs to test multicore-chip designs must simulate the complex circuitry found in general-purpose microprocessors either by hooking together a lot of FPGAs but only modeling only a small portion of the whole chip design or by simulating the circuit behavior in stages, which is extremely slow.

Graduate students Asif Khan and Muralidaran Vijayaraghavan; their adviser, Arvind, the Charles W. and Jennifer C. Johnson Professor of Electrical Engineering and Computer Science; and Silas Boyd-Wickizer, a CSAIL graduate student in the Parallel and Distributed Operating Systems Group, adopted the second approach for a simulation system they’ve dubbed “Arete.” However, the system uses a circuit design they developed that allows the ratio between real clock cycles and simulated cycles to fluctuate as needed thereby allowing for faster simulations and more economical use of the FPGA circuitry.

One advantage of their system, the CSAIL researchers said, is that it makes it easier for outside observers—and even for chip designers themselves—to understand what a simulation is intended to do. With other researchers’ simulators, it’s often the case that “the cycle-level specification for the machine that they’re modeling is in their heads,” Khan says. “What we’re proposing is, instead of having this in your head, let’s start with a specification. Let’s write it down formally, but in a language that is at a very high level of abstraction so it does not require you to write a lot of details. And once you have this specification that clearly tells you how the entire multicore model is going to behave every cycle, you can transform this automatically into an efficient mapping on the FPGA.”

The researchers’ high-level language, which they dubbed StructuralSpec, builds on the BlueSpec hardware design language that Arvind’s group helped develop in the late 1990s and early 2000s. The StructuralSpec user gives a high-level specification of a multicore model, and software spits out the code that implements that model on an FPGA. Where a typical, hand-coded hardware model might have about 30,000 lines of code, Khan says, a similar model implemented on StructuralSpec might have only 8,000 lines of code.

–Ann Mutschler

Science Behind Networks on Chips
As chipmakers continue to add cores or processing units to keep increasing computational power, the traditional bus structure is running out of steam. The result is that cores need to communicate the same way computers hooked to the Internet do—by bundling the information they transmit into packets, according to researchers at MIT.

Li-Shiuan Peh, an associate professor of electrical engineering and computer science at MIT, said each core would have its own router, which could send a packet down any of several paths, depending on the condition of the network as a whole. Peh and her colleagues have developed two techniques to address these concerns. One is something they call “virtual bypassing.” On the Internet, when a packet arrives at a router, the router inspects its addressing information before deciding which path to send it down. With virtual bypassing, however, each router sends an advance signal to the next, so that it can preset its switch, speeding the packet on with no additional computation. In her group’s test chips, Peh says, virtual bypassing allowed a very close approach to the maximum data-transmission rates predicted by theoretical analysis.

Learn more at this year’s DAC when Peh and her colleagues present a paper on the subject. The researchers establish theoretical limits on the efficiency of packet-switched on-chip communication networks and present measurements performed on a test chip in which they said came very close to reaching several of those limits.

Improving Reliability with Magnetic Testing
To measure the adhesion strength between thin films of materials used in microelectronic devices, photovoltaic cells and microelectromechanical systems (MEMS), researchers at Georgia Tech have developed a new technique that leverages the force generated by magnetic repulsion, which could help ensure the long-term reliability of electronic devices, and assist designers in improving resistance to thermal and mechanical stresses.

Commenting on the fixtureless and non-contact technique, known as the magnetically actuated peel test (MAPT), Suresh Sitaraman, a professor in the George W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology said, “As we continue to scale down the transistor sizes in microelectronics, the layers will get thinner and thinner,” he said. “Getting to the nitty-gritty detail of adhesion strength for these layers is where the challenge is. This technique opens up new avenues…This technique would help manufacturers know that their products will meet reliability requirements, and provide designers with the information they need to choose the right materials to meet future design specifications over the lifetimes of devices.”

Sitaraman and doctoral student Gregory Ostrowicki have used their technique to measure the adhesion strength between layers of copper conductor and silicon dioxide insulator. They also plan to use it to study fatigue cycling failure, which occurs over time as the interface between layers is repeatedly placed under stress. The technique may also be used to study adhesion between layers in photovoltaic systems and in MEMS devices, the Georgia Tech researchers said.

–Ann Steffora Mutschler

Debugging Multicore Software In Reverse
One of the big problems in system-level design is debugging software, and nowhere is this harder than with multiple cores. But a researcher at Helsinki’s Aalto University has come up with a visualization tool that speeds the debugging process.

Rather than following the software step by step, Jan Lonnberg’s approach is to start with unexpected errors and then searches for places where the software goes awry. The errors typically crop up in concurrent programming when interrelated processes don’t proceed at the same pace.

Buckliball Anyone?
Understanding how things collapse is just as important as how they can withstand pressure and shock—something that will become critical in stacked die with through-silicon vias.

MIT’s Civil and Environmental Engineering Department has created a collapsible ball from a single piece of material with no moving parts but with strategically placed dimples. When the air is sucked out, the ball collapses. But equally important, the ball can be re-inflated.

How exactly this will apply to electronics and systems remains to be seen. But the more researchers can learn about controlling collapse in certain parts while maintaining others, the more these kinds of ideas can cross into a macro system-level design.

–Ed Sperling

The hidden impact of job loss
The loss of jobs to lower-cost markets has a big effect on the economies where those jobs came from, according to a study by MIT economist David Autor. While this study is interesting in its own right, it may be an indication of what happens if design jobs move overseas.

The study showed that a city with exposure to Chinese manufacturing has a roughly 5% decrease in the number of manufacturing jobs and an increase of about $65 per person in social insurance—unemployment, health care and disability. The $65 wipes out about a third of the benefit of moving that manufacturing overseas, and that’s just for the people who are still employed. Those who are unemployed are hit much harder.

How this will play into the design world remains to be seen. For one thing, complexity is actually forcing a re-aggregation of design teams on the same continent, and often in the same building. But there’s no guarantee that re-aggregation will happen in North America, Europe or Japan, which are the traditional base for complex—and expensive—design. Manufacturing may be just the beginning.

Engineering heroes
Stanford named eight engineering heroes from former faculty and alumni. Making the grade were former Intel CEO Craig Barrett; Andy Bechtolsheim, the architect of Sun’s workstation; Morris Chang, chairman of TSMC, and Theodore Maiman, who invented the world’s first working laser.

These four in particular had a huge impact on the semiconductor industry, not to mention the current design industry their developments helped to create.

Reducing uncertainty
The Heisenberg Uncertainty Principle is getting a little less uncertain. Researchers at Georgia Tech are “squeezing” measurements to make them more accurate.

This may not seem relevant at 28nm, but it may become especially relevant at 10nm when carbon nanotubes, graphene and other new materials force designers to begin grappling with quantum effects. That involves Bose-Einstein Condensates, as well, which also can be squeezed to more accuracy.

It may be time to dust off the physics books and take another look.

Nanowire Advances
Nanowires, which have been a rather vague future direction for ICs beyond 10nm, are showing real signs of progress in the lab.

MIT researchers have figured out a way to control the width and composition as the wires grow through gas adjustments. Initial wires were made with indium nitride and indium gallium nitride.

Nanowires are less than 10nm in thickness. They also are subject to quantum effects because they are so thin that electrons are confined. How nanowires affect signal integrity, power and heat remains to be seen. Also unknown is just how commercially viable they will be—can they be manufactured in volume for a reasonable cost with an acceptable level of defects?

Tiny Floating Surgeons
It’s always interesting to see how technology developed at the chip level actually gets used, and medical research is at the forefront of this. The most recent innovation comes from Stanford electrical engineers, who have created an extremely tiny self-propelled device that can controlled wirelessly throughout the bloodstream.

The device is controlled through electromagnetic RF, meaning it can be powered externally. That significantly reduces the size of the device and makes them small enough to swallow. Stanford’s Ada Poon, assistant professor of electrical engineering, said one of the applications is minimally invasive surgery such as zapping blood clots or removing plaque from arteries. It also can be used for exploration and analysis.

One key insight is the frequency of the chip. It needs to run at about 1GHz, which researchers said is about 100 times higher than they initially thought. But that also meant the size of the antennae could be much, much smaller and still deliver power to the device.

This sounds a lot like Fantastic Voyage, minus the ridiculous part about shrinking people. Who needs people? In the future you may not even need surgeons.

–Ed Sperling

Quantum Networking
Seven U.S. universities have received a grant from the Air Force Office of Scientific Research to find the best approach for developing quantum memory based on the interaction between light and matter.

The ultimate goal is long-distance transmission of secure information. Light is harder to hack into than electricity in a copper cable. The memory needs to be able to store quantum information for longer periods of time—seconds instead of milliseconds–to be able to convert that information to light, and to transmit the information over long distance.

Wireless Drug Delivery
Researchers at MIT have developed a wireless chip that can be used inside an implantable medical device to accurately deliver treatment for osteoporosis. The medical device stores the drugs in hermetically sealed containers and releases doses about the size of a pinprick.

The devices are far enough along that they are now in clinical human trials. They work over a special frequency called Medical Implant Communication Service at a distance of a few inches. That distance will be extended in the future. But what’s particularly interesting is that the device actually contains reservoirs capped with platinum and titanium, which melts when a small current is applied from the chip, thereby releasing the drug.

The chips can be programmed to release a controlled delivery over time, a pulsed drug delivery, or they can deliver multiple drugs at different times.

By Ed Sperling
The jury is out on 3D TV market because not everyone wants to don a pair of glasses to watch their favorite show, but what about holographic TV where you don’t need special glasses? Synopsys’ Eric Huang looks at some new technology out of MIT, complete with video.

Cadence’s Srikanth Vijayaraghavan takes the covers off assertion-based verification methodology for analog. Analog is never going away, even though it might be a tough sell at 14nm, so the best solution is to find a better way of creating it.

Mentor’s Colin Walls dissects C++, which he says is a better C language. You might have expected that, given the two “plus” signs. Why didn’t they call it A++ though?

Semico’s Morry Marshall looks at an RFID chip developed in Brazil that can be implanted into cattle. This gives a whole new meaning to “cow chips.”

Atrenta’s Ron Craig sounds off on timing constraints and how to use them to your advantage, namely why so many engineers are encountering problems with them, in a posting by Ed Lee and Liz Masingill.

Synopsys’ Hezi Saar digs into 4G and why the tablet format is so important to the market. Think of it as a giant videophone—and one with lots of chips and IP.

Cadence’s Jack Erickson says SystemC is neither complicated nor belligerent. Those are his words, and he goes on to defend them—not that SystemC actually needs a defender. Another satisfied user.

Mentor’s Thomas Bollaert points to an ST white paper that lists seven steps to higher productivity. This is an interesting paper, but you do have to register. (Click the link at the bottom of the blog.)

Cadence’s Richard Goering looks at how Teradyne is using metric-driven verification in ASICs and FPGAs. The FPGA angle is particularly interesting, considering most people don’t use MDV in that world.

By Cheryl Ajluni

At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs).

The concept of 3D stacking or integration technology is not new. In fact, 3D stacking of dies has been successfully demonstrated and is currently being commercially employed in some embedded domains (e.g., stacking DRAM memory on CPU cores). A recent 3D IC report from Yole Développement suggests that by 2012, the number of 3D IC-processed wafers could surpass 10 million units, driven in part by handset, wireless and computing applications. Given the intense interest and work going into developing 3D integration technology, this prediction seems just about right—assuming, of course, that a few challenges can first be met.

Exploring the third dimension

Very simply put, 3D integration consists of stacking integrated circuits and connecting them vertically so that they behave as a single device. A 3D chip is therefore just a stack of multiple device layers with direct vertical interconnects tunneling through them. So what’s the big deal about 3D integration?

Today’s semiconductor chips face extreme pressure to achieve increased performance, while reducing their size and accommodating lots of new functionality. When these factors coalesce in traditional 2D chips, longer interconnects result. In SoCs, longer interconnects translate into reduced speed and increased power consumption.

A key benefit of 3D integration is that it can reduce the length of interconnects. Additionally, it provides higher transistor density, faster interconnects and heterogeneous technology integration, with potentially lower power, cost and faster time-to-market. As Matt Nowak, director of engineering in the VLSI technology group of Qualcomm’s CDMA technology division, pointed out in a DAC 2008 presentation, the 3D approach “achieves extremely high densities, allowing us to use heterogeneous technologies and reduce form factor. The key is that it enables the use of new differentiating technologies to build new architectures that cannot be built in existing technologies.”

Eyeing recent developments

Up to this point, most efforts in 3D integration have focused on developing different fabrication techniques for stacking multiple device layers and forming the vertical interconnects. Much of the work has been done through collaborations with academia, industry organizations and government-sponsored laboratories around the world. One of the key technologies to come out of this research is a next-generation interconnect technology known as Through-Silicon Via (TSV). The TSV is a vertical electrical connection that passes completely through a silicon wafer or die to produce multilevel chips with an optimum combination of cost, functionality, performance, and power consumption. By using TSV technology, 3D ICs can pack greater functionality into a smaller footprint and realize shorter critical electrical paths, resulting in faster operation.

Some of the other developments to come out of ongoing 3D integration research were recently recognized at the Electronic Components and Technology Conference. Sandia National Laboratories presented details of its W TSV process, which is said to provide a suitably low-resistance metal with a coefficient of thermal expansion close to Si, a via fill that is conformal, and can be readily integrated into IC fabrication. IMEC introduced a novel process for die-to-wafer bonding (using Cu-Cu bonds) of its 3D SIC technology and a scalable TSV technology for 3D wafer-level packaging. Its TSV technology is designed for 3D structures where interconnects are fabricated after standard CMOS processing.

SEMATECH also is focusing its 3D research on TSV technology, particularly for implementation. The industry organization is actively working to bring together partners from across industry—chipmakers, equipment and materials suppliers, assembly and packaging service companies—to make 3D TSV suitable for high-volume manufacturing (Figure 1).

Help: tool support needed!

While ongoing research and development is absolutely critical to the success of 3D integration, perhaps one of the greatest challenges it faces is tool support in terms of design techniques and methodologies. Without it, engineers have virtually no efficient way to exploit the technology’s benefits. Tool support is especially critical when it comes to 3D integration because vertical stacking tends to increase thermal resistances, further exacerbating temperature-induced problems that can negatively affect system reliability, performance and leakage power. The use of 3D also will significantly complicate the typical design flow.

The key, of course, lies in creating a standardized design environment and methodology for physical design of 3D chips that could support a range of different tools. Having the tools integrated in one place would make it easier for designers to explore and make architectural decisions and then, to hand those decisions off to next stages in the design process.

3D IC integration is still in its infancy and, as a result, tools developed today for one specific application (e.g., stacked memory) may not be suitable for heterogeneous integration tomorrow. Nevertheless, there are some tools available now, with more in development. Some of these tools include:

3D PathFinding

Javelin Design Automation. 3D PathFinding provides a detailed 3D flow for accurate performance/power/cost estimates that can be used for rapid design exploration and optimization of 3D stacked ICs. Developed in collaboration with IMEC and Qualcomm, the solution extends Javelin’s existing PathFinding methodology and j360 Silicon PathFinder physical design prototype platform to support virtual chip design (Figure 2).

MAX-3D, R3Integrator, R3CAD, and R3Artist; R3Logic

These tools, developed through work conducted as part of research programs sponsored by the Defense Advanced Research Projects Agency (DARPA), enable 3D IC design and analysis (Figure 3). MAX-3D is a 3D mask layout tool whose technology file includes all properties of stacking process, wafer orientations, bond materials, via electrical/material properties, and also incorporates 2D foundry design kits. R3Integrator is used for die/interposer/package co-design with TSVs. R3CAD is a java-based, multi-platform tool for 3D design research and prototype study and R3Artist is an embedded 3D layout editor (Figure 3).

R3Logic is currently collaborating with STMicroelectronics and CEA-LETI to develop a full 3D design flow for 3D heterogeneous system and system-in-package design.

3DCACTI

3DCACTI estimates the optimum access times and power dissipation of a cache using 3D IC technology for a given number of active device layers and by partitioning device layers for various technology nodes. Based on the estimation, it searches for the optimized configuration that provides the best delay, power and area efficiency trade-off according to the cost function for a given number of different 3D partitions.

3D Magic and PR3D, Massachusetts Institute of Technology

3D Magic is a comprehensive layout methodology for 3D circuit-layout editing and extraction with MAGIC, an open source layout editor developed by UC Berkeley. PR3D is a placement and routing tool for standard cell design in 3D. Both tools were developed through MIT’s Interconnect Focus Center Research Program. MIT also developed SysRel (System-Level IC Reliability) for assessing the interconnect reliability of 3D ICs from a thermal-aware perspective at the circuit-layout level.

Conclusion

With the pressure on traditional 2D chips mounting, 3D integration has begun to establish itself as a viable means of breathing more life into Moore’s Law. It certainly touches on all the hot buttons in the industry today, namely low power, cost and time-to-market. The challenge will be in ensuring that these benefits are realized in a timely and efficient manner. 3D-specific design tools and methodologies are coming to meet this challenge head on. In the meantime, the tools available now and the groundwork for future tools and methodologies being laid by industry organizations, academia and commercial companies alike, will go along way in ensuring 3D integration plays a critical role in the future of the semiconductor industry.