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IoT Cookbook: Analog and Digital Fusion Bus Recipe

Tuesday, December 2nd, 2014

Experts from ARM, Mathworks, Cadence, Synopsys, Analog Devices, Atrenta, Hillcrest Labs and STMicroelectronics cook up ways to integrate analog with IoT buses.

By John Blyler, Editorial Director

Many embedded engineers approach the development of Internet-of-Things (IoT) devices like a cookbook. By following previous embedded recipes, they hope to create new and deliciously innovative applications. While the recipes may be similar, today’s IoT uses strong concentration of analog, sensors and wireless ingredients. How will these parts combine with the available high-end bus structures like ARM’s AMBA? To find out, “IoT Embedded Systems” talked with the head technical cooks including Paul Williamson, Senior Marketing Manager, ARM; Rob O’Reilly, Senior Member Technical Staff at Analog Devices; Mladen Nizic , Engineering Director, Mixed Signal Solution, Cadence; Ron Lowman, Strategic Marketing Manager for IoT, Synopsys; Corey Mathis, Industry Marketing Manager -  Communications, Electronics and Semiconductors, MathWorks; Daniel Chaitow, Marketing Manager, Hillcrest Labs; Bernard Murphy, CTO, Atrenta; and Sean Newton, Field Applications Engineering Manager, STMicroelectronics. What follows is a portion of their responses. — JB

Key points:

  • System-level design is needed so that the bus interface can control the analog peripheral through a variety of modes and power-efficient scenarios.
  • One industry challenge is to sort the various sensor data streams in sequence, in types, and include the ability to do sample or rate conversion.
  • To ensure the correct sampling of analog sensor signals and the proper timing of all control and data signals, cycle accurate simulations must be performed.
  • Control system and sensor subsystems are needed to help reduce digital bus cycles by tightly integrating the necessary components.
  • Hardware design and software design have inherently different workflows, and as a result, use different design tools and methodologies.
  • For low-power IoT sensors, the analog-digital converter (ADC) power supply must be designed to minimize noise. Attention must also be paid to the routing of analog signals between the sensors and the ADC.
  • Beyond basic sensor interfacing, designer should consider digitally assisted analog (DAA) – or digital logic embedded in analog circuitry that functions as a digital signal processor.

Blyler: What challenges do designers face when integrating analog sensor and wireless IP with digital buses like ARM’s AMBA and others?

Williamson (ARM): Designers need to consider system-level performance when designing the interface between the processor core and the analog peripherals. For example a sensor peripheral might be running continuously, providing data to the CPU only when event thresholds are reached. Alternatively the analog sensor may be passing bursts of sampled data to the CPU for processing.  These different scenarios may require that the designer develop a digital interface that offers simple register control, or more advanced memory access. The design of the interface needs to enable control of the peripheral through a broad range of modes and in a manner that optimizes power efficiency at a system and application level.

O’Reilly (Analog Devices): One challenge is ultra-low power designs to enable management of the overall system power consumption. In IoT systems, typically there is one main SoC connected with multiple sensors running at different Output Data Rates (ODR) using asynchronous clocking. The application processor SoC collects the data from multiple sensors and completes the processing. To keep power consumption low, the SoC generally isn’t active all of the time. The SoC will collect data at certain intervals. To support the needs of sensor fusion it’s necessary that the sensor data includes time information. This highlights the second challenge, the ability to align a variety of different data types in a time sequence required for fusion processing. This raises the question “How can an entire industry adequately sort the various sensor data streams in sequence, in types, and include the ability to do sample or rate conversion.?”

Nizic (Cadence): Typically a sensor will generate a small (low voltage/current) analog signal which needs to be properly conditioned and amplified before converting it to digital signal sent over a bus to memory register for further processing by a DSP or a controller. Sometimes, to save area, multiple sensor signals are multiplexed (sampled) to reduce the number of A2D converters.

From the design methodology aspect, the biggest design challenge is verification. To ensure analog sensor signals are sampled correctly and all control and data signals are timed properly, cycle-accurate simulations must be performed. Since these systems now contain analog, in addition to digital and bus protocol verification, a mixed-signal simulation must cover both hardware and software. To effectively apply mixed-signal simulation, designers must model and abstract behavior of sensors, analog multiplexers, A2D converters and other analog components. On the physical implementation side, busses will require increased routing resources, which in turn mean more careful floor-planning and routing of bus and analog signals to keep chip area at minimum and avoid signal interference.

Lowman (Synopsys): For an IC designer, the digital bus provides a very easy way to snap together an IC by hanging interface controllers such as I2C, SPI, and UARTs to connect to sensors and wireless controllers.  It’s also an easy method to hang USB and Ethernet, as well as analog interfaces, memories and processing engines.  However, things are a bit more complicated on the system level. For example, the sensor in a control system helps some actuator know what to do and when to do it.  The challenge is that there is a delay in bus cycles from sensing to calculating a response to actually delivering a response that ultimately optimizes the control and efficiency of the system.  Examples include motor control, vision systems and power conversion applications. Ideally, you’d want a sensor and control subsystem that has optimized 9D Sensor Fusion application. This subsystem significantly reduces cycles spent traveling over a digital bus by essentially removing the bus and tightly integrating the necessary components needed to sense and process the algorithms. This technique will be critical to reducing power and increasing performance of IoT control systems and sensor applications in a deeply embedded world.

Mathis (Mathworks): It is no surprise that mathematical and signal processing algorithms of increasing complexity are driving many of the innovations in embedded IoT. This trend is partly enabled by the increasing capability of SoC hardware being deployed for the IoT. These SoCs provide embedded engineers greater flexibility regarding where the algorithms get implemented. The greater flexibility, however, leads to new questions in early stage design exploration. Where should the (analog and mixed) signal processing of that data occur? Should it occur in a hardware implementation, which is natively faster but more costly in on-chip resources? Or in software, where inherent latency issues may exist? One key challenge we see is that hardware design and software design have inherently different workflows, and as a result, use different design tools and methodologies. This means SoC architects need to be fluent in both C and HDL, and the hardware/software co-design environments needed for both. Another key challenge is that this integration further exacerbates the functional, gate- or circuit-level, and final sign-off verification problems that have dogged designers for decades. Interestingly, designers facing either or both of these key challenges could benefit significantly from top-down design and verification methodologies. (See last month’s discussion, “Is Hardware Really That Much Different From Software?”)

Chaitow (Hillcrest Labs): In most sensor-based applications, data is ultimately processed in the digital realm so an analog to digital conversion has to occur somewhere in the system before the processing occurs. MEMS sensors measure tiny variations in capacitance, and amplification of that signal is necessary to allow sufficient swing in the signal to ensure a reasonable resolution. Typically the analog to digital conversion is performed at the sensor to allow for reduction of error in the measurement. Errors are generally present because of the presence of noise in the system, but the design of the sensing element and amplifiers have attributes that contribute to error. For a given sensing system minimizing the noise is therefore paramount. The power supply of the ADC needs to be carefully designed to minimize noise and the routing of analog signals between the sensors and the ADC requires careful layout. If the ADC is part of an MCU, then the power regulation of the ADC and the isolation of the analog front end from the digital side of the system is vital to ensure an effective sampling system.

As always with design there are many tradeoffs. A given analog MEMS supplier may be able to provide a superior measurement system to a MEMS supplier that provides a digital output. By accepting the additional complexity of the mixed-signal system and combining the analog sensor with a capable ADC, an improved measurement system can be built. In addition if the application requires multiple sensors, using a single external multiple channel ADC with analog sensors can yield a less expensive system, which will be increasingly important as the IoT revolution continues.

Murphy (Atrenta): Aside from the software needs, there are design and integration considerations. On the design side, there is nothing very odd. The sensor needs to be presented to an AMBA fabric as a slave of some variety (eg APB or AHB), which means it needs all the digital logic to act as a well-behaved slave (see Figure). It should recognize it is not guaranteed to be serviced on demand and therefore should support internal buffering (streaming buffer if an output device for audio, video or other real-time signal). Sensors can be power-hungry so they should support power down that can be signaled by the bus (as requested by software).

The implementation side is definitely more interesting. All of that logic is generally bundled with the analog circuitry into one AMS block and it is usually difficult to pin down a floor-plan outline on such a block until quite close to final layout. This makes full-chip floor planning more challenging because you are connecting to an AMBA switch fabric, which likes to connect to well-constrained interfaces because the switch matrix itself doesn’t constrain layout well on its own. This may lead to a little more iteration of the floor plan than you otherwise might expect

Beyond basic sensor interfacing, you need to consider digitally assisted analog (DAA). This is when you have digital logic embedded in analog circuitry, functioning as a digital signal processor to perform effectively an analog function but perhaps more flexibly and certainly with more programmability that analog circuitry. Typical applications are for beamforming in radio transmission and for super-accurate ADCs.

Figure: The AMBA Bus SOC Platform is a configurable with several peripherals and system functions, e.g., AHB Bus(es), APB Bus(es), arbiters, decoders. Popular peripherals include RAM controllers, Ethernet, PCI, USB, 1394a, UARTs, PWMs, PIOs. (Courtesy of ARM Community -

Newton (STMicroelectronics): Integration of devices such as analog sensors and wireless IP (radios) is widespread today via the use of standard digital bus interfaces such as I2C and SPI. Integration of analog IP with a bus – such as ARM’s AMBA – becomes a matter of connecting the relevant buses to the digital registers contained within the IP. This is exactly what happens when you use I2C or SPI to communicate to standalone sensors or wireless radio, with the low-speed bus interfaces giving external access to the internal registers of the analog IP. The challenges for integration to devices with higher-end busses isn’t so much on the bus interface, as it is in defining and qualifying the resulting SoC. In particular, packaging characteristics, the number of GPIO’s available, the size of package, the type of processing device used (MPU or MCU), internal memory capability such as flash or internal SRAM, and of course the power capabilities of the device in question: does it need very low standby power? Wake capability?  Most of these questions are driven by market requirements and capabilities and must be weighed against the cost and complexity of the integration effort.

The challenges for integration to devices with higher-end busses isn’t so much on the bus interface, as it is in defining packaging characteristics, available GPIOs, type of processing device, memory such as flash or internal SRAM, and power capabilities.

Blyler: Thank you.

This article was sponsored by ARM.

ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. mbed is a trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.

Blog Review – Mon. June 16 2014

Monday, June 16th, 2014

Naturally, there is a DAC theme to this week’s blogs – the old, the new, together with the soccer/football debate and the overlooked heroes of technology. By Caroline Hayes, Senior Editor.

Among those attending DAC 2014, Jack Harding, eSilicon rejoiced in seeing some familiar faces but mourns the lack of new faces and the absence of a rock and roll generation for EDA.

Football fever has affected Shelly Stalnaker, Mentor Graphics, as she celebrates the World Cup coming to a TV screen near you. The rest of the world may call soccer football but the universality of IC design and verification is an analogy that will resonate with sport enthusiasts everywhere.

Celebrating Alan Turing, Aurelien, Dassault Systemes, looks at the life and achievements of the man who broke the Enigma Code, in WWII, invented the first computer in 1936 and who defined artificial intelligence. The fact he wasn’t mentioned in the 2001 film, Engima, about the code breakers, reflects how overlooked this incredible man was.

Mixed signal IC verification was the topic for a DAC panel, and Richard Goering, Cadence runs down what was covered, from tools and methodologies, the prospects for scaling and a hint at what’s next.

Mixed-Signal Platform Extends Charging

Monday, September 19th, 2016

Mixed-signal platforms such as Silego’s GreenPAK simplify the design of an extended battery charger with minimal external components.

by Ramkumar Ramaswamy, PhD

Lead acid batteries, once charged, are typically held at a float voltage that is higher than the open-circuit voltage (OCV). The intent of this float charge is to compensate for self-discharge. Not that this is without problems: there is greater water loss due to gas evolution, when compared to being held at OCV. It has also been argued by many that maintaining stationary batteries at float voltage does more harm than good – see, eg., Nguyen et. al. [1]. Using a reduced float voltage with intermittent charge can be a superior method of battery management in many applications. One specific context of application for such battery management is in on-grid solar applications. In such applications, the battery is only used as a standby, yet it may represent a sizeable chunk of the investment in the solar system. Therefore, the battery life needs to be extended, and its maintenance and watering needs must be reduced also.

On initiating a charging cycle for a lead acid battery, it goes through several states. We summarize the process very briefly; more detailed information is readily available in the public domain, e.g. at websites such as The Battery University [2]. Charging begins in a constant current (CC) regime called the Bulk phase, which ends when the voltage reaches Bulk Voltage (see Table 1). The regime then changes to constant voltage (CV). The battery enters the Absorption state, in which the voltage is held constant at the Bulk Voltage for a specified period of time. Then the voltage is reduced to the Float Voltage which, in the standard case, signals the end of charging. In this application note we are not content with stopping with that. Rather, we want to hold the battery at the Float Voltage for a specified period of time, then reduce the voltage further to what we call the Reduced Float Voltage, which represents the end of the charge cycle. Typically, the Reduced Voltage will be close to the battery’s OCV. However, a battery cannot be held at OCV for too long because it starts to lose capacity and then sulfate. Therefore, the battery must intermittently be taken to a higher voltage (Float or Absorption Voltage) to compensate for this loss of capacity, then brought back to the Reduced Voltage. This may seem like an obvious feature to have in a solar inverter for example, but in the author’s experience it is not always available, even in premium inverter brands.

The below state diagram represents the above states and their transitions.

Figure 1. The Battery State Machine

Solution Architecture using GreenPAK 5

In this application note we will demonstrated how a mixed-signal platform like GreenPAK simplifies the design of an extended battery charger with minimal external components. We start by describing how the various building blocks of GreenPAK5 as well as external elements are brought together to create this platform. (We will henceforth use programming-style variable names such as BulkVoltage, FloatDuration etc.) The chip chosen is SLG46531V.

Figure 2. The GreenPAK 5 Design

Asynchronous State Machine (ASM). GreenPAK 5 was chosen because it offers an ASM that makes it particularly convenient to capture the battery states and transitions. The state and transition definitions as per Figure 1 above.

ACMP0-2. For this application note, we take a case where the nominal battery voltage is 12V. The design can easily be extended to other voltages. We can scale the battery voltage with a resistive voltage divider, but we choose an alternate strategy given that we are not interested in voltages less than 12.5V or greater than 14.5V. We subtract 12.5V using shunt references of 10V and 2.5V, as shown in Figure 3, leaving us with a much smaller voltage range of about 2V to contend with, thereby allowing greater accuracy in voltage measurement. This transformed battery voltage of 0-2V is run through a 0.5X gain stage at each analog comparator (ACMP) IN+ input[R8] .

Thus each ACMP input IN+ sees a voltage of 0-1V.

For example if we take a 12V Exide SolaTubular battery, the manufacturer-specified values and the transformed values for the respective ACMPs are as follows:

Parameter Value for 12V Battery Transformed Value at VIN+
Bulk voltage 14.5V 1.0V
Float voltage 13.7V 0.6V
Reduced Float voltage 12.6V 0.1V

Table 1: Typical voltages associated with a lead-acid battery

The above voltage thresholds for the ACMPs are conveniently derived from the internal voltage reference and no external voltage reference is required. The external components used in the design are shown below; the rationale behind the component values is explained in the section “Example Implementation.’

Figure 3. External Components Used

One of the ACMPs, ACMP0, is referenced to BulkVoltage; when the ASM is in Bulk and the battery reaches BulkVoltage, the AND gate triggers the state change from Bulk to Absorb. The other ACMPs are used to effect the CV regimes by holding the battery voltage at the respective value such as FloatVoltage and ReducedFloatVoltage as we will describe shortly.

Figure 4. DLY Config

Delays/Counters. Once the battery exits the bulk phase, the rest of the state transitions for the remainder of the charge cycle maybe conveniently triggered by the passage of time. For example, the battery moves from Absorb to Float after AbsorbDuration (2 hours) and from Float to ReducedFloat after FloatDuration (1 hour). After spending several days at ReducedFloatVoltage, the battery will be taken up to FloatVoltage again for FloatDuration and the process iterates. These time-based triggers are achieved using delay/counter blocks CNT1/2/3. We wire these as delays rather than counters because a counter outputs a high when it is reset which behavior upsets the operation. Instead, we configure these as rising-edge delays as shown alongside. For example, DLY3′s DLY_IN comes from the ASM’s Float state output; therefore when Float is entered, the high state is detected by DLY3 and fed to the Float-Reduced float transition after FloatDuration. As soon as the ASM moves from Float to ReducedFloat, DLY_IN returns to zero dragging the output also to zero. The clock source for all these delays is CNT0 whose input is the 25kHz clock and output period is set to 60 seconds.

GPIOs. A new charge cycle is initiated by driving a HIGH input on Pin3. In an actual application this could be used to initiate a new cycle manually, based on time or based on the battery voltage going too low. The last use case requires an external comparator, and effectively defines NewCycleVoltage as a trigger. Typically its value would be 11.5V for a 12V battery.

In the CC regime, current must typically be limited to C/10 where C is the battery capacity in AH. This is achieved by the output transistors Q1 and Q2 driven into an ON or OFF state by Pin4, wired as a digital output. The current-determining resistor is on the emitter of Q1, and as indicated its value should be 10/C for a battery of capacity C that is rated for a maximum charge current C/10. The battery is in the collector of Q1 so its voltage does not significantly affect the charge current.

ACMP1, ACMP2. Only one state transition is driven by voltage – the BulkVoltage. In contrast to this, the other voltages – e.g. FloatVoltage and ReducedFloatVoltage are not triggers for state transitions. Rather, these are outcomes of the state that the battery is in.  Because all these voltages are associated with a CV regime, we may use them as references for ACMP1 and ACMP2 respectively, which allows us to trigger a state change based on the current state and the battery voltage. These comparators are in turn used to drive the charging transistor Q1 as described now.

In the CV regime, there are two ways of charging a battery. One is by the use of a steady current and the other is by using a pulsed current of higher magnitude. For example, pulsed current is used in PWM charging which is popular for lead acid batteries as it supposedly helps reduce sulfation (See The Battery University article [3] and the accompanying comments). We use pulsed charging in the CV regime too, using the same PNP transistor used for CC charging. Based on the state of the battery, we select the appropriate ACMP to also drive the bias to Q1.  We use a 25mV hysteresis setting for the ACMPs so that the transistor switches on and off to maintain the average battery voltage at the desired level, equal to the selected ACMP’s reference voltage and within the chosen hysteresis band.

For instance, FloatVoltage is a reference for ACMP2. When the battery enters the Floating phase, we would like to use ACMP2′s output to determine when to bias Q1. Since ACMP2′s input IN+ pin is reading the actual battery voltage, it output will switch the transistor on and off repeatedly as the actual battery voltage oscillates slightly about FloatVoltage (within ACMP2′s hysteresis band). Similar logic holds for CV charging at the other voltages BulkVoltage and ReducedFloatVoltage. This logic is captured in the truth tables for LUT0/1/2, ORed together by L7.

Example Implementation. The design was implemented with the external components of Figure 3 and used to charge an Exide 12V 4.5AH battery. Z1 and Z2 must have a similar operating current range. Here they are LM4040s that operate with a current range of 60 uA to 10mA. Along with R3 = 330R, the current range falls within spec for the desired battery voltage range.  C1 is required to avoid forcing the GreenPAK to respond too fast when the comparator is in the hysteresis range, otherwise spurious behavior can result. Q2 is driven to saturation whenever Pin 4 goes high; this drives nearly 10mA through the LED with Vcc = 15V. With a red LED, the voltage drop across R1 is about 1V, so R1 should be set to 10/C ohms to limit charge current to C/10.

The following photographs show the waveform at Pin 4 when the battery is in the Absorb and Float  CV regimes. The pulsing nature of the charger is evident, the charge pulse in this test setup was about 5ms with a 300mA charge current.

Figure 5. Pin 4 level, Absorb

Figure 6. Pin 4 level, Float

(Note: In the accompanying .GP5 file we have, for testing and evaluation purposes, set CNT0 to output 1s pulses rather than 60s pulses, and the DLY block data have been set so that AbsorbDuration, FloatDuration and ReducedFloatDuration are 1 minute each. The labels attached to the CNT0 and DLY blocks indicate the values that would make more sense in a real deployment.)

Conclusion and Further Extensions. In this application note we demonstrated how a mixed-signal platform like the GreenPAK simplifies the design of an extended battery charger with minimal external components. Several extensions to the design are possible and desirable in a robust, field-deployable system. For complete generality we may add a current sensor that triggers a state change in the CV regimes based not on time but on the current dropping below a certain value. Temperature compensation of battery voltages is an important aspect that we have not considered here. We could also do with a load-dependent voltage trigger for a new charge cycle to begin. Parameters such as AbsorbDuration, FloatDuration etc may be made to depend on the frequency of charge/discharge cycles experienced in the application. And so on. Ultimately the objective is to squeeze the maximum life out of a battery and, though lead acid batteries are almost as old as sliced bread and have been analyzed to death, they are temperamental creatures and battery life optimization is easier said than done!


  1. “Traditional float charges: are they suited to stationary antimony-free lead acid batteries?” T. M. Phuong Nguyen, Guillaume Dillenseger, Christian Glaize and Jean Alzieu, in Trends in Telecommunications Technologies, Christos J. Bouras (ed), INTECH Publishing, 2010.

About the Author

Ramkumar Ramaswamy (Ram) is an electronics engineer based in Bangalore, India. He received his MSc in Physics from the University of Delhi and his PhD in Operations Research from the Indian Institute of Management Calcutta. He has authored several technical articles.

How to Drive a Successful IoT Application Design Project

Monday, December 14th, 2015

Mladen Nizic and Brad Griffin, Cadence Design Ssystems

Internet of Things (IoT) applications are changing the way we live. They are changing how we manufacture and transport goods, deliver healthcare and other services, manage energy distribution and consumption and even how we travel and communicate. An edge-node composition is an essential element of an IoT application, providing an interface between the digital and analog worlds. Despite the diversity of IoT applications, a typical edge node includes sensors to collect information from the outside world, some amount of processing power and memory, the ability to receive and transmit information, and the ability to control devices in the immediate vicinity. Although they are modest in device counts compared to large systems on chips (SoCs), edge node devices are very complex systems that integrate analog and digital functions in silicon, package, and board and are controlled by software that must operate for many years harvesting energy or using a coin battery.

Engineers need to design, verify, and implement these edge-node systems rapidly to meet tight market windows. To achieve aggressive timelines, they need a flow that enables system prototyping, hardware/software verification, mixed-signal chip design and manufacturing, and chip/IC package/board integration. In this article, we will focus on two critical steps in the flow that impact the design cycle and the success of an entire project: 1) simulation/verification of the system/chip and 2) signal integrity analysis in chip-package-board integration.


Verification is the biggest design challenge today, particularly when analog functionality is involved, and IoT devices are no exception. High-performance analog, digital and mixed-signal simulation is indispensable but not sufficient and must be complemented by a model-based, metric-driven methodology. Key elements of the methodology are as follows:

Verification planning and management: Engineers develop verification plans and manage the plan execution carefully to filter out issues as early on as possible. A typical IoT device operates in many different modes (standby, active sensing, recharging, data processing, transmitting/receiving, test, etc.), and the functional verification plan must verify all modes and their transitions in a well-defined sequence. Since operations are controlled by embedded software, the software is ideally verified in conjunction with the hardware. It is important to understand which tests can be performed at a higher level of abstraction and which require transistor-level simulation. For example, high-level abstractions can verify that software algorithm/processor issues apply correct controls to a multiplexer selecting analog input. However, transistor-level simulation is required to verify that a built-in A-to-D converter operates correctly in a specified temperature range.

Behavioral modeling: Due to the complexity of IoT designs, executing the verification plan using transistor-level simulations is practically impossible and needs to be reserved for verifying specific electrical characteristics that require a high level of accuracy and correlation to silicon. For most functional verification planning, the investment in abstracting analog components using Verilog or VHDL behavioral models pays off by making verification much more efficient in thoroughly covering the entire system. Recent advancements in Real Number Modeling (RNM) using Verilog-AMS/wreal or SystemVerilog IEEE 1800 have made the simulation of analog, digital, and software components of an IoT system practical. Of course, modeling has to be done with a clear purpose as required by the verification plan, and the models must be in alignment with the specifications or transistor-level circuit in the case of a bottom-up design.

Coverage metrics: To assess the success of the verification of IoT designs, which are, by default, mixed-signal in nature, digital concepts of coverage metrics need to be extended to analog and mixed-signal—at least when it comes to functional verification. Using property specification language (PSL) or SystemVerilog assertions (SVAs) in conjunction with RNM simulations gives designers the ability to collect coverage, set pass/fail criteria, and evaluate the quality and completeness of the testbench, which can be used to drive improvement. This feedback loop is a major methodology improvement in comparison with the traditional direct test method.

Low-power verification: IoT devices must be extremely power efficient. To minimize power consumption, designers use advanced low-power techniques such as multiple power domains and supply voltages and power shutoffs, which help reduce active and leakage currents or completely turn off parts of the design when not needed. Power specifications captured in standard formats (like CPF or UPF-1801) can be used to ensure that power intent is implemented correctly. Designers should pay particular attention when it comes to managing the switching of power supplies to different power domains and handling analog/digital signal-crossing during power shutoffs. Dynamic CPF/UPF1801-aware mixed-signal simulation and static methods are becoming a standard part of verification methodology.

Mixed-signal simulation: High-performance, tightly integrated SPICE/FastSPICE transistor-level and digital engines supporting analog behavioral languages including RNM are at the core of the verification flow. For example, Cadence® Virtuoso®  AMS Designer is able to mix different levels of hierarchy and understand low-power specifications that make it a simulator of choice for verifying IoT designs.

The outlined methodology is well-supported by the Cadence flow as shown in Figure 1 below.

Fig. 1. Cadence flow for an IoT design

Signal Integrity Analysis

When you first consider designing an IoT device, signal and power integrity may not be the first thing that comes to mind. The focus will likely be on how this unique device will collect input, what it will produce for output, and what kinds of bells and whistles distinguish this device from competitors. However, any modern-day system, including edge-node IoT devices, must be fast, economical, and low power.

Therefore, it is a given that signals will be switching at high rates on a system that is the lowest possible cost and consumes minimal power. Like it or not, signal and power integrity is going to become part of the design challenge at some point.

Design considerations engineers need to keep in mind include:

Power management: Most IoT devices are powered by a battery. Requirements to recharge or replace that battery may make the difference in a product succeeding or failing.  The device must be designed to deliver sufficient power to all components (i.e. microcontrollers and memory) in an efficient manor while keeping low-voltage power rails stable while the device is operating.

The power delivery network (PDN) must be designed to take into account the current return path of switching signals and in a way that reduces any voltage drop due to power that is choked off as a result of congestion caused from signal vias, mounting holes, or various other causes that carve up the PDN. Maintaining stable power is a challenge. Decoupling capacitors (decaps) are used to ensure PDN stability. Space requirements and product cost create a desire to minimize the use of decaps.

The path to a successful IoT PDN design rests in utilizing analysis tools for both DC and AC analysis.  Having a tightly integrated design and analysis environment, as provided by Cadence Allegro® Sigrity™ products, provides design efficiency that saves time and engineering cost while optimizing the IoT PDN for cost and performance.

Fig. 2. Integrated side-by-side PCB design and power integrity analysis as seen in Allegro Sigrity PI Base

Memory interfaces: While sensors provide much of the input, at the heart of a typical IoT device is a microcontroller and system memory. Storing and recalling data quickly and accurately is essential to IoT functions. Dynamic RAM and some of the faster static RAM components utilize parallel bus interfaces to store and retrieve data. The data bus and the address bus provide design challenges. Simultaneous switching signals with fast-edge rates and small voltage swings create a perfect storm of opportunity for simultaneous switching noise (SSN) to impact signal quality. An IoT device used for medical assessment or a device used for military applications such as threat analysis certainly cannot afford to have unreliable data storage and retrieval.

To ensure these devices have reliable data storage and retrieval, controlled impedance and delay-tuned signal routing must be performed during design, and timing analysis must also be performed to ensure that all setup and hold conditions are met.

The path to successful memory interface design is through a constraint-driven design environment that sets both physical and electrical constraints at the logic stage of design. As physical implementation begins, dynamic rule checking that validates length and spacing rules can ensure that data signals, clock signals, address bus signals, and various control signals are routed to complicated timing specifications.

However, with the miniaturized size of many IoT devices (i.e. wearable devices), memory interface signals transition from layer to layer through vias that produce impedance discontinuities. Power-aware signal integrity analysis is required to ensure the tiny timing margins are not impacted by signal ringing, overshoot, and rippling ground reference voltages.

When signal quality issues are discovered through the analysis process, a quick path to resolution through the physical implementation tools is the key to keeping predictable IoT product development schedules.

SerDes interfaces: Many IoT devices communicate to the outside world through wireless interfaces. However, some wearable devices have a physical connector that transfers collected data to a host system. Data transfers must be fast and follow a standard interface protocol such as USB. Designing an interface so that it meets electrical compliance testing becomes part of the design requirements. The USB Implementers Forum (USB-IF) offers an integrator’s list of products that meet a set of compliance tests.  While designing these high-speed interfaces (current USB specs allow transfer speeds of up to 10Gbps), simulating compliance tests is a way to make sure designs will pass the first time.

To meet compliance specifications at high data transfer rates, reflections, crosstalk, interconnect loss, and equalization must be assessed and analyzed.

For serial links, substrate and PCB vias often create the largest impedance discontinuity on the serial link, causing potential reflections along the channel and crosstalk between channels. It can be challenging to maintain signal quality in the face of routing challenges weaving through via fields, as well as the need to transition layers through signal vias. It takes special care to craft signals to meet routing density challenges vs. “best practice” signal integrity. When crafting via transitions that need to appear virtually transparent as well as routing signals through dense via fields, maintaining signal integrity requires detailed extraction and simulation techniques while refining these physical implementation challenges.

At gigabit data rates, USB links are likely to utilize advanced equalization techniques, such as feed forward equalization (FFE) or continuous time linear equalization (CTLE).  FFE and CTLE are complex signal-processing algorithms that are implemented within semiconductor I/Os. To simulate these functions, the algorithms are mimicked in software models and implemented within simulation tools using the Algorithmic Modeling Interface (AMI) extension to the IBIS (I/O Buffer Information Sheet) standard. For USB multi-gigabit SerDes, many component vendors supply IBIS-AMI models.  However, for those vendors that do not, model creation software is available that uses predefined algorithms that can be customized through parameterization to match the performance of the component with the USB interface.

Serial links require compliance to a specific bit error rate (BER). The target BER is typically less than one error for every 10 billion bits received. Since it is not practical to simulate tens of billions of bits of data with traditional circuit simulation, high-capacity channel simulation has become part of any serial link analysis methodology. This approach applies an impulse response to characterize the serial channel and then applies advanced methods to achieve high-capacity throughput.

Having an analysis environment that can perform compliance testing while directly integrating with the implementation tools enables rapid tuning. With the ability to efficiently maximize performance of serial links during the design stage, IoT products can quickly be prototyped, tested at compliance meetings, and completed to meet aggressive time-to-market requirements.


With IoT devices being designed for a number of industries—consumer, medical, industrial, and military, just to name a few—each IoT device design team must consider the signal and power requirements  and recognize that signal and power integrity must become part of the design and analysis methodology. The competitive nature of this emerging industry means that time to market and rapid prototyping are essential to the success of a design team. Utilizing an integrated design and a signal/power analysis environment can provide IoT product creation with the highest probability of success.

Cortex-M processor Family at the Heart of IoT Systems

Saturday, October 25th, 2014

Gabe Moretti, Senior Editor

One cannot have a discussion about the semiconductor industry without hearing the word IoT.  It is really not a word as language lawyers will be ready to point out, but an abbreviation that stands for Internet of Things.  And, of course, the abbreviation is fundamentally incorrect, since the “things” will be connected in a variety of ways, not just the Internet.  In fact it is already clear that devices, grouped to form an intelligent subsystem of the IoT, will be connected using a number of protocols like: 6LoWPAN, ZigBee, WiFi, and Bluetooth.  ARM has developed the Cortex®-M processor family that is particularly well suited for providing processing power to devices that consume very low power in their duties of physical data acquisition. This is an instrumental function of the IoT.

Figure 1. The heterogeneous IoT: lots of “things” inter-connected. (Courtesy of ARM)

Figure 1 shows the vision the semiconductor industry holds of the IoT.  I believe that the figure shows a goal the industry set for itself, and a very ambitious goal it is.  At the moment the complete architecture of the IoT is undefined, and rightly so.  The IoT re-introduces a paradigm first used when ASIC devices were thought of being the ultimate solution to everyone’s computational requirements.  The business of IP started  as an enhancement to application-specific hardware, and now general purpose platforms constitute the core of most systems.  IoT lets the application drive the architecture, and companies like ARM provide the core computational block with an off-the-shelf device like a Cortex MCU.

The ARM Cortex-M processor family is a range of scalable and compatible, energy efficient, easy to use processors designed to help developers meet the needs of tomorrow’s smart and connected embedded applications. Those demands include delivering more features at a lower cost, increasing connectivity, better code reuse and improved energy efficiency. The ARM Cortex-M7 processor is the most recent and highest performance member of the Cortex-M processor family. But where the Cortex-M7 is at the heart of ARM partner SoCs for IoT systems, other connectivity IP is required to complete the intelligent SoC subsystem.

A collection of some of my favorite IoT-related IP follows.

Figure 2. The Cortex-M7 Architecture (Courtesy of ARM)

Development Ecosystem

To efficiently build a system, no matter how small, that can communicate with other devices, one needs IP.  ARM and Cadence Design Systems have had a long-standing collaboration in the area of both IP and development tools.  In September of this year the companies extended an already existing agreement covering more than 130 IP blocks and software.  The new agreement covers an expanded collaboration for IoT and wearable devices targeting TSMC’s ultra-low power technology platform. The collaboration is expected to enable the rapid development of IoT and wearable devices by optimizing the system integration of ARM IP and Cadence’s integrated flow for mixed-signal design and verification.

The partnership will deliver reference designs and physical design knowledge to integrate ARM Cortex processors, ARM CoreLink system IP, and ARM Artisan physical IP along with RF/analog/mixed-signal IP and embedded flash in the Virtuoso-VDI Mixed-Signal Open Access integrated flow for the TSMC process technology.

“The reduction in leakage of TSMC’s new ULP technology platform combined with the proven power-efficiency of Cortex-M processors will enable a vast range of devices to operate in ultra energy-constrained environments,” said Richard York, vice president of embedded segment marketing, ARM. “Our collaboration with Cadence enables designers to continue developing the most innovative IoT devices in the market.”  One of the fundamental changes in design methodology is the aggregation of capabilities from different vendors into one distribution point, like ARM, that serve as the guarantor of a proven development environment.

Communication and Security

System developers need to know that there are a number of sources of IP when deciding on the architecture of a product.  In the case of IoT it is necessary to address both the transmission capabilities and the security of the data.

As a strong partner of ARM Synopsys provides low power IP that supports a wide range of low power features such as configurable shutdown and power modes. The DesignWare family of IP offers both digital and analog components that can be integrated with any Cortex-M MCU.  Beyond the extensive list of digital logic, analog IP including ADCs and DACs, plus audio CODECs play an important role in IoT applications. Designers also have the opportunity to use Synopsys development and verification tools that have a strong track record handling ARM based designs.

The Tensilica group at Cadence has published a paper describing how to use Cadence IP to develop a Wi-Fi 802.11ac transceiver used for WLAN (wireless local area network). This transceiver design is architected on a programmable platform consisting of Tensilica DSPs, using an anchor DSP from the ConnX BBE family of cores in combination with a smaller specialized DSP and dedicated hardware RTL. Because of the enhanced instruction set in the Cortex-M7 and superscalar pipeline, plus the addition of floating point DSP, Cadence radio IP works well with the Cortex-M7 MCU as intermediate band, digital down conversion, post-processing or WLAN provisioning can be done by the Cortex-M7.

Accent S.A. is an Italian company that is focused on RF products.  Accent’s BASEsoc RF Platform for ARM enables pre-optimized, field-proven single chip wireless systems by serving as near-finished solutions for a number of applications.  This modular platform is easily customizable and supports integration of different wireless standards, such as ZigBee, Bluetooth, RFID and UWB, allowing customers to achieve a shorter time-to-market. The company claims that an ARM processor-based, complex RF-IC could be fully specified, developed and ramped to volume production by Accent in less than nine months.

Sonics offers a network on chip (NoC) solution that is both flexible in integrating various communication protocols and highly secure.   Figure 3 shows how the Sonics NoC provides secure communication in any SoC architecture.

Figure 3.  Security is Paramount in Data Transmission (Courtesy of Sonics)

According to Drew Wingard, Sonics CTO “Security is one of the most important, if not the most important, considerations when creating IoT-focused SoCs that collect sensitive information or control expensive equipment and/or resources. ARM’s TrustZone does a good job securing the computing part of the system, but what about the communications, media and sensor/motor subsystems? SoC security goes well beyond the CPU and operating system. SoC designers need a way to ensure complete security for their entire design.”

Drew concludes “The best way to accomplish SoC-wide security is by leveraging on-chip network fabrics like SonicsGN, which has built-in NoCLock features to provide independent, mutually secure domains that enable designers to isolate each subsystem’s shared resources. By minimizing the amount of secure hardware and software in each domain, NoCLock extends ARM TrustZone to provide increased protection and reliability, ensuring that subsystem-level security defects cannot be exploited to compromise the entire system.”

More examples exist of course and this is not an exhaustive list of devices supporting protocols that can be used in the intelligent home architecture.  The intelligent home, together with wearable medical devices, is the most frequent example of IoT that could be implemented by 2020.  In fact it is a sure bet to say that by the time the intelligent home is a reality many more IP blocks to support the application will be available.

Complexity of Mixed-signal Designs

Thursday, August 28th, 2014

Gabe Moretti, Senior Editor

The major constituent of system complexity today is the integration of computing with mechanical and human interfaces.  Both of these are analog in nature, so designing mixed-signal systems is a necessity.  The entire semiconductor chain is impacted by this requirement.  EDA tools must support mixed-signal development and the semiconductor foundries must adapt to using different processes to build one IC.

Impact on Semiconductor Foundries

Jonah McLeod, Director of Corporate Marketing Communications at Kilopass Technology was well informed about foundries situation when ARM processors became widely used in mixed-signal designs.  He told me that: ” Starting in 2012 with the appearance of smart meters, chip vendors such as NXP began integrating the 32-bit ARM Cortex processor with a analog/mixed-signal metrology engine for Smart Metering with two current inputs and a voltage input.

This integration had significant impact on both foundries and analog chip suppliers. The latter had been fabricating mixed-signal chips on process nodes of 180nm and larger, many with their own dedicated fabs. With this integration, they had to incorporate digital logic with their analog designs.

Large semiconductor IDMs like NXP, IT and ST had an advantage over dedicated chip companies like Linear and Analog Devices. The former had both logic and analog design expertise they could bring to bear building these SoCs and they had the fabrication expertise to build digital mixed-signal processes in smaller process geometries.

Long exempt from the pressure to chase smaller process geometries aggressively, the dedicated analog chip companies had a stark choice. They could invest the large capital expenditure required to build smaller geometry fabs or they could go fablite and outsource smaller process geometry designs to the major fabs. This was a major boost for the foundries that needed designs to fill fabs abandoned by digital designs chasing first 40nm and now 28nm. As a result, ffoundries now have 55nm processes tailored for power management ICs (PMICs) and display driver ICs, among others. Analog expertise still counts in this new world order but the competitive advantage goes to analog/mixed-signal design teams able to leverage smaller process geometries to achieve cost savings over competitors.”

As form factors in handheld and IoT devices become increasingly smaller, integrating all the components of a system on one IC becomes a necessity.  Thus fabricating mixed-signal chips with smaller geometries processes grows significantly in importance.

Mladen Nizic, Product Marketing Director at cadence noted that requirements on foundries are directly connected to new requirements for EDA tools.  He observed that: “Advanced process nodes typically introduce more parametric variation, Layout Dependent Effects (LDE), increased impact of parasitics, aging and reliability issues, layout restrictions and other manufacturing effects affecting device performance, making it much harder for designers to predict circuit performance in silicon. To cope with these challenges, designers need automated flow to understand impact of manufacturing effects early, sensitivity analysis to identify most critical devices, rapid analog prototyping to explore layout configurations quickly, constraint driven methodology to guide layout creation and in-design extraction and analysis to enable correct-by-construction design. Moreover, digital-assisted-analog has common approach in achieving analog performance, leading to increased need for integrate mixed-signal design flow.”

Marco Casale-Rossi, Senior Staff Product Marketing Manager, Design Group, Synopsys points out that there is still much life remaining in the 180nm process.  ”I’ll give you the 180 nanometer example: when 180 nanometers was introduced as an emerging technology node back in 1999, it offered single-poly, 6 aluminum metals, digital CMOS transistors and embedded SRAM memory only. Today, 180 nanometers is used for state-of-the-art BCD (Bipolar-CMOS-DMOS) processes, e.g. for smartpower, automotive, security, MCU applications; it features, as I said, bipolar, CMOS and DMOS devices, double-poly, triple-well, four aluminum layers, integrating a broad catalogue of memories such as DRAM, EEPROM, FLASH, OTP, nad more.   Power supplies span from 1V to several tens or even hundreds of Volts; analog & mixed-signal manufacturing processes at established technology nodes are as complex as the latest and greatest digital manufacturing processes at emerging technology nodes, only the metrics of complexity are different.”

EDA Tools and Design Flow

Mixed-signal designs require a more complex flow than strictly digital designs.  They often incorporate multiple analog, RF, mixed-signal, memory and logic blocks operating at high performance and different power domains.  For these reasons engineers designing a mixed-signal IC need different tools throughout the development process.  Architecting, developing testing and place and route functions are all impacted.

Mladen observed that “Mixed-signal chip architects must explore different configurations with all concerned in a design team to avoid costly, late iterations. Designers consider many factors like block placement relative to each other, IO locations, power grid and sensitive analog routes, noise avoidance to arrive to optimal chip architecture.”

Standard organizations, particularly Accellera and the IEEE have developed versions of generally used HD languages like Verilog and VHDL that provide support for mixed-signal descriptions.  VHDL-AMS and Verilog-AMS continue to be supported by the IEEE and working groups are making sure that the needs of designers are met.

Mladen points out that “recent extensions in standardization efforts for Real Number Modeling (RNM) enable effective abstraction of analog for simulation and functional verification almost at digital speeds.    Cadence provides tools for automating analog behavioral and RNM model generation and validation. In last couple of years, adoption of RNM is on rise driven by verification challenges of complex mixed-signal designs.”

Design verification is practically always the costlier part of development.  This is partly due to the lack of effective correct by construction tools and obviously by the increasing complexity of designs that are often a product of various company design teams as well as the use of third party IP.

Steve Smith, Sr. Marketing Director, Analog/Mixed-signal Verification at Synopsyspointed out that: “The need for exhaustive verification of mixed-signal SoCs means that verification teams need perform mixed-signal simulation as part of their automated design regression test processes. To achieve this requirement, mixed-signal verification is increasingly adopting techniques that have been well proven in the purely digital design arena. These techniques include automated stimulus generation, coverage and assertion- driven verification combined with low-power verification extended to support analog and mixed-signal functionality.  As analog/mixed-signal design circuits are developed, design teams will selectively replace high-level models for the SPICE netlist and utilize the high performance and capacity of a FastSPICE simulator coupled to a high-performance digital simulator. This combination provides acceleration for mixed-signal simulation with SPICE-like accuracy to adequately verify the full design. Another benefit of using FastSPICE in this context is post-layout simulation for design signoff within the same verification testbench environment.”

He continued by saying that: “An adjacent aspect of the tighter integration between analog and digital relates to power management – as mixed-signal designs require multiple power domains, low-power verification is becoming more critical. As a result of these growing challenges, design teams are extending proven digital verification methodologies to mixed-signal design.  Accurate and efficient low-power and multiple power domain verification require both knowledge of the overall system’s power intent and careful tracking of signals crossing these power domains. Mixed-signal verification tools are available to perform a comprehensive set of static (rule-based) and dynamic (simulation run-time) circuit checks to quickly identify electric rule violations and power management design errors. With this technology, mixed-signal designers can identify violations such as missing level shifters, leakage paths or power-up checks at the SoC level and avoid significant design errors before tape-out. During detailed mixed-signal verification, these run-time checks can be orchestrated alongside other functional and parametric checks to ensure thorough verification coverage.”

Another significant challenge to designers is placing and routing the design.  Mladen described the way Cadence supports this task.  “Analog designers use digital logic to calibrate and tune their high performance circuits. This is called digitally-assisted-analog approach. There are often tens of thousands of gates integrated with analog in a mixed-signal block, at periphery making it ready for integration to SOC as well as embedded inside the hierarchy of the block. Challenges in realizing this kind of designs are:

- time and effort needed for iteration among analog and digital designers,

- black-boxing among analog and digital domains with no transparency during the iterations,

- sharing data and constraints among analog and digital designers,

- performing ECO particularly late in the design cycle,

- applying static timing analysis across timing paths spanning gates embedded in hierarchy of mixed-signal block(s).

Cadence has addressed these challenges by integrating Virtuoso custom and Encounter digital platforms on common OpenAccess database enabling data and constraint sharing without translation, full transparency in analog and digital parts of layout in both platforms.”

Casale-Rossi has described how Synopsys addresses the problem.  “A&M/S has always had placement (e.g. symmetry, rotation) and routing (e.g. shielding, length/resistance matching) special requirements. With Synopsys’ Custom Designer – IC Compiler round-trip, and with our Galaxy Custom Router, we are providing our partners and customers with an integrated environment for digital and analog & mixed-signal design implementation that helps address the challenges.”


The bottom line is that EDA tools providers, standards developing organization and semiconductor foundries have significant further work to do.  IC complexity will increase and with it mixed-signal designs.  Mixed-signal third party IP is by nature directly connected to a specific foundry and process since it must be developed and verified at the transistor level.  Thus the complexity of integrating IP development and fabrication will limit the number of IP providers to those companies big enough to obtain the attention of the foundry.

Analog Designers Face Low Power Challenges

Monday, June 16th, 2014

By John Blyler, Chief Content Officer

Can mixed signal designs achieve the low power needed by today’s tightly integrated SoCs and embedded IoT communication systems?

System level power budgets are affected by SoC integration. Setting aside the digital scaling benefits of smaller geometric nodes, leading edge SoCs achieve higher performance and tighter integration with decreased voltage levels at a cost. If power is assumed to be constant, then that cost is the increased current flow (P=VI) delivered to an ever larger number of processor cores. That’s why SoC power delivery and distribution remain a major challenge for chip architects, designers and verification engineers.

As with digital engineers, analog and mixed signal power designers must consider ways to lower power consumption early in the design phase. Beyond that consideration, there are several common ways to reduce the analog mixed signal portion of a power budget. These ways include low-power transmitter architectures; analog signal processing in low-voltage domains; and sleep mode power reduction. (ARM’s Diya Soubra takes about mixed signal sleep modes in, “Digital Designers Grapple with Analog Mixed Signal Designs.”)

To efficiently explore the design space and make basic system-level trade-offs, SoC architects must adapt their modeling style to accommodate mixed-signal design and verification techniques. Such early efforts will also help prevent overdesign in which globally distributed and cross-discipline (digital and analog) design teams don’t share information. For example, if designers are creating company-specific intellectual property (IP) cores, then they may not be aware how various IP subsystems are being used at the full chip level.

Similarly, SoC package level designers must also understand how IP is used at the higher board level. Without this information, designers tend to over compensate their portion of the design, i.e., over design to ensure their portion of the design stays within the allocated power budget. But that leads to increased cost and power consumption.

Power Modes

From an architectural viewpoint, power systems really have two categories; active and idle/standby modes. With all of the physical level (PHY) link integration occurring on SoCs, active power considerations must apply not only to digital but also analog and input-output power designs.

Within the modes of active and idle/standby power are the many power states needed to balance the current load amongst various voltage islands. With increased performance and power demands on both digital and analog designs, there is growing interest in Time- and Frequency-Domain Power Distribution (or Delivery) Network (PDN) analysis. Vic Kulkarni, VP and GM at Apache Design, believes that a careful power budgeting at a high level enables the efficient design of the power delivery network in the downstream design flow. (See, “System Level Power Budgeting.”)

SoC power must be modeled throughout all aspects of the design implementation.  Although one single modeling approach won’t work, a number of vertical markets like automotive have found success using virtual prototypes.  “System virtual prototypes are increasingly a mix – not just of hardware and software, but also of digital, control, and analog components integrated with many different sensors and actuators,” observed Arun Mulpur of The Mathworks. (See, “Chip, Boards and Beyond: Modeling Hardware and Software.”)

Communications Modes

Next to driving a device screen or display, the communication subsystem tends to consume the most power on a SoC. That’s why several low power initiatives have recently arisen like Bluetooth Low Energy. Today there are three mainstream standards for Bluetooth in use – Bluetooth 2.0 (often referred to as Bluetooth Classic), Bluetooth 4.0, which offers both a standard high-speed mode and a low-energy mode with limited data rate referred to Bluetooth LE; and a single-mode Bluetooth LE standard that keeps power consumption to a minimum.  (See, “Wearable Technologies Meet Bluetooth Low Energy.”)

Power profiling of software is an important part of designing for cellular embedded systems. But cellular is only one connectivity option when designing the SoC or board level device. Other communication types include short range subsystems, Bluetooth, Zigbee, 6LowPAN and mesh networks. If Wi-Fi connectivity is needed, then there will be choices for fixed LAN connected things using Ethernet or proprietary cabling systems. Further, there will be interplay amongst all this different ways to connect that must be simulated at an overall system-level.  (See, “Cellular vs. WiFi Embedded Design.”)

It has only been in the last decade or so that mixed signal systems have played a more dominant role in system level power budgets. Today’s trend toward a highly connected, Internet-of-Things world (IoT) means that low power, mixed signal communication design must begin early in the design phase to be considered part of the overall system-level power management process.

Digital Designers Grapple with Analog Mixed Signal Designs

Tuesday, June 10th, 2014

By John Blyler, Chief Content Officer

Today’s growth of analog and mixed signal circuits in the Internet of Things (IoT) applications raises questions about compiling C-code, running simulations, low power designs, latency and IP integration.

Often, the most valuable portion of a technical seminar is found in the question-and-answer (Q&A) session that follows the actual presentation. For me, that was true during a recent talk on the creation of mixed signal devices for smart analog and the Internet of Things (IoT) applications. The speakers included Diya Soubra, CPU Product Marketing Manager and Joel Rosenberg, Platform Marketing Director at ARM; and Mladen Nizic, Engineering Director at Cadence. What follows is my paraphrasing of the Q&A session with reference to the presentation where appropriate. – JB

Question: Is it possible to run C and assembly code on an ARM® Cortex®-M0 processor in Cadence’s Virtuoso for custom IC design? Is there a C-compiler within the tool?

Nizic: The C compiler comes from Keil®, ARM’s software development kit. The ARM DS-5 Development Studio is an Eclipse based tool suite for the company’s processors and SoCs. Once the code is compiled, it is run together with RTL software in our (Cadence) Incisive Mixed Signal simulator. The result is a simulation of the processor driven by an instruction set with all digital peripherals simulated in RTL or at the gate level. The analog portions of the design are simulated at the appropriate behavioral level, i.e., Spice transistor level, electrical behavioral Verilog A or a real number model. [See the mixed signal trends section of, “Moore’s Cycle, Fifth Horseman, Mixed Signals, and IP Stress”)

You can use the electrical behavioral models like a Verilog A and VHDL-A and –AMS to simulate the analog portions of the design. But real number models have become increasingly popular for this task. With real number models, you can model analog signals with variable amplitudes but discrete time steps, just as required by digital simulation. Simulations with a real number model representation for analog are done at almost the same speed as the digital simulation and with very little penalty (in accuracy). For example, here (see Figure 1) are the results of a system simulation where we verify how quickly Cortex-M0 would us a regulation signal to bring pressure to a specified value. It takes some 28-clock cycles. Other test bench scenarios might be explored, e.g., sending the Cortex-M0 into sleep mode if no changes in pressure are detected or waking up the processor in a few clock cycles to stabilize the system. The point is that you can swap these real number models for electrical models in Verilog A or for transistor models to redo your simulation to verify that the transistor model performs as expected.

Figure 1: The results of a Cadence simulation to verify the accuracy of a Cortex-M0 to regulate a pressure monitoring system. (Courtesy of Cadence)

Question: Can you give some examples of applications where products are incorporating analog capabilities and how they are using them?

Soubra: Everything related to motor control, power conversion and power control are good examples of where adding a little bit of (processor) smarts placed next to the mixed signal input can make a big difference. This is a clear case of how the industry is shifting toward this analog integration.

Question: What capabilities does ARM offer to support the low power requirement for mixed signal SoC design?

Rosenberg: The answer to this question has both a memory and logic component. In terms of memory, we offer the extended range register file compilers which today can go up to 256k bits. Even though the performance requirement for a given application may be relatively low, the user will want to boot from the flash into the SRAM or the register file instance. Then they will shut down the flash and execute out of the RAM as the RAM offers significantly lower active as well as stand-by power compared to executing out of flash.

On the logic side, we offer a selection from 7, 9 and 12 tracks. Within that, there are three Vt options – one for high, nominal and lower speeds. Beyond that we also offer power management kits that provide things like level shifters and power gating so the user can shut down none active parts of the SoC circuit.

Question: What are the latency numbers for waking up different domains that have been put to sleep?

Soubra: The numbers that I shared during the presentation do not include any peripherals since I have no way of knowing what peripherals will be added. In terms of who is consuming what power, the normal progression tends to be the processor, peripherals, bus and then the flash block. The “wake-up” state latency depends upon the implementation itself. You can go from tens-of-cycles to multiple-of-tens depending upon how the clocks and phase locked loops (PLLs) are implemented. If we shut everything down, then a few cycles will be required before everything goes off an, before we can restart the processor. But we are talking about tens not hundreds of cycles.

Question: And for the wake-up clock latency?

Soubra: Wake-up is the same thing, because when the wake-up controller says “lets go,” it has to restart all the clocks before it starts the processor. So it is exactly the same amount.

ARM Cortex-M low power technologies.

Question: What analog intellectual property (IP) components are offered by ARM and Cadence? How can designers integrate their own IP in the flow?

Nizic: At Cadence, through the acquisition of Cosmic, we have a portfolio of applicable analog and mixed signal IP, e.g., converters, sensors and the like. We support all design views that are necessary for this kind of methodology including model abstracts from real number to behavioral models. Like ARM’s physical IP, all of ours are qualified for the various foundry nodes so the process of integrating IP and silicon is fairly smooth.

Soubra: From ARM’s point-of-view, we are totally focused on the digital part of the SoC, including the processors, bus infrastructure components, peripherals, and memory controllers that are part of the physical IP (standard cell libraries, I/O cells, SRAM, etc). Designers integrate the digital parts (processors, bus components, peripherals and memory controller) in RTL design stages. Also, they can add the functional simulation models of memories and I/O cells in simulations, together with models of analog components from Cadence. The actual physical IP are integrated during various implementation stages (synthesis, placement and routing, etc).

Question: How can designers integrate their own IP into the SoC?

Nizic: Some of the capabilities and flows that we described are actually used to create customer IP for later reuse in SoC integration. There is a centric flow that can be used, whether the customer’s IP is pure analog or contains a small amount of standard cell digital. For example, the behavioral modeling capabilities help package this IP for the functional simulation in full chip verification. But getting the IP ready is only one aspect of the flow.

From a physical abstract it’s possible to characterize the IP for use in timing driven mode. This approach would allow you to physically verify the IP on the SoC for full chip verification.

What Powers the IoT?

Wednesday, October 16th, 2013

By Stephan Ohr, Gartner

Powering the Internet of Things (IoT) is a special challenge, says Gartner analyst Stephan Ohr, especially for the wireless sensor nodes (WSNs) that must collect and report data on their environmental states (temperature, pressure, humidity, vibration and the like). While the majority of WSNs will harness nearby power sources and batteries, there will be as many as 10% of the sensor nodes that must be entirely self-powering. Often located in places where it is difficult or impossible to replace batteries, these remote sensor nodes must continue to function for 20 years or more.

Two research and development efforts focus on self-powering remote sensor nodes: One effort looks at energy harvesting devices, which gather power from ambient sources. The major types of energy harvesting devices include specialized solar cells, vibration and motion energy harvesters, and devices that take advantage of thermal gradients warm and cool surfaces. Research and development concentrated on reducing the size and cost of these devices, and making their energy gathering more efficient. But even in their current state of development, these devices could add up to a half-billion in revenues per year within the next five years.

The other R&D effort concentrates on low-power analog semiconductors which will elevate the milli-volt outputs of energy harvesting devices to the levels necessary for powering sensors, microcontrollers, and wireless transceivers. These devices include DC-DC boost converters, sensor signal conditioning amplifiers, and, in some cases, data converter ICs which transform the analog sensor signals to digital patterns the microcontroller can utilize. Broadline analog suppliers like Linear Technology Corp. and Analog Devices have added low-power ICs to their product portfolios. In addition to boosting low-level signals, they use very little power themselves. LTC’s low-power parts, for example, have a quiescent current rating of 1.3 micro-amps. Other companies liked Advanced Linear Devices (ALD) have been working on low-threshold electronics for years, and Texas Instruments has a lineup of specialized power management devices for WSN applications.

Ohr’s projections on energy harvesting will be part of his talk on “Powering the Internet of Things” at the Sainte Claire Hotel, San Jose, CA on October 24, 2013. (Admission is free, but advance registration is required The Internet of Things – A Disruption and an Evolution)

Source: Gartner Research (Oct 2013)

Stephan (“Steve”) Ohr is the Research Director for Analog ICs, Sensors and Power Management devices at Gartner, Inc., and focuses on markets that promise semiconductor revenue growth. His recent reports have explored custom power management ICs for smart phones and tablets, the impact of Apple’s choices on the MEMs sensor industry, and a competitive landscape for MEMs sensor suppliers.

Ohr’s engineering degree, a BS in Industrial Engineering, comes from the New Jersey Institute of Technology (the Newark College of Engineering) and his graduate degree, an MA in sociology, comes from Rutgers.

Mixed Signal and Microcontrollers Enable IoT

Wednesday, October 16th, 2013

By John Blyler

The Internet of Things (IoT) has become such a hot topic that many business and technical experts see it as a key enabler for the fourth industrial revolution – following the steam engine, the conveyor belt and the first phase of IT automation technology (McKinsey Report). Still, for all the hype, the IoT concept seems hard to define.

From a technical standpoint, the IoT refers to the information system that uses smart sensors and embedded systems that connect wired or wirelessly via Internet protocols. ARM defines IoT as, “a collection of smart, sensor-enabled physical objects, and the networks, servers and services that interact with them. It is a trend and not a single sector or market.” How do these interpretations relate to the real world?

“There are two ways in which the “things” in the IoT interact with the physical world around us,” explains Diya Soubra, CPU Product Manager for ARM’s Processor Division. “First they convert physical (analog) data into information and second they act in the physical world based on information. An example of the first way is a temperature sensor that reports temperature while an example of the second way is a door lock opens upon receiving a text message.”

For many in the chip design and embedded space, IoT seems like the latest iteration of the computer-communication convergence heralded from the last decade. But this time, a new element has been added to the mix, namely, sensor systems. This addition means that the role of analog and mixed signal system must now extend beyond RF and wireless devices to include smart sensors. This combination of analog mixed signal, RF-wireless and digital microcontrollers has increase the complexity and confusion among chip, board, package and end product semiconductor developers.

“Microcontrollers (MCUs) targeting IoT applications are becoming analog-intensive due to sensors, AD converters, RF, Power Management and other analog interfaces and modules that they integrate in addition to digital processor and memory,” says Mladen Nizic, Engineering Director for Mixed Signal Solutions at Cadence Design Systems. “Therefore, challenges and methodology are determined not by the processor, but by what is being integrated around it. This makes it difficult for digital designers to integrate such large amounts of analog. Often, analog or mixed-signal skills need to be in charge of SoC integration, or the digital and analog designer must work very closely to realize the system in silicon.”

The connected devices that make up the IoT must be able to communicate via the Internet. This means the addition of wired or wireless analog functionality to the sensors and devices. But a microcontroller is needed to convert the analog signal to digital and to run the Internet Protocol software stacks. This is why IoT requires a mix of digital (Internet) and analog (physical world) integration.

Team Players?

Just how difficult is it for designers – especially digital – to incorporate analog and mix signal functionality into their SoCs? Soubra puts it this way (see Figure 1): “In the market, these are two distinct disciplines. Analogue is much harder to design and has its set of custom tools. Digital is easier since it is simpler to design, and it has its own tools. In the past (prior to the emergence of IoT devices), Team A designed the digital part of the system while Team B designed the analog part separately. Then, these two distinct subsystems where combined and tested to see which one failed. Upon failure, both teams adjusted their designs and the process was repeated until the system worked as a whole. These different groups using different tools resulted in a lengthy, time consuming process.”

Contrast that approach with the current design cycle where the entire mixed signal designers (Teams A and B) work together from the start as one project using one tool and one team. All tool vendors have offerings to do this today. New tools allow viewing the digital and analog parts at various levels and allow mixed simulations. Every year, the tools become more sophisticated to handle ever more complex designs.

Figure 1: Concurrent, OA-based mixed-signal implementations. (Courtesy of Cadence)

Simulation and IP

Today, all of the major chip- and board-level EDA and IP tool vendors have modeling and simulation tools that support mixed signal designs directly (see Figure 2).

Figure 2: Block diagram of pressures-temperature control and simulation system. (Courtesy Cadence)

Verification of the growing analog mixed-signal portion of SoCs is leading to better behavioral models, which abstract the analog upward to the register transfer level (RTL). This improvement provides a more consistent handoff between the analog and digital boundaries. Another improvement is the use of real number models (RNMs), which enable the discrete time transformations needed for pure digital solver simulation of analog mixed-signal verification. This approach enables faster simulation speeds for event-driven real-time models – a benefit over behavioral models like Verilog-A.

AMS simulations are also using assertion techniques to improve verification – especially in interface testing. Another important trend is the use of statistical analysis to handle both the analog nature of mixed signals and the increasing number of operational modes. (See, “Moore’s Cycle, Fifth Horseman, Mixed Signals, and IP Stress”).

Figure: Cadence’s Mladen Nizic (background right) talk about mixed-signal technology with John Blyler. (Photo courtesy of Lani Wong)

For digital designers, there is a lot to learn in the integration of analog systems. However, the availability of ready-to-use analog IP does make it much easier than in the past. That’s one reason why the analog IP market has grown considerable in the last several years and will continue that trend. As reported earlier this year, the wireless chip market will be the leading growth segment for the semiconductor industry in 2013, predicts IHS iSuppli Semiconductor (“Semiconductor Growth Turns Wireless”).

The report states that original-equipment-manufacturer (OEM) spending on semiconductors for wireless applications will rise by 13.5% this year to reach a value of $69.6 billion – up from $62.3 billion in 2012.

The design and development of wireless and cellular chips – part of the IoT connectivity equation – reflects a continuing need for related semiconductor IP. All wireless devices and cell phones rely on RF and analog mixed-signal (AMS) integrated circuits to convert radio signals into digital data, which can be passed to a baseband processor for data processing. That’s why a “wireless” search on the website reveals list after list of IP companies providing MIPI controllers, ADCs, DACs, PHY and MAC cores, LNAs, PAs, mixers, PLLs, VCOs, audio/video codecs, Viterbi encoders/decoders, and more.

Real-World Examples

“Many traditional analog parts are adding more intelligence to the design and some of them use microcontrollers to do so,” observes Joseph Yiu, Embedded Technology Specialist at ARM. “One example is an SoC from Analog Device (ADuCM360) that contains a 24-bit data acquisition system with multichannel analog-to-digital converters (ADCs), an 32-bit ARM Cortex-M3 processor, and Flash/EE memory. Direct interfacing is provided to external sensors in both wired and battery-powered applications.”

But, as Soubra mentioned earlier, the second way in which the IoT interacts with the physical world is to act on information – in other words, through the use of digital-to-analog converters (DACs). An example of a chip that converts digital signals back to the physical analog world is SmartBond DA14580. This System-on-Chip (SoC) is used to connect keyboards, mice and remote controls wirelessly to tablets, laptops and smart TVs. It consists of Bluetooth subsystem, a 32 -bit ARM Cortex M0 microcontroller, antenna connection and GPIO interfaces.

Challenges Ahead

In addition to tools that simulated both analog, mixed signal and digital designs, perhaps the next most critical challenge in IoT hardware and software development is the lack of standards.

“The industry needs to converge on the standard(s) on communications for IoT applications to enable information flow among different type of devices,” stressed Wang, software will be the key to the flourish of IoT applications, as demonstrated by ARM’s recent acquisition of Sensinode.” A Finnish software company, Sensinode builds a variation of the Internet Protocols (IP) designed for IoT device connection. Specifically, the company develops to the 6LoWPAN standard, a compression format for IPv6 that is designed for low-power, low-bandwidth wireless links.

If IoT devices are to receive widespread adoption by consumers, then security of the data collected and acted upon by these devices must be robust. (Security will be covered in future articles).

Analog and digital integration, interface and communication standards, and system-level security have always been challenges faced by leading edge designers. The only thing that changes is the increasing complexity of the designs. With the dawning of the IoT, that complexity will spread from every physical world sensor node to every cloud-based server receiving data from or transmitting to that node. Perhaps this complexity spreading will ultimately be the biggest challenge faced by today’s intrepid designers.

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