Cadence’s Axel Scherer revs up a sandboxed functional verification course where no installation is required. But does the second “B” in “BYOB” stand for browser or bike?

Mentor’s Andrew Patterson details some principles for connected infotainment. Rule No. 1: The driver should normally be looking forward. The Doors said something similar in the opening line of “Roadhouse Blues.”

Synopsys’ Parag Goel summarizes technical papers submitted at the Synopsys User Group (SNUG) last year, this batch focused on UVM and VMM. There has been a lot of talk about UVM these days, and with verification challenges on the rise there will be a lot more.

Real Intent’s Graham Bell pulls some interesting highlights out of the DVCon keynote speech by Mentor CEO Wally Rhines last week. So much for new acquisitions.

In similar vein, Cadence’s Richard Goering reports on a DVCon panel about verification planning. If you’re looking for best practices in verification, there’s a bunch here.

Mentor’s Colin Walls details a unique business proposal—free software until you can afford to pay for it. That’s a new twist on the buy now, pay later model.

Cadence’s Jeffrey Gallagher drills down, so to speak, into NC outputs for systems in package and stacked die in APD layers. If you’ve looked at the lithography roadmap lately, you might want to start paying attention to this stuff.

Synopsys’ Helene Thibieroz interviews top engineers at Maxim and Orora Design about behavioral modeling for analog/mixed signal, and why it’s so important for speeding up the verification process.

And in case you missed last week’s System-Level Design newsletter, here are some blogs worth noting:

—Synopsys’ Nithya Ruff questions why engineering teams postpone developing software.

—Cadence’s Frank Schirrmeister points out that developing tools for the Internet of Things isn’t as simple as it sounds.

—Arteris’ Kurt Shuler rolls out a list of best practices for adding flexibility into designs.

—Sonics’ Frank Ferro questions whether smart phone makers are listening to their customers.

—And Real Intent’s Graham Bell looks into the idea of automatic formal checks for verification.

By Ed Sperling
SoC design has largely been a race to the next process node in accordance with Moore’s Law, but it’s about to take a sharp turn away from that as the Internet of Things becomes more ubiquitous.

There has been much made about the Internet of Things over the past couple of years—home networks that involve smart refrigerators sending reminders to consumers that the milk is outdated. While this gee-whiz stuff grabs headlines, the reality is that the chips that drive these devices are hardly at the leading edge of design. Some of them date back to the half-micron processes, where things like layout-dependent effects, electromigration and finFETs aren’t even relevant.

But that’s only part of the picture. The real challenge to making this all work is much less about the wonders of technology and more about basic efficiency and cost in familiar areas such as network management, I/O, integration with mobile devices and software that can fuse it all together. And the real killer application appears to be the automobile, where the ability to eke out an extra 5 or 10 miles per gallon and to stay connected by voice without removing your hands from the wheel or your eyes from the road is critical to safety.

“This enters into the world of complex systems because you have to be able to simulate large numbers of things interacting together,” said Wally Rhines, chairman and CEO of Mentor Graphics. “The complexity increases at least as the square of the number of components. If you count the interactions, as long as you have a limited number of air-pressure sensors, light sensors, motion sensors, you can have dedicated signal processing for each of those sensors. As they start interacting, those interactions have to be verified and analyzed.”

Adding to the challenge, what is developed today may not be what it’s used for next year.

“You put out a network of 100 sensors and you’re worried about the interaction between them and the host,” said Rhines. “And then you decide that you’re going to do some other kind of interaction between sensors. That adds to the complexity.

The Internet of Things also relies heavily on analog at the front end—the part that senses and measures what’s going on around us—tied into a number-crunching digital back end. From a design standpoint, this is nothing new. But the challenge is how you manage all the data collected by these analog sensors without overloading the networks and the servers that need to make sense out of all of this—and still do it in an efficient manner with sufficient performance.

“You can’t just transmit all the data that you collect,” said Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence. “It’s more of the client/server approach. The bandwidth is not there to deal with that. Bandwidth is certainly growing, but the amount of data is growing much faster than the bandwidth. That means you have to be smarter at the node. This is why every LED has about 800 bytes of software code. In the future, they’ll probably also be adding IP addresses, which will require more code.”

This doesn’t necessarily require new EDA tools, but it may require thinking about how to use them differently. Simulations need to be run not just for what is there today, but in a virtualized environment to understand future uses and the resulting corner cases that might result. Just as traffic on a chip can cause issues, traffic between chips on an ad hoc basis can cause similar problems. To a large extent, this requires thinking of network-connected platforms rather than chips, but ones that are cheap enough and small enough to fit in lots of different devices.

“You see this with the ARM M series,” said Schirrmeister. “Do you use a regular microcontroller or license the M and configure it to your needs. Platforms like this would help address future changes.”

Flexibility rules
One way of approaching the configurability unknowns is through derivatives. If an ASIC costs $30 million to design, a derivative might cost $10 million. But a platform derivative might be only $5 million, according to Naveed Sherwani, president and CEO of Open-Silicon.

“These are all niche markets,” Sherwani said. “So from a chip development standpoint, the volume is not there. It will have to involve derivatives. Those are the chips that will talk to the Internet.”

But flexibility is the key here. Because no one is certain how technology will be used, or how it will be used in the future, it has to account for that. Corner cases may involve unknowns and best estimates rather than fixed numbers. The Internet of Things involves everything from cars to chips that will be used inside the human body or even inside of livestock. As a result, being able to reconfigure connectivity will be essential to avoid obsolescence, particularly in the beginning as the concept begins rolling out.

“You need a waterfall approach because there is so much heterogeneous stuff that needs to be connected,” said Kurt Shuler, vice president of marketing at Arteris. “A lot of this is about connectivity, and standards will be important. But the other piece of this is that it will also involve humans interacting with machines. So it won’t just be one phone controlling the entire house. It will be lots of things working independently and together. So you need processing power for the human interactions—which is where a network on chip matters—but you probably won’t need so much in a device that is simply passing data along. And if you have cars talking to each other, you’ll need lots of busses.”

Conclusion
None of this will sort itself out overnight, and adoption may not be as straightforward as some proponents anticipate. Still, little by little, more things will be connected to more things, and controllable by more devices from more places.

Sun Microsystems and Novell promoted crude versions of these ideas as far back as the early 1990s, when they believed that networked devices could talk and possibly share processing capabilities. More than two decades later, that networking is wireless, processing power is plentiful, ubiquitous and inexpensive, and connectivity is almost a requirement.

But how all of this technology is used—and potentially used together—remains uncertain. Things talking to things make sense in some areas, but the promise undoubtedly is overhyped in others. For technology to take off it has to be inexpensive enough to be accepted by consumers, easy enough to use so that you don’t have to learn to program it, and practical enough that people will actually use it. The Internet of Things will succeed in some areas and fail miserably in others. But from a design standpoint, the more flexibility and connectivity that is built into devices and platforms—and the more that tools can identify potential conflicts across devices and networks rather than just a chip—the less impact failures will have. And the easier it will be to capitalize on successful segments while minimizing the downside of the less successful ones.

By Ed Sperling
Synopsys teamed up with TSMC to create a reference flow for stacked die. Included are multi-die integration support, as well as extensions to Synopsys’ Galaxy Implementation Platform to include multi-die systems. Most companies expect full 3D to roll out in 2015-2016, while 2.5D production will begin next year.

Synopsys also unveiled the next version of its optical design software for high-performance optical systems. Key to this version is reduced sensitivity to manufacturing and alignment errors.

Cadence rolled out a debugger for RTL, testbench and SoC verification that it claims cuts debug time by up to 40% by enabling users to go forward or backward through their hardware verification and hardware description languages. Cadence also won a couple deals. The first involved CSR, which used Cadence’s Encounter to accelerate tapeout of a low-power, mixed-signal chip.  The second involved STMicroelectronics, which used Cadence’s signoff technologies to speed tapeout for a 28nm SoC.

Tensilica won a deal with Hisense, which is using its HiFi audio/voice DSPs for digital television SoCs. Tensilica also passed the 2 billion mark for IP core shipments. It’s beginning to look like the old McDonald’s signs that listed how many hamburgers were sold.

The market for wearable technology is poised for massive growth. In fact, it’s expected to rise more than 500% between 2011 and 2016, according to IHS iSuppli. Just for perspective, in 2011 14 million wearable technology devices were shipped. Pretty soon you won’t have to ask, ‘Now where did I leave my coat?’

TSMC’s sales dropped 12.4% between August and September, but they’re still up 30.3% in September 2012 compared with September 2011. For the first 9 months of the year, revenue was up 17.5% compared with the same period in 2011.

By Ed Sperling
Mentor Graphics updated UVM Connect, allowing it to be compiled to run with OVM. In case you’ve forgotten, Mentor and Cadence supported OVM, while Synopsys supported VMM. UVM is supposed to be the bridge between both these worlds, but it still isn’t fully baked yet—and some engineers are balking about learning everything from scratch.

Mentor also received certification for its Litho Friendly Design signoff tool for TSMC’s 20nm process.

Apple released its iPhone 5, offering substantially better performance and energy efficiency. But exactly how does that efficiency equate to battery life, particularly now that the company has reduced the thickness of the battery?

Intel took a similar route, focusing on low-power processors to change how people interact with their devices, starting with the Haswell architecture due out next year. The keynotes at this week’s Intel Developer Forum focused on new interfaces and more compute performance rather than extending battery life.

TSMC’s sales grew 2% in August compared with July, up 32% from August 2011. Revenues for the first eight months were up 16% compared to the same period in 2011.

A couple new books were released for verification engineers. One is the Mixed-Signal Verification Guide from Cadence. The second is SystemVerilog Assertions, which has been updated.

As process technologies continue to scale aggressively, it is becoming more challenging when developing high-quality, high-speed mixed-signal IP. Specifically, the 28-nm process poses some unique challenges not found in 65-nm and 40-nm technology processes.

This paper discusses the low power requirements found in 28-nm processes and addresses issues associated with the aggressive scaling of the core supply voltages in these technology processes. It also focuses on restricted design rules and how they have created a paradigm shift in the way circuits are designed and laid out in 28-nm processes as well as describes techniques to maximize design and layout reuse. Furthermore, the paper details design-for-yield challenges encountered in 28-nm processes and the verification methodologies used to ensure robust and manufacturable IP.

To download this white paper, click here.

By Ed Sperling
Cadence published a new book on mixed-signal methodology, focusing on current and future challenges. Topics include everything from behavioral modeling to mixed-signal metric-driven verification and concurrent physical implemention, as well as analog scaling at advanced nodes.

Novatek, the Taiwanese maker of display driver ICs, has entered volume production with a trio of SoCs for set-top boxes and DTVs that use Tensilica’s HiFi Audio DSPs.

MIPS unveiled its full fiscal Q4 earnings. Revenue was $86.2 million for the full 12 months, up 5% compared with fiscal 2011. Fiscal Q4 revenue was $38.4 million, compared with $17.5 million in the same period in 2011. For the year, net income was $14.3 million, but it was $17.3 million for the quarter. That seems to be a push in the right direction.

On-shoring is on the rise in North America, reversing a couple decades of a push to move to the lowest-cost geographies, according to IPC, a broad-based electronics industry group. The study is based on a 2012 survey of 229 manufacturers.

By John E. Blyler
The huge RF radio observatory at Arecibo, Puerto Rico has all of the key ingredients for a high-tech adventure movie. First, its location is remote, as it’s buried deep within the rainforest of a Caribbean island. Second, the sheer size of the radio telescope renders it sublime. It measures 305 m (1001 ft.) in diameter and more than 500 m from the jungle floor to the top of the moveable radio feed platform (see Figure 1). Unlike other astronomic R&D facilities in the United States, the observatory at Arecibo also is more than just a radio telescope. It also is a complete R&D facility. Its mission – in part – is to search for the stuff of science fiction stories ranging from extraterrestrials and gravity waves to asteroids that could devastate the Earth.

We will return to the cool sci-fi aspects of Arecibo later. For now, let’s explore the technology that makes all of this possible—starting with an overview of the RF telescope and the critical electronics. Radio astronomy studies celestial objects using radio transmissions. Often traveling great distances, these radio waves are reflected from the objects of study. The returning signal is analyzed and developed into amazing images. Although this may seem like a straightforward task, the returning signal is typically so weak as to be almost indiscernible from the cosmic noise.

Thus, the successful detection of the returning signal requires the very best that modern electronics has to offer. Indeed, the noise generated by even the most modern low-noise amplifier (LNA) and other sources are orders of magnitude greater than the signals being examined. Dana Whitlow, research technician at Arecibo, estimates that the return signals may be over 40 dB below the overall system noise level—a factor of 10,000 lower!

Critical Sensitivity To Noise
Simply put, everything that can be done is done to maximize the sensitivity of the receivers. The front-end electronics are cytogenetically cooled in 99.99% pure Helium to between 10 and 15 Kelvin. These temperatures can only be achieved in a vacuum. As a result, all of the specially designed electronic systems must be evacuated before the cooling can begin.

The front-end electronic systems consist of amplifiers, filters, and mixers. The amplifiers are specifically designed to minimize noise. Toward that end, Ganesan Rajagopalan, a senior receiver engineer and head of the Electronics Deptartment at the observatory, has been improving the sensitivity of the receivers by slowly replacing the existing gallium-arsenide (GaAs) monolithic microwave integrated circuits (MMICs) with indium-phosphide (InP). MMICs are devices that operate at microwave frequencies between 300 MHz and 300 GHz.

InP-based amplifiers have lower noise and higher gain than their GaAs counterparts. Yet these circuits also must be customized for the lowest noise possible. The Cornell University-based team at Arecibo collaborated with the experts at CalTech’s JPL team to make these customized application-specific integrated circuits (ASICs) tailored to a cryogenic environment. The CalTech design also has been implemented at the Allen Telescope Array (ATA) in California. ATA is a “large number of small dishes” (LNSD) array that’s designed to be highly effective for simultaneous surveys of conventional radio-astronomy projects and Search for Extraterrestrial Intelligence (SETI) observations at centimeter wavelengths.

With such innovative LNA devices, it’s no wonder that the Arecibo Observatory is considered state of the art in receiver technology. In terms of the available bandwidth per receiver, however, the facility is playing catch-up. The receivers used at Arecibo are 2 GHz wide, ranging from 2 to 4 GHz and another from 4 to 8 GHz. The goal is to widen the current 2-GHz signals, which are being received using Ultra Wideband (UWB) technology. Here too, the R&D team is working with other scientists and engineers around the globe to develop a UWB feed that will operate from 1 to 10 GHz. Such a feed would reduce the number of existing receivers from 8 down to 1, which would further reduce the collective number of noise generators in the system.

A Noisy Planet
Reducing the noise sensitivity of the receiving electronics is critical to analyzing the radio signals returning from deep space. But another challenge exists closer to home— namely, the effective “noise” created by wireless devices ranging from cell phones to data devices. The RF telescope operates to 10 GHz and includes receivers in the S-, C-, and X-bands. Wi-Fi technology occupies a relatively small bandwidth centered around 2.4 GHz—right in the middle of the lower S-band space. Another source of radio interference comes from a much more powerful source—namely, the various airports on the island. These sources are mission critical and cannot be turned off at select times during the day.

To help reduce the opportunities for radio noise interference, the Arecibo team actively works with the Puerto Rico Spectrum users’ group. In cases involving mission-critical systems like airport radar, the team has coordinated the on-off time of the radar. The airport radar goes blank for a short period of time when it points in the direction of the Arecibo observatory. Unfortunately, this well-intentioned gesture has proven to be of limited value. The radar signal has more power located in the back lobes of the radar signature than in the front lobes.

Sci-Fi Becomes Reality
As fascinating as the engineering work at Arecibo is, does it really have any practical value? Can it turn science fiction into science fact? Some would suggest that the jungle-hidden facility will play an important role in saving humanity from near-earth objects (NEOs) like asteroids, which may be on a collision course with earth. The RF Observatory has the capability to pinpoint the orbit of NEOs as far away as Jupiter or Saturn and then calculate whether that object poses a threat to humanity. Such knowledge could be used to evacuate populations and move important property to a safe location. This is just one reason why the U.S. Congress is interested in keeping the Arecibo radar telescope working.

“We are also doing a lot of work on pulsars,” explains Rajagopalan. “Pulsar timing is very important in the detection of gravitational wave radiation.” Described as a fluctuation in the curvature of spacetime, which propagates as a wave, gravitational waves were predicted by Albert Einstein’s theory of general relativity. Sources of gravitational waves include binary star systems (e.g., white dwarfs, neutron stars, or black holes).

Pulsar astronomers believe that they can detect gravitational waves. Telescopes at Arecibo, PR and the mainland US, Europe, and Australia are all part of an array that’s being used to carefully time pulsars. All of these facilities make very long, simultaneous observations of the same deep-space source using long baselined interferometry (LBI). Precise synchronization timing among the global facilities is achieved using a hydrogen maser atomic clock. Thus, the research being done here is not just astronomy. It’s planetary radar science and ionospheric as well.

Signal Processing
What happens to the signal returning from the reflection off of nearby planets or from signals originating from a deep-space pulsar? The signal comes into the feed in a concentrated form after reflection from the big reflector (see Figure 3). An ortho-mode transducer (OMT) —some more than 3-ft. long—splits the signal into two separate channels. Noise-injection couplers are connected to one channel. These couplers inject a weak but carefully calibrated noise source into the main signal.

Figure 3: Antenna feed and electronics on platform suspended 500 ft above the main reflector dish floor.

The injected noise signal is switched on and off at a rapid rate that’s called a “winking” rate calibration, says Dana Whitlow, a senior receiver engineer. “By a measurement of the levels later in the system with the cal on and the cal off, we can determine the system noise temperature. Also, this calibration allows us to track unique time-dependent changes and gain of the amplifiers.”

The signal then travels through isolators, which flatten out the frequency response. Effectively, they remove reflections from the amplifiers back into the earlier part of the signal path. Finally, the signal is amplified in the LNAs mentioned earlier.

All of these electronics are contained with a dewar, which is used to cool the amplifiers down to 15 Kelvin. Cables connect the dewar to the next signal-conditioning module, which contains a pulse amplifier module to provide additional amplification. Computer-selectable filters are used to exclude unwanted frequency bands, limiting the bandwidth from radio-interference sources like Wi-Fi and airport radar.

What happens if the ionospheric, planetary, or deep-space phenomena that a researcher is trying to study occur at the same frequency as the radio-interference sources—perhaps centered at 2.4 GHz (same as Wi-Fi)? To study these signals, researchers would have to go to one of the other RF telescope facilities on the mainland United States. For example, the Robert C. Byrd Green Bank Telescope in West Virginia operates in a radio quiet zone.

Aside from rejecting unwanted interference signals, filters also help to prevent the interference from compressing the gain of the subsequent signal chain. If it’s strong enough, an interfering signal could drive an amplifier into saturation. This forces the gain to go down, says Whitlow. “If there’s anything that radio astronomers hate, it’s unexpected gain changes in their signal path. It’s difficult, if not impossible, to deal with from a perspective of obtaining calibrated data of their signal or source they are looking at.” After more filtering and amplification, just to increase the signal strength, the signal is then downconverted to a lower, intermediate frequency.

One might wonder if all of these filters don’t attenuate the signal even further—especially because they are passive filters, which contain no power source to help boost the signal strength. While it’s true that passive filters attenuate the signal slightly, these attenuations can be corrected by the numerous amplifiers. Active filters would have their own problems, such as the introduction of extra noise and distortion.

Finally, the conditioned signal is sent down from the receiver platform to the control-room area some 500 m below using analog optical fiber cable. Fiber-optic cable is used because it has a much broader frequency response. Plus, it doesn’t pick up electrical noise due to the imperfect shielding of coaxial cable. Fiber cables are typically much less lossy than coaxial—especially at the higher frequency ends.

Perhaps the most compelling reason for fiber over coaxial cable is that the former doesn’t conduct lightning down to the control room, explains Whitlow. “I haven’t been down here to see this firsthand, but I’ve been told by many people that in the early days of the observatory, when lightning struck the platform, there would be sparks jumping around things inside the control room.”

Coming in Part II: We’ll delve into the technology used in the control room and laboratory, where the data is digitized and analysis is performed. Of particular interest to chip and embedded designers will be the evolution taking place from ASIC- to FPGA-based systems.

By Ed Sperling

For decades, analog and digital engineers have lived in completely separate worlds. The lines are blurring between those worlds, though, in complex SoCs. So far, the transition has been difficult, and most engineers predict it will get worse at future process nodes.

The basic problem is that each world has functioned independently of the other from the start. They use different tools, they work on different schedules and they generally think about problems from a different vantage point. There are some very good reasons for this. In the digital realm, designs typically last only a year or two. In pure analog, they can last a decade, with a major emphasis on having a specification that’s performance tuned to be just a notch better than the competition.

“These have been two very distinct markets,” said Ed Lechner, director of product marketing for custom design at Synopsys. “One is for standard analog parts, which is the world of Linear, Analog Devices and Fairchild. Their most popular node is 180nm and they tune for maximum performance. At the other end of the spectrum are the digital engineers who are working at 32nm and 45nm. They’re willing to forgo getting maximum performance for a quick and dirty solution so they can get the product out the door in time for the Christmas season.”

But pushing down to the leading edge of Moore’s Law also has opened up an enormous amount of real estate. That creates the opportunity to shrink a bill of materials, and therefore the cost, by combining functions that formerly were on multiple chips into a single chip. This is where analog meets digital, and the relationship—uneasy at a distance—is becoming even rockier when both functions are being forced to work in sync on the same development schedule.

Linda Fosler, marketing director in Mentor Graphics’ deep submicron division, just returned from a European tour where she met with 10 of Mentor’s top customers there. She said those companies want to be able to design mixed signal chips in the same time frame as digital chips and without having to boost the number of engineers to get the job done on schedule.

“One problem we’ve heard is that respins have made companies late to market, which is very costly to them,” Fosler said. “The problem is that the interface between the analog and digital blocks is not tested until the last minute because these teams aren’t working together. The industry needs to address implementation effects—basically the parasitics—of what affects the final qualification of silicon. It must be dealt with iteratively at the layout and schematic level, and built into the tools. We also have to build more intelligent manufacturing awareness into the tools.”

Failure to communicate

The fact that engineering teams are spread out around the globe doesn’t help matters. Even when analog and digital engineers are locked in the same building, they tend not to talk to each other. But none of the tools for developing chips have been constructed to deal with collaboration between teams, which is why most design is done in discrete units defined by the chip architects.

The problem is that in a mixed signal chip, it’s not just the teams that have to communicate. What they’re developing has to work well together, too.

“We’ve heard from some customers that to complete a chip in a compressed schedule, they tape out on tapeout day, whether they’ve finished the simulation or not,” said Bradley Geden, product marketing manager for AMS circuit simulation at Synopsys. “This is what causes re-spins. What’s needed is a formal methodology with sufficient verification and sufficient coverage in an AMS block.”

So far, that methodology doesn’t exist. Nevertheless, the amount of mixed signal content shows no sign of decreasing. Even with digital components there is growing analog content.

“As soon as you add analog onto a chip, the chance of respins increases three times,” said Mar Hershenson, vice president of product development in Magma’s custom design business unit. The schedule is more complex and the tools allow us to put more content on a chip. But they need to work much better. A lot of companies complain they don’t have enough analog designers, but the digital people and the analog people don’t speak the same language and they don’t have the same tools. When it comes time to integrate, that’s where the problem begins.”

Nevertheless, she said the real selling point for mixed signal chips is integration. The less work the customer has to do to integrate those functions, the more attractive a company’s technology looks.

Conclusion

Most tools vendors see mixed signal as an opportunity. They recognize that analog will never be completely automated because some functions will always be customized for a specific chip. But it can at least be enabled and integrated better into the complex design process that includes both digital and analog.

This becomes particularly important as analog engineers are forced to fit into digital design schedules. Getting a design out the door, relatively bug free and on schedule has been achievable so far primarily by ramping up the number of engineers working on those chips. There’s a bundle of money available to the tools vendors that can reduce that pain, and the race is already well under way.

System-Level Design sat down to discuss mixed signal design with Robert Hum, VP and general manager of Mentor Graphics’ Deep Submicron Division; Mar Hershenson, VP of product development in Magma’s custom design business unit; Eric Filseth, CEO of Ciranova, and John Stabenow, group director for solution and product marketing at Cadence. What follows are excerpts of that conversation.

By Ed Sperling
SLD: Analog has always been considered more art than science. How far has it come, and will it ever be automated?
Stabenow: It depends on your time frame. If you’re talking about the slide rule days, we’ve come a long way. If you’re talking about since 2001, we haven’t come that far.
Filseth: That’s right. The basic way of doing analog design hasn’t changed much over the last 15 years. The tools that support the original way of doing it have gotten incrementally better, but it certainly looks like we’ve hit a point of diminishing returns for how productive you can get the traditional methodology to be. The basic concept of how this is done—simulation, handcrafted layout, schematic layout, PDKs, parameter accels—have been there a long time. It isn’t likely to get twice as efficient under the current path.
Hershenson: The biggest change in the past 10 to 15 years has been in simulation and the capacity of the circuits it can handle today. But fundamentally it’s the same.

SLD: But how about the designs?
Filseth: They’ve changed dramatically. They are a lot more complicated. There are a lot more transistors in an analog/mixed signal design. We don’t see that much pure linear analog anymore. It’s all mixed signal.
Hershenson: The main tools for mixed signal are editors and simulators. That’s about it.
Filseth: If you think about the last major advancement, it’s shape-based routing, although arguably it’s used for assembly.
Hum: The digital domain has had the luxury of a unifying paradigm—RTL. That is the central idea that has driven abstract-to-specific automation. The digital side has parametrically focused on timing, but now that power has been added it’s getting more difficult. It’s hard to analyze timing and power. In the analog world there has not been, and there is unlikely to be, a unifying paradigm. The things that define phase lock loops are quite different from the things that make USB 2.0 PHY’s work.

SLD: So where will progress come from?
Hum: In the analog world, whatever progress there is will come from top-down, domain-specific approaches. What you used to do filter synthesis in the old days was a filter package. That doesn’t help for A-to-D conversion. In the analog world, the name of the game in automation is going to be tuned to vertical tracks, and it’s going to be pretty specific. In the next 10 years, there may not be any breakthroughs in this area. There is nothing happening in a coordinated way to create the automation for these small areas.
Filseth: That varies a little bit depending upon where you are in the flow. As you get closer to the architecture, you get more specialized. As you get closer to the silicon, things get more horizontal. And the level of horizontal-ness increases as you get closer to tapeout.

SLD: Is there room to do the different pieces separately?
Stabenow: It does have to be done together. We’re seeing mixed signal everywhere. But that doesn’t necessarily lead you to an analog automation path. You have this automation path on the digital side—things you can do with machines. But in the analog perspective, other than analog macros it’s all being done from scratch and by hand.
Hershenson: The A-to-D converters and phase lock loop are fundamentally different blocks, but they do share a lot of components. In a filter, a main block is a Gm cell or an Op Amp. It’s the same in some types of ADC. There is some commonality on the blocks being used in the different circuits. Otherwise in school we’d have to take 50 classes to become an analog designer. There are some concepts like linearity and gain that are common to different applications. The other thing we’re seeing is talk about integration shortening the design flow. It hasn’t happened. But one thing that has happened is that because of the complexity, there are many more data converters and PLLs on the chip. In digital blocks, high-speed I/Os have a ton of analog content.
Filseth: In the past half-dozen years there’s been a very interesting market split in analog/mixed signal. Traditionally, analog and mixed signal content was on a separate chip. If you were an analog/mixed signal IC company making data converters, you competed with another analog/mixed signal IC company on who had the best integral non-linearity spec on the data converter. Your chip would go onto a circuit board on an MRI system, and the lifespan would be seven years or more. In that sector, pure quality result is critical. Time to market was important, but not critical. You chose the best silicon technology for the job. If it was half-micron CMOS, that’s what you used. In the past half-dozen years, there’s been a different kind of analog/mixed signal chip. Anyone doing a networking chip needs a high-speed SERDES. People want to put PHY radios on a single SoC. The dynamics of the analog/mixed signal content is different. You’re not competing on specifications for your data converter. You’re competing on how fast you can get all this stuff out the door and will you be in time for Christmas? In this kind of market, what counts is good quality results. But top priority is getting all of this stuff integrated together. This is the part of the market that’s growing fastest.
Stabenow: I wonder if the automation won’t come in the form of macro IP. The big SoC guys will buy analog blocks. That means the design problem still exists back at the beginning where they’re generating the IP.

SLD: Is this a problem of people being used to doing things certain ways?
Hershenson: The new generation is different than the old generation. If you were working at Linear or Analog Devices and you got a 1% better gain in your Op Amp, you were king for a day. The major universities like Stanford and MIT have industry-funded programs to improve the analog design flow. Just having the core isn’t enough. You have to figure out how to put systems together. Systems are not just for cell phones. They’re for cars and bio-engineering. This is just beginning. It’s training analog designers plus CAD. The new people we interview know MATLAB and they’re not afraid of writing a Tcl script. I think that’s going to help a lot.

SLD: So what pieces can be automated?
Hum: There are several areas. There is a market developing for big D, little A, where little A is a hard analog block or some kind of malleable parameterized thing that’s a block generator. The problem is verifying that you’ve embedded the analog block and that it’s happy in its embedded location. We need the equivalent of analog assertions. In the digital world, you’ve got the digital assertion space, which looks at protocols between blocks. In the analog world, there is a set of assertions you can come up with. They’re clearly incomplete. Step one is to make sure it’s embedded right, that you understand the boundary and the handshake and transactions that go across it. Big D people wouldn’t know a transistor if it hit them. That’s not how they’re trained. They’re trained in finite state machines, complexity and how to do an 80-million gate design. All you want to know about your analog blog is that you’ve embedded it right. If you had a model that’s plus or minus 10% accurate, that’s enough.

SLD: So what’s the solution?
Hum: There are people working on these non-linear response surface models, which is one approach to it. There’s other work to look at automatic extraction mechanisms. Once you have a circuit and want to get a facsimile of that circuit in the digital domain, you need an interpolation function. There’s good work going on there in universities to generate interpolation functions. This is a different approach than synthesis. It’s de-synthesis. I have the polygons and the transistors and the SPICE mode