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Posts Tagged ‘Mixed Signal’

Cortex-M processor Family at the Heart of IoT Systems

Saturday, October 25th, 2014

Gabe Moretti, Senior Editor

One cannot have a discussion about the semiconductor industry without hearing the word IoT.  It is really not a word as language lawyers will be ready to point out, but an abbreviation that stands for Internet of Things.  And, of course, the abbreviation is fundamentally incorrect, since the “things” will be connected in a variety of ways, not just the Internet.  In fact it is already clear that devices, grouped to form an intelligent subsystem of the IoT, will be connected using a number of protocols like: 6LoWPAN, ZigBee, WiFi, and Bluetooth.  ARM has developed the Cortex®-M processor family that is particularly well suited for providing processing power to devices that consume very low power in their duties of physical data acquisition. This is an instrumental function of the IoT.

Figure 1. The heterogeneous IoT: lots of “things” inter-connected. (Courtesy of ARM)

Figure 1 shows the vision the semiconductor industry holds of the IoT.  I believe that the figure shows a goal the industry set for itself, and a very ambitious goal it is.  At the moment the complete architecture of the IoT is undefined, and rightly so.  The IoT re-introduces a paradigm first used when ASIC devices were thought of being the ultimate solution to everyone’s computational requirements.  The business of IP started  as an enhancement to application-specific hardware, and now general purpose platforms constitute the core of most systems.  IoT lets the application drive the architecture, and companies like ARM provide the core computational block with an off-the-shelf device like a Cortex MCU.

The ARM Cortex-M processor family is a range of scalable and compatible, energy efficient, easy to use processors designed to help developers meet the needs of tomorrow’s smart and connected embedded applications. Those demands include delivering more features at a lower cost, increasing connectivity, better code reuse and improved energy efficiency. The ARM Cortex-M7 processor is the most recent and highest performance member of the Cortex-M processor family. But where the Cortex-M7 is at the heart of ARM partner SoCs for IoT systems, other connectivity IP is required to complete the intelligent SoC subsystem.

A collection of some of my favorite IoT-related IP follows.

Figure 2. The Cortex-M7 Architecture (Courtesy of ARM)

Development Ecosystem

To efficiently build a system, no matter how small, that can communicate with other devices, one needs IP.  ARM and Cadence Design Systems have had a long-standing collaboration in the area of both IP and development tools.  In September of this year the companies extended an already existing agreement covering more than 130 IP blocks and software.  The new agreement covers an expanded collaboration for IoT and wearable devices targeting TSMC’s ultra-low power technology platform. The collaboration is expected to enable the rapid development of IoT and wearable devices by optimizing the system integration of ARM IP and Cadence’s integrated flow for mixed-signal design and verification.

The partnership will deliver reference designs and physical design knowledge to integrate ARM Cortex processors, ARM CoreLink system IP, and ARM Artisan physical IP along with RF/analog/mixed-signal IP and embedded flash in the Virtuoso-VDI Mixed-Signal Open Access integrated flow for the TSMC process technology.

“The reduction in leakage of TSMC’s new ULP technology platform combined with the proven power-efficiency of Cortex-M processors will enable a vast range of devices to operate in ultra energy-constrained environments,” said Richard York, vice president of embedded segment marketing, ARM. “Our collaboration with Cadence enables designers to continue developing the most innovative IoT devices in the market.”  One of the fundamental changes in design methodology is the aggregation of capabilities from different vendors into one distribution point, like ARM, that serve as the guarantor of a proven development environment.

Communication and Security

System developers need to know that there are a number of sources of IP when deciding on the architecture of a product.  In the case of IoT it is necessary to address both the transmission capabilities and the security of the data.

As a strong partner of ARM Synopsys provides low power IP that supports a wide range of low power features such as configurable shutdown and power modes. The DesignWare family of IP offers both digital and analog components that can be integrated with any Cortex-M MCU.  Beyond the extensive list of digital logic, analog IP including ADCs and DACs, plus audio CODECs play an important role in IoT applications. Designers also have the opportunity to use Synopsys development and verification tools that have a strong track record handling ARM based designs.

The Tensilica group at Cadence has published a paper describing how to use Cadence IP to develop a Wi-Fi 802.11ac transceiver used for WLAN (wireless local area network). This transceiver design is architected on a programmable platform consisting of Tensilica DSPs, using an anchor DSP from the ConnX BBE family of cores in combination with a smaller specialized DSP and dedicated hardware RTL. Because of the enhanced instruction set in the Cortex-M7 and superscalar pipeline, plus the addition of floating point DSP, Cadence radio IP works well with the Cortex-M7 MCU as intermediate band, digital down conversion, post-processing or WLAN provisioning can be done by the Cortex-M7.

Accent S.A. is an Italian company that is focused on RF products.  Accent’s BASEsoc RF Platform for ARM enables pre-optimized, field-proven single chip wireless systems by serving as near-finished solutions for a number of applications.  This modular platform is easily customizable and supports integration of different wireless standards, such as ZigBee, Bluetooth, RFID and UWB, allowing customers to achieve a shorter time-to-market. The company claims that an ARM processor-based, complex RF-IC could be fully specified, developed and ramped to volume production by Accent in less than nine months.

Sonics offers a network on chip (NoC) solution that is both flexible in integrating various communication protocols and highly secure.   Figure 3 shows how the Sonics NoC provides secure communication in any SoC architecture.

Figure 3.  Security is Paramount in Data Transmission (Courtesy of Sonics)

According to Drew Wingard, Sonics CTO “Security is one of the most important, if not the most important, considerations when creating IoT-focused SoCs that collect sensitive information or control expensive equipment and/or resources. ARM’s TrustZone does a good job securing the computing part of the system, but what about the communications, media and sensor/motor subsystems? SoC security goes well beyond the CPU and operating system. SoC designers need a way to ensure complete security for their entire design.”

Drew concludes “The best way to accomplish SoC-wide security is by leveraging on-chip network fabrics like SonicsGN, which has built-in NoCLock features to provide independent, mutually secure domains that enable designers to isolate each subsystem’s shared resources. By minimizing the amount of secure hardware and software in each domain, NoCLock extends ARM TrustZone to provide increased protection and reliability, ensuring that subsystem-level security defects cannot be exploited to compromise the entire system.”

More examples exist of course and this is not an exhaustive list of devices supporting protocols that can be used in the intelligent home architecture.  The intelligent home, together with wearable medical devices, is the most frequent example of IoT that could be implemented by 2020.  In fact it is a sure bet to say that by the time the intelligent home is a reality many more IP blocks to support the application will be available.

Complexity of Mixed-signal Designs

Thursday, August 28th, 2014

Gabe Moretti, Senior Editor

The major constituent of system complexity today is the integration of computing with mechanical and human interfaces.  Both of these are analog in nature, so designing mixed-signal systems is a necessity.  The entire semiconductor chain is impacted by this requirement.  EDA tools must support mixed-signal development and the semiconductor foundries must adapt to using different processes to build one IC.

Impact on Semiconductor Foundries

Jonah McLeod, Director of Corporate Marketing Communications at Kilopass Technology was well informed about foundries situation when ARM processors became widely used in mixed-signal designs.  He told me that: ” Starting in 2012 with the appearance of smart meters, chip vendors such as NXP began integrating the 32-bit ARM Cortex processor with a analog/mixed-signal metrology engine for Smart Metering with two current inputs and a voltage input.

This integration had significant impact on both foundries and analog chip suppliers. The latter had been fabricating mixed-signal chips on process nodes of 180nm and larger, many with their own dedicated fabs. With this integration, they had to incorporate digital logic with their analog designs.

Large semiconductor IDMs like NXP, IT and ST had an advantage over dedicated chip companies like Linear and Analog Devices. The former had both logic and analog design expertise they could bring to bear building these SoCs and they had the fabrication expertise to build digital mixed-signal processes in smaller process geometries.

Long exempt from the pressure to chase smaller process geometries aggressively, the dedicated analog chip companies had a stark choice. They could invest the large capital expenditure required to build smaller geometry fabs or they could go fablite and outsource smaller process geometry designs to the major fabs. This was a major boost for the foundries that needed designs to fill fabs abandoned by digital designs chasing first 40nm and now 28nm. As a result, ffoundries now have 55nm processes tailored for power management ICs (PMICs) and display driver ICs, among others. Analog expertise still counts in this new world order but the competitive advantage goes to analog/mixed-signal design teams able to leverage smaller process geometries to achieve cost savings over competitors.”

As form factors in handheld and IoT devices become increasingly smaller, integrating all the components of a system on one IC becomes a necessity.  Thus fabricating mixed-signal chips with smaller geometries processes grows significantly in importance.

Mladen Nizic, Product Marketing Director at cadence noted that requirements on foundries are directly connected to new requirements for EDA tools.  He observed that: “Advanced process nodes typically introduce more parametric variation, Layout Dependent Effects (LDE), increased impact of parasitics, aging and reliability issues, layout restrictions and other manufacturing effects affecting device performance, making it much harder for designers to predict circuit performance in silicon. To cope with these challenges, designers need automated flow to understand impact of manufacturing effects early, sensitivity analysis to identify most critical devices, rapid analog prototyping to explore layout configurations quickly, constraint driven methodology to guide layout creation and in-design extraction and analysis to enable correct-by-construction design. Moreover, digital-assisted-analog has common approach in achieving analog performance, leading to increased need for integrate mixed-signal design flow.”

Marco Casale-Rossi, Senior Staff Product Marketing Manager, Design Group, Synopsys points out that there is still much life remaining in the 180nm process.  ”I’ll give you the 180 nanometer example: when 180 nanometers was introduced as an emerging technology node back in 1999, it offered single-poly, 6 aluminum metals, digital CMOS transistors and embedded SRAM memory only. Today, 180 nanometers is used for state-of-the-art BCD (Bipolar-CMOS-DMOS) processes, e.g. for smartpower, automotive, security, MCU applications; it features, as I said, bipolar, CMOS and DMOS devices, double-poly, triple-well, four aluminum layers, integrating a broad catalogue of memories such as DRAM, EEPROM, FLASH, OTP, nad more.   Power supplies span from 1V to several tens or even hundreds of Volts; analog & mixed-signal manufacturing processes at established technology nodes are as complex as the latest and greatest digital manufacturing processes at emerging technology nodes, only the metrics of complexity are different.”

EDA Tools and Design Flow

Mixed-signal designs require a more complex flow than strictly digital designs.  They often incorporate multiple analog, RF, mixed-signal, memory and logic blocks operating at high performance and different power domains.  For these reasons engineers designing a mixed-signal IC need different tools throughout the development process.  Architecting, developing testing and place and route functions are all impacted.

Mladen observed that “Mixed-signal chip architects must explore different configurations with all concerned in a design team to avoid costly, late iterations. Designers consider many factors like block placement relative to each other, IO locations, power grid and sensitive analog routes, noise avoidance to arrive to optimal chip architecture.”

Standard organizations, particularly Accellera and the IEEE have developed versions of generally used HD languages like Verilog and VHDL that provide support for mixed-signal descriptions.  VHDL-AMS and Verilog-AMS continue to be supported by the IEEE and working groups are making sure that the needs of designers are met.

Mladen points out that “recent extensions in standardization efforts for Real Number Modeling (RNM) enable effective abstraction of analog for simulation and functional verification almost at digital speeds.    Cadence provides tools for automating analog behavioral and RNM model generation and validation. In last couple of years, adoption of RNM is on rise driven by verification challenges of complex mixed-signal designs.”

Design verification is practically always the costlier part of development.  This is partly due to the lack of effective correct by construction tools and obviously by the increasing complexity of designs that are often a product of various company design teams as well as the use of third party IP.

Steve Smith, Sr. Marketing Director, Analog/Mixed-signal Verification at Synopsyspointed out that: “The need for exhaustive verification of mixed-signal SoCs means that verification teams need perform mixed-signal simulation as part of their automated design regression test processes. To achieve this requirement, mixed-signal verification is increasingly adopting techniques that have been well proven in the purely digital design arena. These techniques include automated stimulus generation, coverage and assertion- driven verification combined with low-power verification extended to support analog and mixed-signal functionality.  As analog/mixed-signal design circuits are developed, design teams will selectively replace high-level models for the SPICE netlist and utilize the high performance and capacity of a FastSPICE simulator coupled to a high-performance digital simulator. This combination provides acceleration for mixed-signal simulation with SPICE-like accuracy to adequately verify the full design. Another benefit of using FastSPICE in this context is post-layout simulation for design signoff within the same verification testbench environment.”

He continued by saying that: “An adjacent aspect of the tighter integration between analog and digital relates to power management – as mixed-signal designs require multiple power domains, low-power verification is becoming more critical. As a result of these growing challenges, design teams are extending proven digital verification methodologies to mixed-signal design.  Accurate and efficient low-power and multiple power domain verification require both knowledge of the overall system’s power intent and careful tracking of signals crossing these power domains. Mixed-signal verification tools are available to perform a comprehensive set of static (rule-based) and dynamic (simulation run-time) circuit checks to quickly identify electric rule violations and power management design errors. With this technology, mixed-signal designers can identify violations such as missing level shifters, leakage paths or power-up checks at the SoC level and avoid significant design errors before tape-out. During detailed mixed-signal verification, these run-time checks can be orchestrated alongside other functional and parametric checks to ensure thorough verification coverage.”

Another significant challenge to designers is placing and routing the design.  Mladen described the way Cadence supports this task.  “Analog designers use digital logic to calibrate and tune their high performance circuits. This is called digitally-assisted-analog approach. There are often tens of thousands of gates integrated with analog in a mixed-signal block, at periphery making it ready for integration to SOC as well as embedded inside the hierarchy of the block. Challenges in realizing this kind of designs are:

- time and effort needed for iteration among analog and digital designers,

- black-boxing among analog and digital domains with no transparency during the iterations,

- sharing data and constraints among analog and digital designers,

- performing ECO particularly late in the design cycle,

- applying static timing analysis across timing paths spanning gates embedded in hierarchy of mixed-signal block(s).

Cadence has addressed these challenges by integrating Virtuoso custom and Encounter digital platforms on common OpenAccess database enabling data and constraint sharing without translation, full transparency in analog and digital parts of layout in both platforms.”

Casale-Rossi has described how Synopsys addresses the problem.  “A&M/S has always had placement (e.g. symmetry, rotation) and routing (e.g. shielding, length/resistance matching) special requirements. With Synopsys’ Custom Designer – IC Compiler round-trip, and with our Galaxy Custom Router, we are providing our partners and customers with an integrated environment for digital and analog & mixed-signal design implementation that helps address the challenges.”

Conclusion

The bottom line is that EDA tools providers, standards developing organization and semiconductor foundries have significant further work to do.  IC complexity will increase and with it mixed-signal designs.  Mixed-signal third party IP is by nature directly connected to a specific foundry and process since it must be developed and verified at the transistor level.  Thus the complexity of integrating IP development and fabrication will limit the number of IP providers to those companies big enough to obtain the attention of the foundry.

Analog Designers Face Low Power Challenges

Monday, June 16th, 2014

By John Blyler, Chief Content Officer

Can mixed signal designs achieve the low power needed by today’s tightly integrated SoCs and embedded IoT communication systems?

System level power budgets are affected by SoC integration. Setting aside the digital scaling benefits of smaller geometric nodes, leading edge SoCs achieve higher performance and tighter integration with decreased voltage levels at a cost. If power is assumed to be constant, then that cost is the increased current flow (P=VI) delivered to an ever larger number of processor cores. That’s why SoC power delivery and distribution remain a major challenge for chip architects, designers and verification engineers.

As with digital engineers, analog and mixed signal power designers must consider ways to lower power consumption early in the design phase. Beyond that consideration, there are several common ways to reduce the analog mixed signal portion of a power budget. These ways include low-power transmitter architectures; analog signal processing in low-voltage domains; and sleep mode power reduction. (ARM’s Diya Soubra takes about mixed signal sleep modes in, “Digital Designers Grapple with Analog Mixed Signal Designs.”)

To efficiently explore the design space and make basic system-level trade-offs, SoC architects must adapt their modeling style to accommodate mixed-signal design and verification techniques. Such early efforts will also help prevent overdesign in which globally distributed and cross-discipline (digital and analog) design teams don’t share information. For example, if designers are creating company-specific intellectual property (IP) cores, then they may not be aware how various IP subsystems are being used at the full chip level.

Similarly, SoC package level designers must also understand how IP is used at the higher board level. Without this information, designers tend to over compensate their portion of the design, i.e., over design to ensure their portion of the design stays within the allocated power budget. But that leads to increased cost and power consumption.

Power Modes

From an architectural viewpoint, power systems really have two categories; active and idle/standby modes. With all of the physical level (PHY) link integration occurring on SoCs, active power considerations must apply not only to digital but also analog and input-output power designs.

Within the modes of active and idle/standby power are the many power states needed to balance the current load amongst various voltage islands. With increased performance and power demands on both digital and analog designs, there is growing interest in Time- and Frequency-Domain Power Distribution (or Delivery) Network (PDN) analysis. Vic Kulkarni, VP and GM at Apache Design, believes that a careful power budgeting at a high level enables the efficient design of the power delivery network in the downstream design flow. (See, “System Level Power Budgeting.”)

SoC power must be modeled throughout all aspects of the design implementation.  Although one single modeling approach won’t work, a number of vertical markets like automotive have found success using virtual prototypes.  “System virtual prototypes are increasingly a mix – not just of hardware and software, but also of digital, control, and analog components integrated with many different sensors and actuators,” observed Arun Mulpur of The Mathworks. (See, “Chip, Boards and Beyond: Modeling Hardware and Software.”)

Communications Modes

Next to driving a device screen or display, the communication subsystem tends to consume the most power on a SoC. That’s why several low power initiatives have recently arisen like Bluetooth Low Energy. Today there are three mainstream standards for Bluetooth in use – Bluetooth 2.0 (often referred to as Bluetooth Classic), Bluetooth 4.0, which offers both a standard high-speed mode and a low-energy mode with limited data rate referred to Bluetooth LE; and a single-mode Bluetooth LE standard that keeps power consumption to a minimum.  (See, “Wearable Technologies Meet Bluetooth Low Energy.”)

Power profiling of software is an important part of designing for cellular embedded systems. But cellular is only one connectivity option when designing the SoC or board level device. Other communication types include short range subsystems, Bluetooth, Zigbee, 6LowPAN and mesh networks. If Wi-Fi connectivity is needed, then there will be choices for fixed LAN connected things using Ethernet or proprietary cabling systems. Further, there will be interplay amongst all this different ways to connect that must be simulated at an overall system-level.  (See, “Cellular vs. WiFi Embedded Design.”)

It has only been in the last decade or so that mixed signal systems have played a more dominant role in system level power budgets. Today’s trend toward a highly connected, Internet-of-Things world (IoT) means that low power, mixed signal communication design must begin early in the design phase to be considered part of the overall system-level power management process.

Blog Review – Mon. June 16 2014

Monday, June 16th, 2014

Naturally, there is a DAC theme to this week’s blogs – the old, the new, together with the soccer/football debate and the overlooked heroes of technology. By Caroline Hayes, Senior Editor.

Among those attending DAC 2014, Jack Harding, eSilicon rejoiced in seeing some familiar faces but mourns the lack of new faces and the absence of a rock and roll generation for EDA.

Football fever has affected Shelly Stalnaker, Mentor Graphics, as she celebrates the World Cup coming to a TV screen near you. The rest of the world may call soccer football but the universality of IC design and verification is an analogy that will resonate with sport enthusiasts everywhere.

Celebrating Alan Turing, Aurelien, Dassault Systemes, looks at the life and achievements of the man who broke the Enigma Code, in WWII, invented the first computer in 1936 and who defined artificial intelligence. The fact he wasn’t mentioned in the 2001 film, Engima, about the code breakers, reflects how overlooked this incredible man was.

Mixed signal IC verification was the topic for a DAC panel, and Richard Goering, Cadence runs down what was covered, from tools and methodologies, the prospects for scaling and a hint at what’s next.

Digital Designers Grapple with Analog Mixed Signal Designs

Tuesday, June 10th, 2014

By John Blyler, Chief Content Officer

Today’s growth of analog and mixed signal circuits in the Internet of Things (IoT) applications raises questions about compiling C-code, running simulations, low power designs, latency and IP integration.

Often, the most valuable portion of a technical seminar is found in the question-and-answer (Q&A) session that follows the actual presentation. For me, that was true during a recent talk on the creation of mixed signal devices for smart analog and the Internet of Things (IoT) applications. The speakers included Diya Soubra, CPU Product Marketing Manager and Joel Rosenberg, Platform Marketing Director at ARM; and Mladen Nizic, Engineering Director at Cadence. What follows is my paraphrasing of the Q&A session with reference to the presentation where appropriate. – JB

Question: Is it possible to run C and assembly code on an ARM® Cortex®-M0 processor in Cadence’s Virtuoso for custom IC design? Is there a C-compiler within the tool?

Nizic: The C compiler comes from Keil®, ARM’s software development kit. The ARM DS-5 Development Studio is an Eclipse based tool suite for the company’s processors and SoCs. Once the code is compiled, it is run together with RTL software in our (Cadence) Incisive Mixed Signal simulator. The result is a simulation of the processor driven by an instruction set with all digital peripherals simulated in RTL or at the gate level. The analog portions of the design are simulated at the appropriate behavioral level, i.e., Spice transistor level, electrical behavioral Verilog A or a real number model. [See the mixed signal trends section of, “Moore’s Cycle, Fifth Horseman, Mixed Signals, and IP Stress”)

You can use the electrical behavioral models like a Verilog A and VHDL-A and –AMS to simulate the analog portions of the design. But real number models have become increasingly popular for this task. With real number models, you can model analog signals with variable amplitudes but discrete time steps, just as required by digital simulation. Simulations with a real number model representation for analog are done at almost the same speed as the digital simulation and with very little penalty (in accuracy). For example, here (see Figure 1) are the results of a system simulation where we verify how quickly Cortex-M0 would us a regulation signal to bring pressure to a specified value. It takes some 28-clock cycles. Other test bench scenarios might be explored, e.g., sending the Cortex-M0 into sleep mode if no changes in pressure are detected or waking up the processor in a few clock cycles to stabilize the system. The point is that you can swap these real number models for electrical models in Verilog A or for transistor models to redo your simulation to verify that the transistor model performs as expected.

Figure 1: The results of a Cadence simulation to verify the accuracy of a Cortex-M0 to regulate a pressure monitoring system. (Courtesy of Cadence)

Question: Can you give some examples of applications where products are incorporating analog capabilities and how they are using them?

Soubra: Everything related to motor control, power conversion and power control are good examples of where adding a little bit of (processor) smarts placed next to the mixed signal input can make a big difference. This is a clear case of how the industry is shifting toward this analog integration.

Question: What capabilities does ARM offer to support the low power requirement for mixed signal SoC design?

Rosenberg: The answer to this question has both a memory and logic component. In terms of memory, we offer the extended range register file compilers which today can go up to 256k bits. Even though the performance requirement for a given application may be relatively low, the user will want to boot from the flash into the SRAM or the register file instance. Then they will shut down the flash and execute out of the RAM as the RAM offers significantly lower active as well as stand-by power compared to executing out of flash.

On the logic side, we offer a selection from 7, 9 and 12 tracks. Within that, there are three Vt options – one for high, nominal and lower speeds. Beyond that we also offer power management kits that provide things like level shifters and power gating so the user can shut down none active parts of the SoC circuit.

Question: What are the latency numbers for waking up different domains that have been put to sleep?

Soubra: The numbers that I shared during the presentation do not include any peripherals since I have no way of knowing what peripherals will be added. In terms of who is consuming what power, the normal progression tends to be the processor, peripherals, bus and then the flash block. The “wake-up” state latency depends upon the implementation itself. You can go from tens-of-cycles to multiple-of-tens depending upon how the clocks and phase locked loops (PLLs) are implemented. If we shut everything down, then a few cycles will be required before everything goes off an, before we can restart the processor. But we are talking about tens not hundreds of cycles.

Question: And for the wake-up clock latency?

Soubra: Wake-up is the same thing, because when the wake-up controller says “lets go,” it has to restart all the clocks before it starts the processor. So it is exactly the same amount.

ARM Cortex-M low power technologies.

Question: What analog intellectual property (IP) components are offered by ARM and Cadence? How can designers integrate their own IP in the flow?

Nizic: At Cadence, through the acquisition of Cosmic, we have a portfolio of applicable analog and mixed signal IP, e.g., converters, sensors and the like. We support all design views that are necessary for this kind of methodology including model abstracts from real number to behavioral models. Like ARM’s physical IP, all of ours are qualified for the various foundry nodes so the process of integrating IP and silicon is fairly smooth.

Soubra: From ARM’s point-of-view, we are totally focused on the digital part of the SoC, including the processors, bus infrastructure components, peripherals, and memory controllers that are part of the physical IP (standard cell libraries, I/O cells, SRAM, etc). Designers integrate the digital parts (processors, bus components, peripherals and memory controller) in RTL design stages. Also, they can add the functional simulation models of memories and I/O cells in simulations, together with models of analog components from Cadence. The actual physical IP are integrated during various implementation stages (synthesis, placement and routing, etc).

Question: How can designers integrate their own IP into the SoC?

Nizic: Some of the capabilities and flows that we described are actually used to create customer IP for later reuse in SoC integration. There is a centric flow that can be used, whether the customer’s IP is pure analog or contains a small amount of standard cell digital. For example, the behavioral modeling capabilities help package this IP for the functional simulation in full chip verification. But getting the IP ready is only one aspect of the flow.

From a physical abstract it’s possible to characterize the IP for use in timing driven mode. This approach would allow you to physically verify the IP on the SoC for full chip verification.

What Powers the IoT?

Wednesday, October 16th, 2013

By Stephan Ohr, Gartner

Powering the Internet of Things (IoT) is a special challenge, says Gartner analyst Stephan Ohr, especially for the wireless sensor nodes (WSNs) that must collect and report data on their environmental states (temperature, pressure, humidity, vibration and the like). While the majority of WSNs will harness nearby power sources and batteries, there will be as many as 10% of the sensor nodes that must be entirely self-powering. Often located in places where it is difficult or impossible to replace batteries, these remote sensor nodes must continue to function for 20 years or more.

Two research and development efforts focus on self-powering remote sensor nodes: One effort looks at energy harvesting devices, which gather power from ambient sources. The major types of energy harvesting devices include specialized solar cells, vibration and motion energy harvesters, and devices that take advantage of thermal gradients warm and cool surfaces. Research and development concentrated on reducing the size and cost of these devices, and making their energy gathering more efficient. But even in their current state of development, these devices could add up to a half-billion in revenues per year within the next five years.

The other R&D effort concentrates on low-power analog semiconductors which will elevate the milli-volt outputs of energy harvesting devices to the levels necessary for powering sensors, microcontrollers, and wireless transceivers. These devices include DC-DC boost converters, sensor signal conditioning amplifiers, and, in some cases, data converter ICs which transform the analog sensor signals to digital patterns the microcontroller can utilize. Broadline analog suppliers like Linear Technology Corp. and Analog Devices have added low-power ICs to their product portfolios. In addition to boosting low-level signals, they use very little power themselves. LTC’s low-power parts, for example, have a quiescent current rating of 1.3 micro-amps. Other companies liked Advanced Linear Devices (ALD) have been working on low-threshold electronics for years, and Texas Instruments has a lineup of specialized power management devices for WSN applications.

Ohr’s projections on energy harvesting will be part of his talk on “Powering the Internet of Things” at the Sainte Claire Hotel, San Jose, CA on October 24, 2013. (Admission is free, but advance registration is required The Internet of Things – A Disruption and an Evolution)

Source: Gartner Research (Oct 2013)

Stephan (“Steve”) Ohr is the Research Director for Analog ICs, Sensors and Power Management devices at Gartner, Inc., and focuses on markets that promise semiconductor revenue growth. His recent reports have explored custom power management ICs for smart phones and tablets, the impact of Apple’s choices on the MEMs sensor industry, and a competitive landscape for MEMs sensor suppliers.

Ohr’s engineering degree, a BS in Industrial Engineering, comes from the New Jersey Institute of Technology (the Newark College of Engineering) and his graduate degree, an MA in sociology, comes from Rutgers.

Mixed Signal and Microcontrollers Enable IoT

Wednesday, October 16th, 2013

By John Blyler

The Internet of Things (IoT) has become such a hot topic that many business and technical experts see it as a key enabler for the fourth industrial revolution – following the steam engine, the conveyor belt and the first phase of IT automation technology (McKinsey Report). Still, for all the hype, the IoT concept seems hard to define.

From a technical standpoint, the IoT refers to the information system that uses smart sensors and embedded systems that connect wired or wirelessly via Internet protocols. ARM defines IoT as, “a collection of smart, sensor-enabled physical objects, and the networks, servers and services that interact with them. It is a trend and not a single sector or market.” How do these interpretations relate to the real world?

“There are two ways in which the “things” in the IoT interact with the physical world around us,” explains Diya Soubra, CPU Product Manager for ARM’s Processor Division. “First they convert physical (analog) data into information and second they act in the physical world based on information. An example of the first way is a temperature sensor that reports temperature while an example of the second way is a door lock opens upon receiving a text message.”

For many in the chip design and embedded space, IoT seems like the latest iteration of the computer-communication convergence heralded from the last decade. But this time, a new element has been added to the mix, namely, sensor systems. This addition means that the role of analog and mixed signal system must now extend beyond RF and wireless devices to include smart sensors. This combination of analog mixed signal, RF-wireless and digital microcontrollers has increase the complexity and confusion among chip, board, package and end product semiconductor developers.

“Microcontrollers (MCUs) targeting IoT applications are becoming analog-intensive due to sensors, AD converters, RF, Power Management and other analog interfaces and modules that they integrate in addition to digital processor and memory,” says Mladen Nizic, Engineering Director for Mixed Signal Solutions at Cadence Design Systems. “Therefore, challenges and methodology are determined not by the processor, but by what is being integrated around it. This makes it difficult for digital designers to integrate such large amounts of analog. Often, analog or mixed-signal skills need to be in charge of SoC integration, or the digital and analog designer must work very closely to realize the system in silicon.”

The connected devices that make up the IoT must be able to communicate via the Internet. This means the addition of wired or wireless analog functionality to the sensors and devices. But a microcontroller is needed to convert the analog signal to digital and to run the Internet Protocol software stacks. This is why IoT requires a mix of digital (Internet) and analog (physical world) integration.

Team Players?

Just how difficult is it for designers – especially digital – to incorporate analog and mix signal functionality into their SoCs? Soubra puts it this way (see Figure 1): “In the market, these are two distinct disciplines. Analogue is much harder to design and has its set of custom tools. Digital is easier since it is simpler to design, and it has its own tools. In the past (prior to the emergence of IoT devices), Team A designed the digital part of the system while Team B designed the analog part separately. Then, these two distinct subsystems where combined and tested to see which one failed. Upon failure, both teams adjusted their designs and the process was repeated until the system worked as a whole. These different groups using different tools resulted in a lengthy, time consuming process.”

Contrast that approach with the current design cycle where the entire mixed signal designers (Teams A and B) work together from the start as one project using one tool and one team. All tool vendors have offerings to do this today. New tools allow viewing the digital and analog parts at various levels and allow mixed simulations. Every year, the tools become more sophisticated to handle ever more complex designs.

Figure 1: Concurrent, OA-based mixed-signal implementations. (Courtesy of Cadence)

Simulation and IP

Today, all of the major chip- and board-level EDA and IP tool vendors have modeling and simulation tools that support mixed signal designs directly (see Figure 2).

Figure 2: Block diagram of pressures-temperature control and simulation system. (Courtesy Cadence)

Verification of the growing analog mixed-signal portion of SoCs is leading to better behavioral models, which abstract the analog upward to the register transfer level (RTL). This improvement provides a more consistent handoff between the analog and digital boundaries. Another improvement is the use of real number models (RNMs), which enable the discrete time transformations needed for pure digital solver simulation of analog mixed-signal verification. This approach enables faster simulation speeds for event-driven real-time models – a benefit over behavioral models like Verilog-A.

AMS simulations are also using assertion techniques to improve verification – especially in interface testing. Another important trend is the use of statistical analysis to handle both the analog nature of mixed signals and the increasing number of operational modes. (See, “Moore’s Cycle, Fifth Horseman, Mixed Signals, and IP Stress”).

Figure: Cadence’s Mladen Nizic (background right) talk about mixed-signal technology with John Blyler. (Photo courtesy of Lani Wong)

For digital designers, there is a lot to learn in the integration of analog systems. However, the availability of ready-to-use analog IP does make it much easier than in the past. That’s one reason why the analog IP market has grown considerable in the last several years and will continue that trend. As reported earlier this year, the wireless chip market will be the leading growth segment for the semiconductor industry in 2013, predicts IHS iSuppli Semiconductor (“Semiconductor Growth Turns Wireless”).

The report states that original-equipment-manufacturer (OEM) spending on semiconductors for wireless applications will rise by 13.5% this year to reach a value of $69.6 billion – up from $62.3 billion in 2012.

The design and development of wireless and cellular chips – part of the IoT connectivity equation – reflects a continuing need for related semiconductor IP. All wireless devices and cell phones rely on RF and analog mixed-signal (AMS) integrated circuits to convert radio signals into digital data, which can be passed to a baseband processor for data processing. That’s why a “wireless” search on the Chipestimate.com website reveals list after list of IP companies providing MIPI controllers, ADCs, DACs, PHY and MAC cores, LNAs, PAs, mixers, PLLs, VCOs, audio/video codecs, Viterbi encoders/decoders, and more.

Real-World Examples

“Many traditional analog parts are adding more intelligence to the design and some of them use microcontrollers to do so,” observes Joseph Yiu, Embedded Technology Specialist at ARM. “One example is an SoC from Analog Device (ADuCM360) that contains a 24-bit data acquisition system with multichannel analog-to-digital converters (ADCs), an 32-bit ARM Cortex-M3 processor, and Flash/EE memory. Direct interfacing is provided to external sensors in both wired and battery-powered applications.”

But, as Soubra mentioned earlier, the second way in which the IoT interacts with the physical world is to act on information – in other words, through the use of digital-to-analog converters (DACs). An example of a chip that converts digital signals back to the physical analog world is SmartBond DA14580. This System-on-Chip (SoC) is used to connect keyboards, mice and remote controls wirelessly to tablets, laptops and smart TVs. It consists of Bluetooth subsystem, a 32 -bit ARM Cortex M0 microcontroller, antenna connection and GPIO interfaces.

Challenges Ahead

In addition to tools that simulated both analog, mixed signal and digital designs, perhaps the next most critical challenge in IoT hardware and software development is the lack of standards.

“The industry needs to converge on the standard(s) on communications for IoT applications to enable information flow among different type of devices,” stressed Wang, software will be the key to the flourish of IoT applications, as demonstrated by ARM’s recent acquisition of Sensinode.” A Finnish software company, Sensinode builds a variation of the Internet Protocols (IP) designed for IoT device connection. Specifically, the company develops to the 6LoWPAN standard, a compression format for IPv6 that is designed for low-power, low-bandwidth wireless links.

If IoT devices are to receive widespread adoption by consumers, then security of the data collected and acted upon by these devices must be robust. (Security will be covered in future articles).

Analog and digital integration, interface and communication standards, and system-level security have always been challenges faced by leading edge designers. The only thing that changes is the increasing complexity of the designs. With the dawning of the IoT, that complexity will spread from every physical world sensor node to every cloud-based server receiving data from or transmitting to that node. Perhaps this complexity spreading will ultimately be the biggest challenge faced by today’s intrepid designers.

Solutions For Mixed-Signal IP, IC, And SoC Implementation

Thursday, September 27th, 2012

Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Realizing modern mixed-signal designs requires new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implementation challenges and focuses on three advanced, highly integrated flows to meet those challenges: analog-centric schematic-driven, digital-centric netlist-driven, and concurrent mixed-signal. Each flow leverages a common OpenAccess database for both analog and digital data and constraints, ensuring tool interoperability without data translation. Each flow also offers benefits in the area of chip planning and area reduction; full transparency between analog and digital data for fewer iterations and faster design closure; and easier, more automated ECOs, even at late stages of design.

To view this white paper, click here.

Remote RF Telescope Bring Sci-Fi To Reality

Thursday, April 22nd, 2010

By John E. Blyler
The huge RF radio observatory at Arecibo, Puerto Rico has all of the key ingredients for a high-tech adventure movie. First, its location is remote, as it’s buried deep within the rainforest of a Caribbean island. Second, the sheer size of the radio telescope renders it sublime. It measures 305 m (1001 ft.) in diameter and more than 500 m from the jungle floor to the top of the moveable radio feed platform (see Figure 1). Unlike other astronomic R&D facilities in the United States, the observatory at Arecibo also is more than just a radio telescope. It also is a complete R&D facility. Its mission – in part – is to search for the stuff of science fiction stories ranging from extraterrestrials and gravity waves to asteroids that could devastate the Earth.

We will return to the cool sci-fi aspects of Arecibo later. For now, let’s explore the technology that makes all of this possible—starting with an overview of the RF telescope and the critical electronics. Radio astronomy studies celestial objects using radio transmissions. Often traveling great distances, these radio waves are reflected from the objects of study. The returning signal is analyzed and developed into amazing images. Although this may seem like a straightforward task, the returning signal is typically so weak as to be almost indiscernible from the cosmic noise.

Thus, the successful detection of the returning signal requires the very best that modern electronics has to offer. Indeed, the noise generated by even the most modern low-noise amplifier (LNA) and other sources are orders of magnitude greater than the signals being examined. Dana Whitlow, research technician at Arecibo, estimates that the return signals may be over 40 dB below the overall system noise level—a factor of 10,000 lower!

Critical Sensitivity To Noise
Simply put, everything that can be done is done to maximize the sensitivity of the receivers. The front-end electronics are cytogenetically cooled in 99.99% pure Helium to between 10 and 15 Kelvin. These temperatures can only be achieved in a vacuum. As a result, all of the specially designed electronic systems must be evacuated before the cooling can begin.

The front-end electronic systems consist of amplifiers, filters, and mixers. The amplifiers are specifically designed to minimize noise. Toward that end, Ganesan Rajagopalan, a senior receiver engineer and head of the Electronics Deptartment at the observatory, has been improving the sensitivity of the receivers by slowly replacing the existing gallium-arsenide (GaAs) monolithic microwave integrated circuits (MMICs) with indium-phosphide (InP). MMICs are devices that operate at microwave frequencies between 300 MHz and 300 GHz.

InP-based amplifiers have lower noise and higher gain than their GaAs counterparts. Yet these circuits also must be customized for the lowest noise possible. The Cornell University-based team at Arecibo collaborated with the experts at CalTech’s JPL team to make these customized application-specific integrated circuits (ASICs) tailored to a cryogenic environment. The CalTech design also has been implemented at the Allen Telescope Array (ATA) in California. ATA is a “large number of small dishes” (LNSD) array that’s designed to be highly effective for simultaneous surveys of conventional radio-astronomy projects and Search for Extraterrestrial Intelligence (SETI) observations at centimeter wavelengths.

With such innovative LNA devices, it’s no wonder that the Arecibo Observatory is considered state of the art in receiver technology. In terms of the available bandwidth per receiver, however, the facility is playing catch-up. The receivers used at Arecibo are 2 GHz wide, ranging from 2 to 4 GHz and another from 4 to 8 GHz. The goal is to widen the current 2-GHz signals, which are being received using Ultra Wideband (UWB) technology. Here too, the R&D team is working with other scientists and engineers around the globe to develop a UWB feed that will operate from 1 to 10 GHz. Such a feed would reduce the number of existing receivers from 8 down to 1, which would further reduce the collective number of noise generators in the system.

A Noisy Planet
Reducing the noise sensitivity of the receiving electronics is critical to analyzing the radio signals returning from deep space. But another challenge exists closer to home— namely, the effective “noise” created by wireless devices ranging from cell phones to data devices. The RF telescope operates to 10 GHz and includes receivers in the S-, C-, and X-bands. Wi-Fi technology occupies a relatively small bandwidth centered around 2.4 GHz—right in the middle of the lower S-band space. Another source of radio interference comes from a much more powerful source—namely, the various airports on the island. These sources are mission critical and cannot be turned off at select times during the day.

To help reduce the opportunities for radio noise interference, the Arecibo team actively works with the Puerto Rico Spectrum users’ group. In cases involving mission-critical systems like airport radar, the team has coordinated the on-off time of the radar. The airport radar goes blank for a short period of time when it points in the direction of the Arecibo observatory. Unfortunately, this well-intentioned gesture has proven to be of limited value. The radar signal has more power located in the back lobes of the radar signature than in the front lobes.

Sci-Fi Becomes Reality
As fascinating as the engineering work at Arecibo is, does it really have any practical value? Can it turn science fiction into science fact? Some would suggest that the jungle-hidden facility will play an important role in saving humanity from near-earth objects (NEOs) like asteroids, which may be on a collision course with earth. The RF Observatory has the capability to pinpoint the orbit of NEOs as far away as Jupiter or Saturn and then calculate whether that object poses a threat to humanity. Such knowledge could be used to evacuate populations and move important property to a safe location. This is just one reason why the U.S. Congress is interested in keeping the Arecibo radar telescope working.

“We are also doing a lot of work on pulsars,” explains Rajagopalan. “Pulsar timing is very important in the detection of gravitational wave radiation.” Described as a fluctuation in the curvature of spacetime, which propagates as a wave, gravitational waves were predicted by Albert Einstein’s theory of general relativity. Sources of gravitational waves include binary star systems (e.g., white dwarfs, neutron stars, or black holes).

Pulsar astronomers believe that they can detect gravitational waves. Telescopes at Arecibo, PR and the mainland US, Europe, and Australia are all part of an array that’s being used to carefully time pulsars. All of these facilities make very long, simultaneous observations of the same deep-space source using long baselined interferometry (LBI). Precise synchronization timing among the global facilities is achieved using a hydrogen maser atomic clock. Thus, the research being done here is not just astronomy. It’s planetary radar science and ionospheric as well.

Signal Processing
What happens to the signal returning from the reflection off of nearby planets or from signals originating from a deep-space pulsar? The signal comes into the feed in a concentrated form after reflection from the big reflector (see Figure 3). An ortho-mode transducer (OMT) —some more than 3-ft. long—splits the signal into two separate channels. Noise-injection couplers are connected to one channel. These couplers inject a weak but carefully calibrated noise source into the main signal.

The injected noise signal is switched on and off at a rapid rate that’s called a “winking” rate calibration, says Dana Whitlow, a senior receiver engineer. “By a measurement of the levels later in the system with the cal on and the cal off, we can determine the system noise temperature. Also, this calibration allows us to track unique time-dependent changes and gain of the amplifiers.”

The signal then travels through isolators, which flatten out the frequency response. Effectively, they remove reflections from the amplifiers back into the earlier part of the signal path. Finally, the signal is amplified in the LNAs mentioned earlier.

All of these electronics are contained with a dewar, which is used to cool the amplifiers down to 15 Kelvin. Cables connect the dewar to the next signal-conditioning module, which contains a pulse amplifier module to provide additional amplification. Computer-selectable filters are used to exclude unwanted frequency bands, limiting the bandwidth from radio-interference sources like Wi-Fi and airport radar.

What happens if the ionospheric, planetary, or deep-space phenomena that a researcher is trying to study occur at the same frequency as the radio-interference sources—perhaps centered at 2.4 GHz (same as Wi-Fi)? To study these signals, researchers would have to go to one of the other RF telescope facilities on the mainland United States. For example, the Robert C. Byrd Green Bank Telescope in West Virginia operates in a radio quiet zone.

Aside from rejecting unwanted interference signals, filters also help to prevent the interference from compressing the gain of the subsequent signal chain. If it’s strong enough, an interfering signal could drive an amplifier into saturation. This forces the gain to go down, says Whitlow. “If there’s anything that radio astronomers hate, it’s unexpected gain changes in their signal path. It’s difficult, if not impossible, to deal with from a perspective of obtaining calibrated data of their signal or source they are looking at.” After more filtering and amplification, just to increase the signal strength, the signal is then downconverted to a lower, intermediate frequency.

One might wonder if all of these filters don’t attenuate the signal even further—especially because they are passive filters, which contain no power source to help boost the signal strength. While it’s true that passive filters attenuate the signal slightly, these attenuations can be corrected by the numerous amplifiers. Active filters would have their own problems, such as the introduction of extra noise and distortion.

Finally, the conditioned signal is sent down from the receiver platform to the control-room area some 500 m below using analog optical fiber cable. Fiber-optic cable is used because it has a much broader frequency response. Plus, it doesn’t pick up electrical noise due to the imperfect shielding of coaxial cable. Fiber cables are typically much less lossy than coaxial—especially at the higher frequency ends.

Perhaps the most compelling reason for fiber over coaxial cable is that the former doesn’t conduct lightning down to the control room, explains Whitlow. “I haven’t been down here to see this firsthand, but I’ve been told by many people that in the early days of the observatory, when lightning struck the platform, there would be sparks jumping around things inside the control room.”

Coming in Part II: We’ll delve into the technology used in the control room and laboratory, where the data is digitized and analysis is performed. Of particular interest to chip and embedded designers will be the evolution taking place from ASIC- to FPGA-based systems.