By John E. Blyler
The huge RF radio observatory at Arecibo, Puerto Rico has all of the key ingredients for a high-tech adventure movie. First, its location is remote, as it’s buried deep within the rainforest of a Caribbean island. Second, the sheer size of the radio telescope renders it sublime. It measures 305 m (1001 ft.) in diameter and more than 500 m from the jungle floor to the top of the moveable radio feed platform (see Figure 1). Unlike other astronomic R&D facilities in the United States, the observatory at Arecibo also is more than just a radio telescope. It also is a complete R&D facility. Its mission – in part – is to search for the stuff of science fiction stories ranging from extraterrestrials and gravity waves to asteroids that could devastate the Earth.

We will return to the cool sci-fi aspects of Arecibo later. For now, let’s explore the technology that makes all of this possible—starting with an overview of the RF telescope and the critical electronics. Radio astronomy studies celestial objects using radio transmissions. Often traveling great distances, these radio waves are reflected from the objects of study. The returning signal is analyzed and developed into amazing images. Although this may seem like a straightforward task, the returning signal is typically so weak as to be almost indiscernible from the cosmic noise.

Thus, the successful detection of the returning signal requires the very best that modern electronics has to offer. Indeed, the noise generated by even the most modern low-noise amplifier (LNA) and other sources are orders of magnitude greater than the signals being examined. Dana Whitlow, research technician at Arecibo, estimates that the return signals may be over 40 dB below the overall system noise level—a factor of 10,000 lower!

Critical Sensitivity To Noise
Simply put, everything that can be done is done to maximize the sensitivity of the receivers. The front-end electronics are cytogenetically cooled in 99.99% pure Helium to between 10 and 15 Kelvin. These temperatures can only be achieved in a vacuum. As a result, all of the specially designed electronic systems must be evacuated before the cooling can begin.

The front-end electronic systems consist of amplifiers, filters, and mixers. The amplifiers are specifically designed to minimize noise. Toward that end, Ganesan Rajagopalan, a senior receiver engineer and head of the Electronics Deptartment at the observatory, has been improving the sensitivity of the receivers by slowly replacing the existing gallium-arsenide (GaAs) monolithic microwave integrated circuits (MMICs) with indium-phosphide (InP). MMICs are devices that operate at microwave frequencies between 300 MHz and 300 GHz.

InP-based amplifiers have lower noise and higher gain than their GaAs counterparts. Yet these circuits also must be customized for the lowest noise possible. The Cornell University-based team at Arecibo collaborated with the experts at CalTech’s JPL team to make these customized application-specific integrated circuits (ASICs) tailored to a cryogenic environment. The CalTech design also has been implemented at the Allen Telescope Array (ATA) in California. ATA is a “large number of small dishes” (LNSD) array that’s designed to be highly effective for simultaneous surveys of conventional radio-astronomy projects and Search for Extraterrestrial Intelligence (SETI) observations at centimeter wavelengths.

With such innovative LNA devices, it’s no wonder that the Arecibo Observatory is considered state of the art in receiver technology. In terms of the available bandwidth per receiver, however, the facility is playing catch-up. The receivers used at Arecibo are 2 GHz wide, ranging from 2 to 4 GHz and another from 4 to 8 GHz. The goal is to widen the current 2-GHz signals, which are being received using Ultra Wideband (UWB) technology. Here too, the R&D team is working with other scientists and engineers around the globe to develop a UWB feed that will operate from 1 to 10 GHz. Such a feed would reduce the number of existing receivers from 8 down to 1, which would further reduce the collective number of noise generators in the system.

A Noisy Planet
Reducing the noise sensitivity of the receiving electronics is critical to analyzing the radio signals returning from deep space. But another challenge exists closer to home— namely, the effective “noise” created by wireless devices ranging from cell phones to data devices. The RF telescope operates to 10 GHz and includes receivers in the S-, C-, and X-bands. Wi-Fi technology occupies a relatively small bandwidth centered around 2.4 GHz—right in the middle of the lower S-band space. Another source of radio interference comes from a much more powerful source—namely, the various airports on the island. These sources are mission critical and cannot be turned off at select times during the day.

To help reduce the opportunities for radio noise interference, the Arecibo team actively works with the Puerto Rico Spectrum users’ group. In cases involving mission-critical systems like airport radar, the team has coordinated the on-off time of the radar. The airport radar goes blank for a short period of time when it points in the direction of the Arecibo observatory. Unfortunately, this well-intentioned gesture has proven to be of limited value. The radar signal has more power located in the back lobes of the radar signature than in the front lobes.

Sci-Fi Becomes Reality
As fascinating as the engineering work at Arecibo is, does it really have any practical value? Can it turn science fiction into science fact? Some would suggest that the jungle-hidden facility will play an important role in saving humanity from near-earth objects (NEOs) like asteroids, which may be on a collision course with earth. The RF Observatory has the capability to pinpoint the orbit of NEOs as far away as Jupiter or Saturn and then calculate whether that object poses a threat to humanity. Such knowledge could be used to evacuate populations and move important property to a safe location. This is just one reason why the U.S. Congress is interested in keeping the Arecibo radar telescope working.

“We are also doing a lot of work on pulsars,” explains Rajagopalan. “Pulsar timing is very important in the detection of gravitational wave radiation.” Described as a fluctuation in the curvature of spacetime, which propagates as a wave, gravitational waves were predicted by Albert Einstein’s theory of general relativity. Sources of gravitational waves include binary star systems (e.g., white dwarfs, neutron stars, or black holes).

Pulsar astronomers believe that they can detect gravitational waves. Telescopes at Arecibo, PR and the mainland US, Europe, and Australia are all part of an array that’s being used to carefully time pulsars. All of these facilities make very long, simultaneous observations of the same deep-space source using long baselined interferometry (LBI). Precise synchronization timing among the global facilities is achieved using a hydrogen maser atomic clock. Thus, the research being done here is not just astronomy. It’s planetary radar science and ionospheric as well.

Signal Processing
What happens to the signal returning from the reflection off of nearby planets or from signals originating from a deep-space pulsar? The signal comes into the feed in a concentrated form after reflection from the big reflector (see Figure 3). An ortho-mode transducer (OMT) —some more than 3-ft. long—splits the signal into two separate channels. Noise-injection couplers are connected to one channel. These couplers inject a weak but carefully calibrated noise source into the main signal.

Figure 3: Antenna feed and electronics on platform suspended 500 ft above the main reflector dish floor.

The injected noise signal is switched on and off at a rapid rate that’s called a “winking” rate calibration, says Dana Whitlow, a senior receiver engineer. “By a measurement of the levels later in the system with the cal on and the cal off, we can determine the system noise temperature. Also, this calibration allows us to track unique time-dependent changes and gain of the amplifiers.”

The signal then travels through isolators, which flatten out the frequency response. Effectively, they remove reflections from the amplifiers back into the earlier part of the signal path. Finally, the signal is amplified in the LNAs mentioned earlier.

All of these electronics are contained with a dewar, which is used to cool the amplifiers down to 15 Kelvin. Cables connect the dewar to the next signal-conditioning module, which contains a pulse amplifier module to provide additional amplification. Computer-selectable filters are used to exclude unwanted frequency bands, limiting the bandwidth from radio-interference sources like Wi-Fi and airport radar.

What happens if the ionospheric, planetary, or deep-space phenomena that a researcher is trying to study occur at the same frequency as the radio-interference sources—perhaps centered at 2.4 GHz (same as Wi-Fi)? To study these signals, researchers would have to go to one of the other RF telescope facilities on the mainland United States. For example, the Robert C. Byrd Green Bank Telescope in West Virginia operates in a radio quiet zone.

Aside from rejecting unwanted interference signals, filters also help to prevent the interference from compressing the gain of the subsequent signal chain. If it’s strong enough, an interfering signal could drive an amplifier into saturation. This forces the gain to go down, says Whitlow. “If there’s anything that radio astronomers hate, it’s unexpected gain changes in their signal path. It’s difficult, if not impossible, to deal with from a perspective of obtaining calibrated data of their signal or source they are looking at.” After more filtering and amplification, just to increase the signal strength, the signal is then downconverted to a lower, intermediate frequency.

One might wonder if all of these filters don’t attenuate the signal even further—especially because they are passive filters, which contain no power source to help boost the signal strength. While it’s true that passive filters attenuate the signal slightly, these attenuations can be corrected by the numerous amplifiers. Active filters would have their own problems, such as the introduction of extra noise and distortion.

Finally, the conditioned signal is sent down from the receiver platform to the control-room area some 500 m below using analog optical fiber cable. Fiber-optic cable is used because it has a much broader frequency response. Plus, it doesn’t pick up electrical noise due to the imperfect shielding of coaxial cable. Fiber cables are typically much less lossy than coaxial—especially at the higher frequency ends.

Perhaps the most compelling reason for fiber over coaxial cable is that the former doesn’t conduct lightning down to the control room, explains Whitlow. “I haven’t been down here to see this firsthand, but I’ve been told by many people that in the early days of the observatory, when lightning struck the platform, there would be sparks jumping around things inside the control room.”

Coming in Part II: We’ll delve into the technology used in the control room and laboratory, where the data is digitized and analysis is performed. Of particular interest to chip and embedded designers will be the evolution taking place from ASIC- to FPGA-based systems.

By Ed Sperling

For decades, analog and digital engineers have lived in completely separate worlds. The lines are blurring between those worlds, though, in complex SoCs. So far, the transition has been difficult, and most engineers predict it will get worse at future process nodes.

The basic problem is that each world has functioned independently of the other from the start. They use different tools, they work on different schedules and they generally think about problems from a different vantage point. There are some very good reasons for this. In the digital realm, designs typically last only a year or two. In pure analog, they can last a decade, with a major emphasis on having a specification that’s performance tuned to be just a notch better than the competition.

“These have been two very distinct markets,” said Ed Lechner, director of product marketing for custom design at Synopsys. “One is for standard analog parts, which is the world of Linear, Analog Devices and Fairchild. Their most popular node is 180nm and they tune for maximum performance. At the other end of the spectrum are the digital engineers who are working at 32nm and 45nm. They’re willing to forgo getting maximum performance for a quick and dirty solution so they can get the product out the door in time for the Christmas season.”

But pushing down to the leading edge of Moore’s Law also has opened up an enormous amount of real estate. That creates the opportunity to shrink a bill of materials, and therefore the cost, by combining functions that formerly were on multiple chips into a single chip. This is where analog meets digital, and the relationship—uneasy at a distance—is becoming even rockier when both functions are being forced to work in sync on the same development schedule.

Linda Fosler, marketing director in Mentor Graphics’ deep submicron division, just returned from a European tour where she met with 10 of Mentor’s top customers there. She said those companies want to be able to design mixed signal chips in the same time frame as digital chips and without having to boost the number of engineers to get the job done on schedule.

“One problem we’ve heard is that respins have made companies late to market, which is very costly to them,” Fosler said. “The problem is that the interface between the analog and digital blocks is not tested until the last minute because these teams aren’t working together. The industry needs to address implementation effects—basically the parasitics—of what affects the final qualification of silicon. It must be dealt with iteratively at the layout and schematic level, and built into the tools. We also have to build more intelligent manufacturing awareness into the tools.”

Failure to communicate

The fact that engineering teams are spread out around the globe doesn’t help matters. Even when analog and digital engineers are locked in the same building, they tend not to talk to each other. But none of the tools for developing chips have been constructed to deal with collaboration between teams, which is why most design is done in discrete units defined by the chip architects.

The problem is that in a mixed signal chip, it’s not just the teams that have to communicate. What they’re developing has to work well together, too.

“We’ve heard from some customers that to complete a chip in a compressed schedule, they tape out on tapeout day, whether they’ve finished the simulation or not,” said Bradley Geden, product marketing manager for AMS circuit simulation at Synopsys. “This is what causes re-spins. What’s needed is a formal methodology with sufficient verification and sufficient coverage in an AMS block.”

So far, that methodology doesn’t exist. Nevertheless, the amount of mixed signal content shows no sign of decreasing. Even with digital components there is growing analog content.

“As soon as you add analog onto a chip, the chance of respins increases three times,” said Mar Hershenson, vice president of product development in Magma’s custom design business unit. The schedule is more complex and the tools allow us to put more content on a chip. But they need to work much better. A lot of companies complain they don’t have enough analog designers, but the digital people and the analog people don’t speak the same language and they don’t have the same tools. When it comes time to integrate, that’s where the problem begins.”

Nevertheless, she said the real selling point for mixed signal chips is integration. The less work the customer has to do to integrate those functions, the more attractive a company’s technology looks.

Conclusion

Most tools vendors see mixed signal as an opportunity. They recognize that analog will never be completely automated because some functions will always be customized for a specific chip. But it can at least be enabled and integrated better into the complex design process that includes both digital and analog.

This becomes particularly important as analog engineers are forced to fit into digital design schedules. Getting a design out the door, relatively bug free and on schedule has been achievable so far primarily by ramping up the number of engineers working on those chips. There’s a bundle of money available to the tools vendors that can reduce that pain, and the race is already well under way.

System-Level Design sat down to discuss mixed signal design with Robert Hum, VP and general manager of Mentor Graphics’ Deep Submicron Division; Mar Hershenson, VP of product development in Magma’s custom design business unit; Eric Filseth, CEO of Ciranova, and John Stabenow, group director for solution and product marketing at Cadence. What follows are excerpts of that conversation.

By Ed Sperling
SLD: Analog has always been considered more art than science. How far has it come, and will it ever be automated?
Stabenow: It depends on your time frame. If you’re talking about the slide rule days, we’ve come a long way. If you’re talking about since 2001, we haven’t come that far.
Filseth: That’s right. The basic way of doing analog design hasn’t changed much over the last 15 years. The tools that support the original way of doing it have gotten incrementally better, but it certainly looks like we’ve hit a point of diminishing returns for how productive you can get the traditional methodology to be. The basic concept of how this is done—simulation, handcrafted layout, schematic layout, PDKs, parameter accels—have been there a long time. It isn’t likely to get twice as efficient under the current path.
Hershenson: The biggest change in the past 10 to 15 years has been in simulation and the capacity of the circuits it can handle today. But fundamentally it’s the same.

SLD: But how about the designs?
Filseth: They’ve changed dramatically. They are a lot more complicated. There are a lot more transistors in an analog/mixed signal design. We don’t see that much pure linear analog anymore. It’s all mixed signal.
Hershenson: The main tools for mixed signal are editors and simulators. That’s about it.
Filseth: If you think about the last major advancement, it’s shape-based routing, although arguably it’s used for assembly.
Hum: The digital domain has had the luxury of a unifying paradigm—RTL. That is the central idea that has driven abstract-to-specific automation. The digital side has parametrically focused on timing, but now that power has been added it’s getting more difficult. It’s hard to analyze timing and power. In the analog world there has not been, and there is unlikely to be, a unifying paradigm. The things that define phase lock loops are quite different from the things that make USB 2.0 PHY’s work.

SLD: So where will progress come from?
Hum: In the analog world, whatever progress there is will come from top-down, domain-specific approaches. What you used to do filter synthesis in the old days was a filter package. That doesn’t help for A-to-D conversion. In the analog world, the name of the game in automation is going to be tuned to vertical tracks, and it’s going to be pretty specific. In the next 10 years, there may not be any breakthroughs in this area. There is nothing happening in a coordinated way to create the automation for these small areas.
Filseth: That varies a little bit depending upon where you are in the flow. As you get closer to the architecture, you get more specialized. As you get closer to the silicon, things get more horizontal. And the level of horizontal-ness increases as you get closer to tapeout.

SLD: Is there room to do the different pieces separately?
Stabenow: It does have to be done together. We’re seeing mixed signal everywhere. But that doesn’t necessarily lead you to an analog automation path. You have this automation path on the digital side—things you can do with machines. But in the analog perspective, other than analog macros it’s all being done from scratch and by hand.
Hershenson: The A-to-D converters and phase lock loop are fundamentally different blocks, but they do share a lot of components. In a filter, a main block is a Gm cell or an Op Amp. It’s the same in some types of ADC. There is some commonality on the blocks being used in the different circuits. Otherwise in school we’d have to take 50 classes to become an analog designer. There are some concepts like linearity and gain that are common to different applications. The other thing we’re seeing is talk about integration shortening the design flow. It hasn’t happened. But one thing that has happened is that because of the complexity, there are many more data converters and PLLs on the chip. In digital blocks, high-speed I/Os have a ton of analog content.
Filseth: In the past half-dozen years there’s been a very interesting market split in analog/mixed signal. Traditionally, analog and mixed signal content was on a separate chip. If you were an analog/mixed signal IC company making data converters, you competed with another analog/mixed signal IC company on who had the best integral non-linearity spec on the data converter. Your chip would go onto a circuit board on an MRI system, and the lifespan would be seven years or more. In that sector, pure quality result is critical. Time to market was important, but not critical. You chose the best silicon technology for the job. If it was half-micron CMOS, that’s what you used. In the past half-dozen years, there’s been a different kind of analog/mixed signal chip. Anyone doing a networking chip needs a high-speed SERDES. People want to put PHY radios on a single SoC. The dynamics of the analog/mixed signal content is different. You’re not competing on specifications for your data converter. You’re competing on how fast you can get all this stuff out the door and will you be in time for Christmas? In this kind of market, what counts is good quality results. But top priority is getting all of this stuff integrated together. This is the part of the market that’s growing fastest.
Stabenow: I wonder if the automation won’t come in the form of macro IP. The big SoC guys will buy analog blocks. That means the design problem still exists back at the beginning where they’re generating the IP.

SLD: Is this a problem of people being used to doing things certain ways?
Hershenson: The new generation is different than the old generation. If you were working at Linear or Analog Devices and you got a 1% better gain in your Op Amp, you were king for a day. The major universities like Stanford and MIT have industry-funded programs to improve the analog design flow. Just having the core isn’t enough. You have to figure out how to put systems together. Systems are not just for cell phones. They’re for cars and bio-engineering. This is just beginning. It’s training analog designers plus CAD. The new people we interview know MATLAB and they’re not afraid of writing a Tcl script. I think that’s going to help a lot.

SLD: So what pieces can be automated?
Hum: There are several areas. There is a market developing for big D, little A, where little A is a hard analog block or some kind of malleable parameterized thing that’s a block generator. The problem is verifying that you’ve embedded the analog block and that it’s happy in its embedded location. We need the equivalent of analog assertions. In the digital world, you’ve got the digital assertion space, which looks at protocols between blocks. In the analog world, there is a set of assertions you can come up with. They’re clearly incomplete. Step one is to make sure it’s embedded right, that you understand the boundary and the handshake and transactions that go across it. Big D people wouldn’t know a transistor if it hit them. That’s not how they’re trained. They’re trained in finite state machines, complexity and how to do an 80-million gate design. All you want to know about your analog blog is that you’ve embedded it right. If you had a model that’s plus or minus 10% accurate, that’s enough.

SLD: So what’s the solution?
Hum: There are people working on these non-linear response surface models, which is one approach to it. There’s other work to look at automatic extraction mechanisms. Once you have a circuit and want to get a facsimile of that circuit in the digital domain, you need an interpolation function. There’s good work going on there in universities to generate interpolation functions. This is a different approach than synthesis. It’s de-synthesis. I have the polygons and the transistors and the SPICE mode

It was a good week for team approaches and an overall brighter outlook for the industry.

Synopsys teamed up with ARM to boost efficiency for ARM’s AMBA 3 interconnect, configuring the interconnect to eliminate unnecessary logic. That ripples down into better performance, lower power and less routing on an SoC. So now what do you do with all that space you’ve just opened up? See below.

Speaking of team approaches, TSMC and Cadence teamed up to provide a 65nm mixed signal/RF reference design kit focusing on behavioral models and a reference flow. Included in the release is a phase-locked loop noise-sensitive reference design. This is the most recent in what is expected to be a flood of tools aimed at the analog and mixed signal market, something that will become critical in SoCs that incorporate more and more functions to soak up all that extra space each process node provides. While the digital engineers will likely use whatever comes their way, the analog engineers are a lot pickier about these things. A big plus is that the reference design kit will help with mixed signal verification, which is where the real time savings are needed.

The auto industry may be down, but that doesn’t mean you don’t make tools to improve its efficiency. Mentor Graphics rolled out an integrated design environment for the Automotive Open System Architecture (AUTOSAR) system that uses standard interfaces and components dictated by AUTOSAR. Anything that helps Detroit regain its footing is good for the entire industry, given the number of electronics components that are finding their way into cars these days.

ARM unveiled physical IP for TSMC’s 40nm G process, balancing performance with lower power. The target markets are consumer devices like set-top boxes, disk drives, mobile computing devices, HDTV and graphics processors. Included is a power management kit and ECO kit library extensions for addressing current leakage by replacing or complementing the HVt, RVt or LVt implant layers with long channel-length devices.

Handset sales are stabilizing. TriQuint Semiconductor posted 7% gains in total revenues in the first quarter of 2009 compared to the same period in 2008, including a 24% growth in handsets. Given the fact that no one likes to be locked into a contract for more than two years, and the ongoing recession has been under way for 16 months, it’s getting to be that time for many people.

Computer sales revived in the past quarter. Intel posted Q1 revenue of $7.1 billion, along with a statement from CEO Paul Otellini that the industry is “returning to normal seasonal patterns.” There’s only so long you can keep an old laptop computer or server blade going before it starts costing you big bucks in productivity loss. The big question is whether the replacement is a new computer or a netbook or smart phone—or whether it’s some combination of those.

AMD reported revenue of $1.8 billion during Q1, which was flat compared to the fourth quarter of 2008. While it was down 21 percent from Q1 of 2008, it’s not exactly an apples-to-apples comparison because AMD no longer has an in-house fab. Still, it was better than anyone expected, even with an operating loss of $308 million. 

And finally, the whole market continued its drive upward. Both the Dow and the Nasdaq have been posting gains for weeks. While it’s too early to tell if this upward trend will stick, the market usually runs 6 to 12 months ahead of the overall economy, depending upon who you listen to. At the very least, it’s a signal for the foundries to begin starting up their machinery again and for companies to begin developing products for next holiday season.

–Ed Sperling

Analog and mixed signal IP began closing the gap with digital core IP in design explorations in the first two months of this year, a clear sign that multicore systems on chip have emerged as the dominant semiconductor model and that the architecture requires both types of IP.

While it’s too early to tell this year what effect that will have on overall design activity—the economy is the real determining factor there—the convergence is pronounced. In January, when chip design exploration typically is at its lowest even in a good year, there were 894 digital IP core explorations vs. 427 for analog and mixed signal. Last month, the number for digital had grown to 2,729 while those for analog/mixed signal had increased to 2350.

Off-chip interface IP also is becoming important, although to a far lesser extent. Much of that work is still being done by hand, but many industry insiders believe that approach will change over the next couple of process nodes as design engineers are called upon to add more context to their designs, including software applications and application interfaces, as well as connections at the board level. The exploration with off-chip interfaces was 211 in February, up from 75 in January.

On chip bus IP activity, meanwhile, was 173 in January vs. 327 in February, and verification IP—still in emerging market mode—showed 9 investigations in January and 28 in February.

January (blue) vs. February design investigations.

–Ed Sperling

By Cheryl Ajluni

In spite of all of its hype, WiMAX is not the only standard causing a stir these days or being called a “killer app.” Another technology that has achieved this illustrious title is Long Term Evolution (LTE), the Third Generation Partnership Project’s (3GPP’s) air interface for wireless access.

Granted, WiMAX does have the advantage of a head start in development, testing and deployment, but LTE is gaining momentum. According to a new ABI Research report, more than 18 operators globally have announced LTE deployment plans, and the tough economy seems to have done little to dampen their enthusiasm. Verizon accelerated its LTE deployment timetable, moving its launch forward from 2010 to 2009. NTT also is likely to deploy LTE in Japan in 2009. By 2013, operators are expected to spend over $8.6 billion on LTE base station infrastructure alone.

The difficulty with these projections is that LTE is an evolving technology (e.g., its MAC and upper layers are still be finalized) and therefore subject to change and interpretation. Specifications for the LTE radio interface are stabilizing, but this uncertainty leaves room for error and further complicates an already challenging design and test process. Nevertheless, chipsets, infrastructure and devices currently are being developed for commercial launch. Much of the pressure for successful development falls to the system-level engineer, who must accurately and cost-effectively design and test for the moving target that is LTE. How can this goal be achieved? Let’s take a closer look.

Understanding the Options

While LTE is expected to offer both consumers and operators a number of key benefits (e.g., lower costs, better services and an increase in data rate with lower latency), the complexity resulting from its use of technologies like SC-FDMA in the uplink, multiple antenna configurations and OFDMA, presents a host of engineering challenges to the engineer. LTE’s variable channel bandwidths further add to this complexity. Challenges also stem from the dependence of LTE system performance on its baseband and RF subsystems, both of which are subject to impairments like nonlinearities, multi-path and fading.

Dealing with this complexity and the resulting challenges is no easy task. As Frank Ditore, product marketing manager at Agilent Technologies points out, “For the system-level engineer working with LTE, or any emerging technology for that matter, there is simply nothing to validate their designs against. There is no LTE base station against which a designer can test their handset design. So, right from the very beginning the engineer faces uncertainty.”

Anritsu offers a solution to this dilemma. Its new MD8430A Signalling Tester is intended for developers who want to verify the operation of a new LTE terminal, but are unable to connect to an actual base station. As a base station simulator, this solution offers the functions needed to test the performance of 3.9G mobile terminals supporting the LTE standard.

What are some of the designer’s other options? The first alternative is to guess. In this case, the engineer builds a device with LTE functionality and hopes the design is correct. If the device was not designed properly, the engineer would unfortunately not realize this until after the design was fabricated. The design would then need to be fixed and fabricated again—a costly and time consuming process and one that’s not likely to receive much support given the current economic situation.

The other alternative is to use early design solutions with algorithms created by a company that’s closely involved with the LTE specification. Granted these solutions and the algorithms on which they are based will not be perfect as LTE is not yet finalized, but they do increase the engineer’s confidence that his/her design is correct. Over time these algorithms will become more mature and the design solutions that employ them will likewise mature, further raising the engineer’s confidence. And, since algorithms used in early design solutions ultimately find their way into measurement solutions, test equipment like signal analyzers, signal generators and network emulators that employ these algorithms also will be mature. Using design tools and measurement solutions from the same company is one way to ensure access to the most mature algorithms.

Agilent Technologies is one company offering solutions that span the entire LTE development lifecycle. In addition to its Advanced Design System (ADS) and the ADS Wireless LTE Library for design simulation and verification, the company also offers a range of pattern generators, logic analyzers, signal generators, signal analyzers, and network emulation and protocol development tools—all of which support early R&D in components, base station equipment and user equipment.

Successful Design And Test

Regardless of which company’s design and test solutions that are used, there are a few key tips for the engineer to keep in mind:

1. Design simulation can be a valuable ally in addressing LTE development challenges and in verifying the engineer’s interpretation of the LTE standard. Its uses are multi-purpose: enabling the engineer to perform system-level trade-offs early in the design cycle to determine design requirements and specifications, and enabling evaluation of the system’s RF/mixed-signal performance by simulating RF and baseband designs together in one simulation environment. Additionally, combining design simulation with test equipment provides added flexibility in addressing testing needs for LTE.

   One solution capable of enabling such functionality is Agilent’s SystemVue 2008 (see Figure 2). This new electronic design automation platform provides an easy-to-use environment with simulator and modeling technologies, along with links to hardware implementation and test. It allows algorithm creation and prototyping for challenging communications system architectures at the physical layer. It also bridges the design flow gap between algorithm developers and the mainstream design community and lowers the cost of ownership by unifying a disjointed flow at an affordable price.

2. For design and test accuracy, select tools from a company with known good algorithms and models.

3. Consider purchasing design automation tools and measurement solutions from the same company, as its algorithms will become much more mature as they trickle down from design automation tool to measurement solution.

4. Foster a close working relationship with the company from whom you purchase design tools and/or measurement solutions. You want to know what your vendor is doing to address changes in the LTE specification and that they are fully committed to making updates to their solutions, as necessary, in a quick and efficient manner.

5. According to Andrew Kodarin, business development manager, Anritsu, another key tip is to “verify that the solutions you purchase are future proof and will preserve your investment.” In other words, ensure that the tools can be expanded to support future developments in the standard and that you won’t have to buy a new solution every time the specification changes.

Summary

There is no denying the current buzz surrounding LTE. Despite this, its true test will come on the first day of its commercial launch, when user’s expectations will be at the highest. How well LTE can meet those expectations will ultimately determine its long-term success. Much of this burden will fall to the system-level engineer tasked with designing and testing LTE devices. While some uncertainty in this process is inevitable given the changing nature of the standard, some tips (e.g., using design simulation with known, good algorithms and models) can prove especially useful in helping the engineer achieve a successful design.

System-Level Design sat down to discuss mixed signal design with Robert Hum, VP and general manager of Mentor Graphics’ Deep Submicron Division; Mar Hershenson, VP of product development in Magma’s custom design business unit; Eric Filseth, CEO of Ciranova, and John Stabenow, group director for solution and product marketing at Cadence. What follows are excerpts of that conversation.

SLD: Are we actually getting to the point where we can automate mixed-signal design?

Hum: We can’t automate design, but we have the tools to let the digital guys embed analog stuff without killing themselves.

Filseth: The abstractions in digital meant that designers didn’t have to worry about all the nuances of the silicon. Automation for analog/mixed signal has to do that, too. It has to take care of all the nuances so the designer doesn’t have to know all that stuff intimately.

Hum: Analog design is ugly enough as analog design. We’ve all sped up our simulators and we’re all multithreaded and everyone claims to be superlinear. But if you take your standard circuits that used to work three years ago and you move them to 45nm and you do an abstraction, all of a sudden the parasitic file is 10x as big as it used to be. So you run your model order reduction scheme, you find it’s not quite accurate enough and you back off a bit, but you still find your design is bigger than it used to be because at 45nm all the third-order effects are now first-order effects. Now you’ve got this problem where the parasitics are components and you’re now impacted by lithography. You’ve got proximity problems, stress effects and carrier mobility impact. All of a sudden your design has more parameters than you thought you had. As a community, we have to get better about what we model. It can’t just be thanking the designer for the design because we now have 10x more components in there, and that’s not helping. These third-order effects have to be modeled so you don’t impact the design cycle. There’s another abstraction level that has to come up from the silicon level through the photolithography problems and reflect back into the design cycles.

SLD: What else can be automated?

Stabenow: The fastest time to benefit for the users is in the initial parasitics and getting that fed back to the users. Automation is a scary word. I don’t think you can truly synthesis analog layout yet. We have a pretty good understanding of it, but that’s the first big improvement we can make. Model-based design is the way to get there from the designer’s perspective. Getting feedback about what’s actually going to go on silicon is critical to improving time to market.

Filseth: Clearly, a lot of layout can be automated. How close can these polygons be together? People do this today, they run DRC, it’s not correct. They move them, they run DRC, it’s not correct. They move them again. This is the kind of thing that cries out for computer aided design. So the first step is design rules. The second step is what we consider micro-geometry around devices—interdigitation, abutment, well manipulation, multiple kinds of wells. That can be automated, too. The third piece in analog is that these things need to be aligned, there needs to be symmetry and mirroring and matching. That’s circuit designer intent, and I don’t think that can ever be automated completely. You need an experienced person saying the power output stage on this side and the sensor input stage on this side have to be in a line of symmetry. You can’t infer that automatically. You need a designer to do that. But you can capture intent about, ‘I want that there and that there.’ Clearly you can automate most of layout, and you can assist circuit intent. At 45 or 32nm, that’s a gigantic improvement.

SLD: How about reusable IP blocks?

Hershenson: Hard IP has been tried for more than a decade and hasn’t been very successful. You need a slightly different data converter or a slightly different something else, and slightly different means you have to do it all over again.

Filseth: Or you want it in this footprint for this SoC and that footprint for another SoC.

Stabenow: It works for exactly one case.

Hershenson: That’s why IP companies have turned into services companies. The big semiconductor companies have their central IP groups that generate IP for the rest of the company, and they have the same problems as the companies that generate hard IP. What they’re implementing are soft IP technologies. They’re forcing designers to write analog assertions in the schematic or enter constraints. The thing we’re looking at is how to enable people to create this soft IP. It’s going to be domain-specific. So if it’s high-speed I/O, we’re going to offer ways to write soft high-speed I/O in a way that’s more efficient. I’ve been working for the past 10 years on model-based design and extracting information in a way that it can be optimized. There’s a lot less effort. Models allow you abstract proximity effects, parasitics, system effects, circuit effects and layout constraints all at the same level. This is by no means an industry standard, but there is some adoption.

Filseth: We’re seeing a pickup in constraint-driven design, as well. It’s a simple step forward. It’s not automation, but it’s a re-use of IP. It may be something as simple as, ‘What was the designer’s intent?’ The designer may have moved onto a new company, but at least the intent was there and it’s not in the form of a hand-written napkin.

Hershenson: Exactly. That’s the direction we’re all going. What’s going to be the next generation will be a platform where you can model your circuit in a unified way so you can use it for design, verification and visual model abstraction.

SLD: Can you potentially take analog and doing it in digital?

Hum: The other way of doing things is to use a DSP and do it in digital. But the world is conspiring against that because there’s a power tradeoff. It used to be that whatever was analog went digital, and whatever was digital went into software. Now the issue is that you have to run your processors so fast that you use up a lot of juice. You unbundle your processors and put digital co-processors there. Digital co-processors still use too much juice, so put an analog block there. There’s been a reverse trend of software goes to co-processor, co-processor goes to analog. There’s not a clear trend to turn analog into digital. The only advantage of a digital radio is being able to take two chips and turn them into one.

Hershenson: You still need a big data converter.

Hum: And you still need a gigahertz clock. And then you have to worry about the power. Technically, you can do it. But you need a car battery to go with the phone.

Hershenson: As long as you’re interfacing with the real world, there’s going to be some analog.

Hum: The big D, little A market is there. But there are other markets where there is big A, little D. These devices are smaller. They’re not at 45nm. Some of these things live in your car and handle 1 kilovolt and 50 amps. These are very different markets. In the big A, little D markets, you have to encapsulate the analog and make it safe to use.

Filseth: There are two problems. One is a system integration problem and the other is a design problem.

By Ed Sperling

Santa Clara, CA – User groups are typically good for figuring out the pain points for engineers, but this year’s Mentor Graphics User2User conference was as much about survival skills as it was pain points.

Terry Fox, signal integrity consultant at Terry Fox & Associates, advised engineers working in the high-speed design world to speak in terms that “bean counters can understand.”

“There are two things that bean counters understand,” he said. “Cost and risk. And it’s very dangerous when they think they understand engineering.”

He also said all designs need to leave room for errors in their noise and power budgets and advised engineers that there really are “designs from hell” where nothing will ever work right. One way around that is to make sure that in the pre-layout design review there actually is a layout person. But he said noted that the process must budget enough slack for inaccuracies within that process.

One recurring theme throughout the conference was access to information in a central place. Fox said there needs to be a single location for all critical information in a design. At the board level, Chad Hawkinson, vice president of vertical marketing at PTC, said the missing piece of the puzzle is communication among various engineering groups so that incremental decisions along the way between the MCAD and ECAD teams are effectively communicated.

“The result is less problems toward the end of the process,” he said.

Lack of communication has dogged all aspects of system-level design for years. Cadence’s Open Access database was created in part to create a better method for sharing tools and IP, and partly to improve communication across various groups. That has become particularly important as designs include more software development up front, as various pieces of the entire design become compressed and begin overlapping, and as teams are spread out around the globe.

While all of this is useful information, survival skills may say something about an industry under pressure. It’s no longer just technical information and how-to engineering content, and either the presenters are under pressure or they’re hearing a lot more feedback from engineers about what they’re encountering in the field.

By Ed Sperling

Sept. 24, 2008—Santa Clara, CA—Verifying intellectual property blocks at the bleeding edge of technology is as much guesswork as it is engineering, and the result is often a combination of bad yields, bad chips, and truly bad business choices.

Two panels at the GSA-IP conference here looked at the chip design business at the most advanced process nodes, both arriving at similar conclusions. Because IP has to be developed as early as possible for each node, and because process technology is not stable at first, the marriage starts out like two people who have never met. At best it doesn’t work optimally. At worst, it’s a disaster.

“If I have a brand new standard and IP, I will do the best I possibly can at every node,” said Kamalesh Ruparel, VP and general manager of ASIP Solutions at Virage Logic. “But it can’t be 100% validated. The only thing we can do is put a process in place for consistent improvement.”

Ming Hsu , VP of worldwide IP support at foundry UMC, called it a “chicken and egg problem. We know the process is not mature. It has a learning curve, and that takes time.”

Ruparel noted that large customers often get the benefit of lots of attention from the foundries and know which questions to ask. Midsize companies, meanwhile, typically don’t get fully validated IP. “It is a nightmare for them. You’ve got DFM, ever-changing parasitics and new SPICE models. The problem is that a lot of customers don’t know what to ask for. IP is moving so fast that what we see a lot of times is buzzwords.”

Even where digital IP can be verified, analog typically cannot. The list of things that can go wrong in a mixed signal SoC are endless. Robert Heaton, director of analog solutions architecture at MIPS Technologies, said there are no consistent methods for verifying mixed-signal chips. “It’s not universally formalized,” he said. “There are no tools.”

In addition, because IP is changing so quickly and chips are becoming so complicated, the checklists that companies use to make sure they’ve checked everything are quickly outdated, Heaton said.

Nevertheless, it often is the IP that is the problem in low yields and chips that don’t work. Wayne Dai, CEO at VeriSilicon, said his company has a 90 percent rate for first silicon. He said the other 10 percent is almost always due to IP problems.