Nvidia senior vice president of GPU engineering Jonah Alben talks with System-Level Design about the challenges of designing a graphics chip at advanced process nodes.

By Gabe Moretti
Electronic computing systems have gone through an evolutionary cycle since the invention of the mainframe, and the process is continuing. Semiconductor technology, mostly based on CMOS fabrication methods, has enabled an increase in design complexity and device functionality that have revolutionized the world.

But 20nm processes may be the last that obey Newtonian physics. The next process, 14nm, must deal not only with atomic effects, but most likely with quantum effects. At those dimensions, the laws of physics laws are different and much more costly to obey.

The development of electronic computing devices
A brief history will help clarify this. Until the late ’60s, mainframes were the only way to execute computer programs. The hardware was built by electronic engineers, the operating system and device drivers by system programmers, and application programmers developed application programs to automatically solve specific problems.

The introduction of microprocessors followed the increased capacity of manufacturers to diffuse sufficient transistors on a die, and opened the opportunity to build a computing system on very few—and eventually only one—printed circuit board. The systems were still designed using standard parts from suppliers offering both digital and analog components and continued the separation between hardware and software.

Synopsys’ introduction of the first commercially available digital logic synthesis marked a watershed in the design of computing systems. By 1992 Design Compiler was mature enough to understand the semantic flavor of both VHDL and Verilog. It allowed designers to develop integrated circuits that replaced the functionality of standard components to such an extent that it made that industry relatively obsolete. Only analog components survived, because no one had found a way to synthesize an analog design in a cost-effective manner.

Today ICs containing hundreds of million of transistors are built almost routinely. Analog functions can be easily integrated with digital function using IP cores, or, in some cases, even take advantage of specific analog synthesis applications.

The EDA industry is focused on enabling engineers to do the same thing with every processing node. Integrating more functionality in an IC seems the “thing to do”.

Reality will force a new paradigm.
But during the impressive growth in computing capacity of an IC, the semiconductor industry has failed to manage costs. Financial realities are replacing engineering capabilities as the determining factor in deciding what to build and what markets to serve. The ITRS road map shows that unless a new development paradigm is found, the cost of developing an ASIC could reach the $1 billion mark by 2015. This, of course, is an unsustainable proposition. It just does not make sense.

The generally accepted architectural solution today is to design and build a family of devices. Starting from a common hardware architecture, designers count mostly on software to tailor each device to specific tasks or human interfaces. The aim is to keep manufacturing costs constant, or to slightly lower them by increasing yield, while producing end products that look different enough to entice consumers to purchase a new device in the same family every couple of years.

This strategy is enabled by the fact that CMOS fabrication technology has remained constant enough, from a product design point of view, to allow engineers to focus on integration as the primary goal. The increasingly complex DFM, meanwhile, has followed the rules of Newtonian physics. The last process that supports this approach is now being ready for commercial release—the 20nm node.

To design and develop such complex devices, engineers have had to face the daunting task of designing hardware/software systems in the same amount of time as was required for hardware systems. This has turned out to be impossible, because no one can debug a software system without executing it on the hardware it is destined to use. EDA vendors have used their creativity to provide virtual prototyping capabilities. Just like in the old days when engineers developed instructions set simulators of the CPU, today virtual prototyping aims to allow the development of a model of the hardware system before the system prototype is available.

This is not an easy task, and one that has yet to reach maturity. In the last couple of years Synopsys has focused on developing and supporting efficient virtual prototyping. After purchasing Virtio a few years ago, it discovered that having a virtual prototype of a CPU alone was not enough. It looked for complementary technology and eventually purchased both CoWare and VaST. Last week Synopsys announced the result of the integration of these technologies: the Virtualizer. The product is a big step forward, but it still is based on the common methodology of building a compute system in CMOS.

A possible future
The EDA industry was built to provide tools for hardware designers. This has now morphed in supporting system designers, as well. But the tools still keep hardware and software as separate disciplines that require new methods to co-exist efficiently. In the future designers will have to look at providing complete system solutions that erase this distinction. A system architecture should not be based on the characteristics of hardware or software, but instead on the characteristics of the system itself.

Companies still have to address four fundamental issues in deciding to develop a product: cost (time and resources), power use, chip size and packaging, and product family ROI. These four items taken individually for a new ASIC program may be difficult to solve until development is so far along as to make it impractical to even start the project. That means system tools will be needed not just to estimate, but to predict with enough accuracy both the power consumption and the size of the device.

Reusable IP is a partial solution to the problem, but it is still marketed as a replacement to the old component market. In insufficient number of standards make the choice non-deterministic, at best. Hardware IP integration is still difficult and time consuming as busses become more and more complex. Even with advances in virtual prototyping, software development and integration will continue to increase in difficulty, especially due to the lack of standards in software architecture. There also are no standard platforms—true computing systems tailored to a specific application market. Standard platforms can deliver solutions to both power consumption and packaging, thus simplify the problem considerably.

This isn’t without risk, of course. It potentially puts EDA vendors in the position of competing with their customers. But if the customers fail, so will the EDA industry. EDA must still provide all of the tools necessary to develop a product specific platform, should a customer choose to do so, but an increasing number of companies will require system solutions, not just an inventory of IP components. To successfully grow, EDA must be in the system business, not “just” in the tools business.

By Ed Sperling
The push to 20nm and beyond is creating some interesting gyrations in the EDA industry. While tools vendors continue to work on tools for the latest process nodes, they’re also taking some significant sidesteps.

The first to publicly recognize a shift is under way was Cadence, which last year issued its EDA 360 manifesto. The strategy is to continue investing in existing tool lines while also building an IP integration methodology and a software-down rather than hardware-up approach. With fewer companies able to stay on the Moore’s Law road map, Cadence was the first to offer up its alternative plans.

Over the past week, both Mentor and Synopsys have started unrolling their own diverse strategies. And while none of these companies is willing to give up the cash cows that have sustained their growth—modeling, simulation, synthesis, layout, and verification—there are some interesting new additions to the mix.

Mentor looks up and down
Mentor Graphics is among the most diversified of the three big vendors already, but in its core tools area it has been steadily focused on delivering Moore’s Law in 2D. This week the company began acknowledging that 2D design was running out of steam for an increasing number of companies. While memory and processor makers probably will continue push the limits down to single-digit nanometer designs, even the most advanced SoC developers will start seeing diminishing returns by 20nm, where double patterning will become a requirement.

Wally Rhines, Mentor’s chairman and CEO, said during a speech at Globalpress that the semiconductor industry has been riding the Moore’s Law wave of efficiency for 40 years. He said there are still major advances to be made, but not all of them will be from new process nodes.

“All the cost reduction was from shrinking feature sizes,” he said. “Moore’s Law will dissipate with time, but the learning curve will never dissipate. Shrinking features in 2D will not only be more difficult, but it will be more expensive.”

In other words, the return on investment goes down with each node. At 20nm, double patterning will be required, which will make the economic corollary to Moore’s Law difficult to maintain. “This is the first time a change in area will not provide a big cost reduction,” Rhines said.

Mentor has been rather quiet on 2.5D and 3D stacking until now, but this week it came out strongly in favor of the shift. In 2.5D, an interposer is used to connect various die together. In 3D, through-silicon vias will be used for the connections.
“The most promising solution is to grow in a third dimension,” Rhines said. He said that 3D ultimately will offer huge benefits, but added that “2.5D will last much longer than people expect.”

Mentor’s initial play for this market will be through its Tessent testing capabilities. Testing in 3D is extremely complicated because not all of the standard connections for testing are available in a stacked die. The company also will likely have to tweak its DFM tools, because a yield issue involving three die stacked together is three times as expensive as a single die failure. Many of the other tools sold by the company are expected to be tweaked to work with 3D stacks.

“Over the next two to three years you’ll start seeing products with interposers,” Rhines said, adding that by shortening and widening the channels there will be both significant performance increases and a major reduction in the power needed to drive signals. And as aside, he noted that the first TSV patent was filed by William Shockley in 1958.

Synopsys looks sideways
Synopsys president and CEO Aart de Geus believes there is plenty of life left in Moore’s Law—at least for its top customers. He said there is work under way well beyond 16nm and that new transistor types such as FinFETS are being developed to work at those geometries. But he also acknowledged the growth of multichip stacks connected through an interposer.

Synopsys has been a bit more bullish publicly about 2.5D and 3D than Mentor, although not nearly as vocal as Cadence. But it has been much quieter about some of its work in adjacent markets. This week de Geus peeled back the covers on a cloud-based approach for the company’s tools, which he said can be billed by the hour or even portions of an hour for intensive debugging. That should quell some of the concerns for buying tools at advanced nodes because the tools themselves were underutilized much of the year.

Cloud-based approaches are interesting because capacity can be turned on and off. Synopsys has a license from Amazon, which is one of the more recent pioneers of this strategy. The cloud approach basically is a sophisticated repackaging of the old mainframe time-sharing. But time-sharing involved limited resources and rather rigid scheduling, whereas the modern cloud approach is much more flexible because the cost of compute resources has declined in accordance to Moore’s Law. The big cost now is housing the servers and providing the power to run them and cool them, which is why they have to be fully utilized to be cost-effective. Most companies cannot utilize them fully, which makes the cloud model increasingly attractive.

“We can sell simulation by the hour or even lower,” said de Geus at the Synopsys User Group meeting this week.

One of the big problems with acceptance of cloud-based strategies so far has been that sensitive company data has to be moved outside of the company for testing. Synopsys insists that will no longer be a problem. “The information is very secure,” de Geus said. “Cloud providers are providing military security, which the company’s can’t even do themselves. Companies have not had the right legal framework to deal with this in the past. But that’s changing at a super rapid speed.”

Synopsys also is moving into a number of new adjacent markets such as optical. De Geus said the keys for successful adjacent markets are that they share the same technology or the same channel or the same customers. “If you don’t have a reasonable sense for these adjacencies then you increase your risk.” He joked that’s why Synopsys will never buy a shoe company.

System-Level Design sat down to discuss where the value has shifted in the supply chain with Tom Quan, director at TSMC; Kalar Rajendiran, senior director of marketing at eSilicon; John Koeter, vice president of marketing in Synopsys’ solutions group, and Phil Yastrow, product marketing manager at Avago. What follows are excerpts of that conversation.

SLD: Do you get more value as a customer than before?
Rajendiran: The rule of thumb used to be that you got 15x your investment that was good. If you invested $30 million and you were going after a $450 million market that was good enough. The problem is that it’s no longer $30 million to do a 40nm chip, it’s more like $80 million. And on the other side the markets are no longer generalized. It’s no longer a $450 million market. It’s probably a $200 million market. So in the past you might have been satisfied with 30% market share. Now you need 80% market share. Moore’s Law is great, but the reality has changed the problem from a technology issue to a business issue. The ROI has to be higher. You can’t change the end market.

SLD: What differentiates one chip from another in the future? Is it software or hardware?
Rajendiran: It’s both. If you ask a software engineer and a hardware engineer they’ll have their own take on which one is more complicated, which is harder to test and which is harder to break. But the real smart companies figure out a way to not just build a chip, but also the firmware and the software stack. If software is completely new, there’s a higher probability it will have bugs in it.
Koeter: At 40nm, if you look at the total cost of a chip, the cost of the software will just exceed the cost of the hardware.

SLD: Is that the whole stack?
Koeter: It’s what a semiconductor company would develop. It used to be low-level drivers. Now it’s highly integrated, sophisticated software. But 40nm is the crossover point. So if you look at semiconductor companies, increasingly they’re creating value through software engineers and also their architects. They absolutely want to move up. Unfortunately, every semiconductor company I talk with says that while they put 50% of their costs into developing software, they don’t get any return on that. They don’t get to charge for the software.

SLD: Does that mean Synopsys going to buy an RTOS company?
Koeter: We have a very strong push in this area. Recently we announced an M-language synthesis tool (Synphony). We’ve also been in virtual platforms for three or four years. Systems historically has been a very fractured space, but that’s getting to be a strong opportunity for EDA companies.

SLD: Is the value in the pieces or the integration?
Yastrow: Both. You have to have good IP and you have to have a way to integrate it. You have to have a way to make it work in a customer application. This comes back to channel modeling and how the package fits in. But it’s interesting when we start talking about software vs. hardware. It’s easy to argue that everything is software. People are writing RTL, getting the code to work, making sure they’ve covered all the corner cases and verifying it all. We’re seeing with Moore’s Law that verification is becoming a huge, huge chunk of the work.
Koeter: It’s 70% for the hardware, and then it depends on how you validate the software.
Yastrow: So not only do you need the great IP—memory, logic and I/Os—but you need someone to take that and integrate it first in the form of RTL, and then for the physical designers to make sure it meets timing and it meets power budgets.

SLD: At 32nm and 28nm we’re starting to see restrictive design rules. How does that affect all of this?
Quan: That’s for better yield in the long run.

SLD: But TSMC also is rating IP, right?
Quan: At 40nm we started asking customers and IP providers to run full DFM checks on IP blocks or the full design. It used to be recommended but not mandatory. One of the reasons for this is we’ve seen a lot of layout patterns that might not be reproduced perfectly in silicon. That will affect yield. At 28nm it gets even more difficult in terms of lithography, CMP and DFM. If we give the designer less freedom then it’s easier to validate and check and have better yield. You used to be able to put a lot of bends and jogs into a polygon. Now you try to have more regular structures with no bandwidth jogs. That will facilitate double patterning at future nodes, too.
Rajendiran: Customers don’t like restrictions of any kind. People are talking about orthogonal routing, which gives more flexibility. And companies are developing libraries so that when lithography progresses everything works fine at future geometries. If that can be achieved, every designer will be happy.
Quan: We build our own libraries and we collaborate with IP providers on theirs. Once you get the signal out to the pin and you do place and route, you also know which direction it should go. But it does require a joint effort from the IP provider, the company building the library, and the tool provider to make sure the whole design flow can use these new cells.
Koeter: It certainly makes life harder for an IP vendor. Now we have to worry about multiple layouts of the same IP block. You’re going to see more consolidation in the physical IP space.
Yastrow: We will find a way to deal with it. Competitively, everyone is dealt the same cards. But that’s not the only challenge. Voltage levels are also a problem. You’re trying to comply with standards back to the system level and getting the customer channel to work. You get a performance hit from a higher voltage level, and then the standards run at 1 volt instead of 0.85.
Koeter: USB has to have backward compatibility to 5 volts. Try doing 5-volt tolerance in a 1.8 volt I/O device.

SLD: Does a 3D stacked-die approach change where the value is—providing it works?
Quan: It’s a way to put more stuff in the same area. People have been going down the path of shrinking the die and getting more performance. But there’s always some technology that cannot scale down that easily, like analog and RF. In memory if you have 1 megabit and you want 4 megabits you build them horizontally or you stack them. That’s already been done. From an SoC perspective, where you’re mixing different blocks—memory, analog, RF, digital baseband—it’s a different approach to how you build them. But there will certainly be challenges. Through-silicon vias present more challenges in terms of validating the timing through these vias. And when you stack up things, the thermal profile will be different.
Yastrow: There are two things we know for sure. One thing is customers need more memory. The other thing we known is it’s becoming more difficult to combine an eDRAM process with a logic process and to be able to have them both optimized. Now you end up with tradeoffs. You optimize for the embedded memory or the logic. That’s why 3D where you have a memory chip and an ASIC that are tightly coupled is very real.
Koeter: One of our concerns as an IP vendor is whether 3D ICs will change the fundamental way chips are partitioned. Will all the analog be put in a 130nm or 180nm and the digital be put in a 32nm or 22nm chip. We’re looking at it all the time and talk to customers about it, but right now there’s no indication that’s a significant trend. People continue to integrate analog and digital with big ‘D’ little ‘a’ chips. What they’re doing in 3D is stacking memory on top of those chips.
Yastrow: Besides stacking we’re also seeing new standards developing beyond DDR3. You will still have a discrete chip. But I don’t think you’ll see as much embedded memory on chips. Maybe there will be some SRAM and DRAM, but it’s getting harder and harder to make those two match. So maybe you’ll have two side by side, instead of on top of each other, with an extremely high-speed link between them. That’s why some of these standards that are being developed, like GDDR5 (graphics double data rate, version 5).
Quan: There has been talk about a silicon interposer where instead of stacking them you connect them through a silicon substrate.
Rajendiran: That’s already happening. 3D is taking it to the next level. Will it happen? I think it will. The question is how soon. I don’t think it will happen in the next two or three years because it is easier said than done. It’s a bigger floor plan issue.

SLD: Does the highest value go to people solving the hardest problem, such as power modeling?
Yastrow: It’s a table stake. You have to reduce the power. You won’t necessarily get more money but you won’t lose the design.
Koeter: I absolutely agree. At least you won’t lose money.
Quan: The system-level spec is only getting harder and harder. Even though you leverage the latest process, so you can reduce power and leakage, you still have to have a lot of design techniques. If you have better power consumption, you have more chance of winning the design.

By Ed Sperling

For the better part of two decades there has been a steady stream of predictions about the abrupt end of Moore’s Law, but it now appears the formula for doubling the number of transistors on a die every couple years will simply dissipate rather than fall off a cliff.

While companies such as Intel and IBM continue to develop road maps that extend their road maps all the way to 11nm and 7nm, respectively—at least carrying development through the end of the next decade—the reality is that SoCs will likely contain components built using multiple process nodes. There will undoubtedly continue to be development at the most advanced nodes, but there also will be some components that reach back to 130nm, and some all the way to 180nm.

“At some point Moore’s Law runs out of steam and there will be a crossover to different approaches,” said Charlie Janac, CEO of Arteris. “You can make 11nm steppers and do physical vapor deposition, but they’re going to be very pricey.”

Developers and chipmakers say economics already make stacked die viable. Now it’s just a matter of putting all the pieces in place to make it technologically possible.

Texas Instruments, for one, is looking at a number of different integration models including vertical integration using through-silicon vias (TSVs), said Robert Tolbert, TI’s OMAP platform marketing manager.

“When you have a chip that includes wireless, LAN connectivity, Bluetooth and GPS (global positioning systems), all of those technologies have to be integrated with each other,” Tolbert said. “Through-silicon vias are one approach we are looking at. There also has to be more integration at the package level.”

The stacked die approach
TI isn’t the only company looking at stacked die as a potential solution. All the major chip developers are. In fact, the standards group Si2 currently is working to develop standards for 3D stacking, which should speed its adoption once those standards are ready.

“We’re seeing a lot of attention being paid to 3D lately,” said Bernard Murphy, chief technology officer at Atrenta. “It’s getting a lot of air time with companies like ST and Qualcomm. Folks are trying to figure out how to combine more functionality into a chip. It’s a difference of using known pieces or trying to develop an overall optimized problem. A stacked die allows you to partition on the fly for a known device because you are not building those functions as part of a die.”

This is different from the system-in-package approach taken by memory makers, which have been churning out a rudimentary stacked die for several years in the form of flash or DRAM. That’s more of a system-in-package approach to put more memory into a single package.

The real work is under way inside R&D department at large companies and inside universities to develop chips that stack processing, logic and memory in various vertical layers, thereby reducing the amount of distance between the pieces and greatly simplifying timing and verification—currently the two biggest problems in developing SoCs. Initial versions most likely will contain two layers, but more layers will be added over time.

“The technology is not ready, and neither are the standards and the way all this technology gets used,” said Javier Delacruz, director of eSilicon’s packaging group. “But there is definitely a need for this. As we move down technology nodes and you can fit more on a chip, the cost per unit area is increasing. The best way to address that is to take the non-critical pieces off the chip. It’s a no-brainer. So you take out the memory and add an interface.”

Figure 1: 3D structure with through silicon vias. Source: MicroMagic

That also eases some of the power modeling issues for chips, he said. “Right now, everything is very high power because of the power supplies needed for all the parts of a chip and it’s thermally intensive. But with TSVs, you don’t need to drive a DDR at 1.8 volts.”

What also makes this approach attractive is the ability to mix and match lithographic geometries. A core for one function can be manufactured at a different process node than a core for a different function or a block of memory. In addition, the distances needed to reach various components can be shortened by stacking them rather than routing across a chip, where it can be affected by other traffic, Delacruz said.

What’s here, what’s missing
While this is considered a likely solution for building chips, it’s still largely a research project.

“3D TSV adoption is very application-driven,” said Rajiv Maheshwary, senior director for customer marketing at Synopsys. “In 2010 you will see MEMS, CMOS image sensors and homogenous memories in production. Heterogeneous system integration (logic + memory, logic + RF, logic + logic) will take some time—probably somewhere between 2011 and 2013—for several reasons. First, the supply chain is not ready. That includes the foundries, outsourced assembly and test and EDA tools. Second, the cost of building fine-grain TSVs in the 5 to 10 micron range needs to come down before design teams can move to 3D. And third, business issues exist such as who is best suited to make 3D devices and IP-related issues.”

Thermal issues also are a problem. Getting the heat out of a chip is hard enough in a single layer. In multiple layers, the heat generated through leakage can impact signal integrity or, in the worst case, destroy a chip. Maheshwary said that over time he expects to see three types of TSVs because of this—signal, power and thermal—each with a different pitch.

In addition, there need to be standards for design rules and via patterns, which need to be developed by the memory makers. Also needed are interfaces to improve communications across the chip. The long-term outlook includes separate clocks, separate power and logic to manage communications between the various components, said Geert Rosseel, vice president of technology at Arteris.

“The question from our standpoint is what happens in the middle,” he said. “You want a unified architecture but you also need to turn off certain parts of the chip. You need some way to manage all of that because on chip you may have 32-bit, 64-bit and 128-bit signals. The only way we know of doing that is by packetizing the communications over a unidirectional link with a network on chip structure.”

And finally, the existing tools need to be evolved to be able to do place and route and verification on stacked die. EDA companies say tools will have to be enhanced to focus on TSV modeling, which is largely thermo-mechanical analysis, design for test, physical design, and signoff, which includes parasitic extraction, timing/IR drop and thermal analysis.

It was a good week for globalization, but a bad week for the global economy.

ARM made a “strategic” investment in eSOL, a Japanese embedded software vendor. The real way to read this announcement is that ARM has bought its way into the Japanese car market, which is about the only way you can actually get into that market if you’re an outsider. Despite its prowess around the globe in many markets, Japan’s domestic market remains impossible for non-Japanese companies to crack. But the downturn is hurting Japanese companies, too. Remember when Japanese firms were buying up U.S. real estate in the 1980s?

The economy may be down, but that isn’t stopping Moore’s Law. Mentor Graphics issued an announcement that STMicro is using its Eldo simulator to characterize 32nm cell libraries. Seems like the folks in Europe are staying busy to keep from freezing (or at least to justify their jobs.) Get ready for more power islands, really complex verification—as if it wasn’t complex enough before—and lots of complaints about tools not doing enough because there’s now lots more to do. 

That’s only part of the shift, though. While companies like ST, TI and Intel push to the next process node, others are jumping a half node. TSMC is looking at half-node increments to stay ahead of the pack, which may explain why NEC has partnered with Virage Logic at 40nm.

Speaking of TSMC, did anyone notice that Intel is pushing its Atom chip into the commercial foundry world? The two companies inked a deal to collaborate on IP, platform and SoC solutions involving Atom. There are two ways to read this. One is that, in light of Intel’s $7 billion investment to upgrade its fabs, Intel doesn’t see Atom as a core part of its chip lineup. The other way is that Intel believes it can further reduce costs on its core platform by outsourcing some of the manufacturing. Our guess is there’s a little bit of both involved, meaning Intel is hedging its bets on whether Atom will really pay off while simultaneously giving it a chance to compete with ARM.

The competitive stakes for Intel are growing from a different side, as well. Intel has always been proud of its ability to maintain its own fabs. The spinoff of AMD’s fab business and a subsequent investment into that business by Abu Dhabi-based Advanced Technology Investment Co.—read huge oil company profits looking for a new market opportunity—could make even Intel question its go-it-alone strategy. AMD’s ploy is to open its fab to outsiders while reaping the same unbridled flow of information back and forth between fab and design team—while utilizing capacity from outside companies the way IBM has done with its fab in East Fishkill, N.Y.

And if that doesn’t make chip manufacturing interesting enough, Shanghai-based SMIC received approval from the U.S. government to export its 32nm technology to the United States. That SMIC has gone from 65nm to 32nm and is now talking about success at 45nm is rather surprising, considering the bulk of its work has been at 180nm. That the U.S. government isn’t putting up any roadblocks is less surprising—at least when you think about all those U.S. bonds being held by the Chinese government. The last thing the U.S. can afford right now is a trade war with China, and SMIC is one of China’s most important companies.

–Ed Sperling

By Ed Sperling

Feb. 4, 2009— Santa Clara, Calif. — Moore’s Law is still alive, but just how well it is depends on your perspective.

Paolo Gargini, Intel’s director of technology strategy, said the good news is that Intel can see its way to remaining on the Moore’s Law road map for at least the next 10 years. The bad news is that it’s going to cost a lot more money to do that—about $9 billion for fabs, $1 billion for technology and another $2 billion for products. And that’s at every new process node.

Speaking at DesignCon, Gargini said Intel is counting on 1 billion users of mobile Internet technology, 100 megabits per second of wireless throughput and 1 billion transistors on the go to turn a profit from that enormous investment. But the number of other companies that can afford to keep pace with their own fabs will continue to shrink.

From a technology standpoint, what will drive those changes are continuous shrinkage in the length of gates, the thickness of the insulation and voltage, as well as strained materials, high k dielectrics, metal gates and a host of new materials. In fact, Gargini said that in the future silicon may simply be the base material on which everything else is built. Intel is in the process of developing new deposition methods and experimenting with new materials and approaches. Those new approaches include nMOS, or n-type metal oxide semiconductor, quantum-field effect transistors (QWFETs), as well as nanowires and nanotubes.

Intel is on track to deliver 32nm chips this year, he said.