By Ed Sperling
Mentor’s Mike Jensen looks at the “Rooster Tail,” the giant fan of water released out of three dams in the Pacific Northwest. Check out the photos and you’ll know why they call it the Rooster Tail. This would certainly be a rude awakening in the morning.

Synopsys’ Navraj Nandra examines whether DDR3L will ever make its way into mobile DRAM. The answer, apparently, is no.

Cadence’s Richard Goering peers into the details of 20nm RTL to GDSII methodology. This is like looking over Niagara Falls where manufacturability, timing variability and design size and complexity are churning at the bottom. Better reinforce the barrel.

DeepChip’s John Cooley focuses in on the changes on Mentor’s board of directors, notably that two of Carl Icahn’s three choices for the board have been replaced. This gives new meaning to hot swapping.

NXP engineer Chris Hill, standing in for Mentor’s Robin Bornoff, looks at diminishing returns in thermal design of PCBs and how extra copper layers don’t always help. Given the price of copper these days, no one will argue.

Independent blogger Gaurav Jalan examines the list of challenges for verification teams, providing some insight into why it takes so long to get a chip out the door. Even more disturbing, though, is that confidence in the final product appears to be on the wane.

Synopsys’ Eric Huang had one of those “ah-hah” moments about the limits of family involvement in technical subjects. You do what for a living? Is that legal?

Cadence’s Jason Andrews looks at simulation performance on a Zynq virtual platform using VirtualBox compared with native Linux.

Si2’s Steve Schulz previews what his group is doing at DAC this year, which will include a rundown of all the standards efforts under way at the moment—or at least the ones they’re talking about in public.

Mentor’s Brooks Moses looks at the embedded software in a control cluster of an unmanned aircraft and how difficult it is to program to get maximum performance. In this case, “maximum performance” may mean different things to different people.

By Ed Sperling
NXP has incorporated Tensilica’s ConnX baseband engine DSP core into its software-defined radio platform for satellite and terrestrial digital radio. The chip is being used in everything from digital radio and mobile HDTV to traffic system electronics.

Cadence published what it claims is a definitive book on advanced verification. Given the time it takes to do verification, this certainly can’t hurt.

Picochip churned out a femtocell for the consumer electronics market using Synopsys’ Galaxy flow, which speeded up migration to the 40nm process node.

TSMC reported a 4.5% year-over-year decrease in Q4 revenue, with a net margin of 30.2%. While that’s an interesting bellwether for the semiconductor industry, what’s really interesting in the earnings report are some of the other numbers. In 2012, the company expects capital expenditures to be about $6 billion. In addition, 28nm process technology accounted for just 2% of total wafer revenue; 40nm was 27% and 65nm was 30%.

By Ann Steffora Mutschler
Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT — IEEE 1685, “Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP.

The IP-XACT technical committee has been busy over the past year. Formerly an effort of The SPIRIT Consortium, which merged with Accellera in April, the standard was ratified by the IEEE in June, and has since been downloaded hundreds of times, according to Accellera vice-chair Dennis Brophy, who also serves as director of strategic business development at Mentor Graphics Corp.

“In the first few months of operation we have had several hundred copies downloaded for free,” he noted. “We can predict a very good multi-year trajectory for making the standard easily available to users and consumers, and will help also promote a healthy SoC design environment enabled with IP-XACT.”

IP-XACT, which is an XML schema for meta-data documenting IP and an API that allows tools to access the meta-data, has its roots at STMicroelectronics dating back to 2003. Other vendors involved at a highly visible level include Atrenta, Semifore, NXP Semiconductors, Cadence, Duolog and AMD.

Accellera is well aware what work is not done, and one of the groups inside the standards body is a verification IP technical subcommittee, “whose initial task was to find a way to bring multiple methodologies together so that you could author in one environment and use in another. We proved that through bringing VMM and OVM together so that they could actually work side-by-side and users could author in one and use in the other. We had an open-source kit that users could download in conjunction with their preferred methodology to use and then promote verification IP interoperability,” Brophy explained.

That group took the next step of asking why there isn’t a single standard methodology and have begun work on UVM (universal verification methodology), which intends to bring together the best of all technologies to focus the industry development resources around one methodology – and this is where IP-XACT comes in, he continued.

As a result, the IP-XACT committee relaunched itself over the summer to determine where to go next and are now in the beginning phases of asking themselves that question and inviting other industry participants to join with the committee to start the next phase of development. One of those, interestingly enough, is what can be done to cross-pollinate between the UVM work that is going on, and what impact it will have on IP-XACT. “We know it should have some. IP-XACT has been what I would characterize as a very strong support for design IP that facilitates the design process, but has been a bit weaker in terms of delivery of verification IP,” Brophy observed.

“What Accellera sees is that we really need to have both comprehended in an IP-XACT so we have an ongoing cross-relationship between the technical subcommittees–the IP-XACT group and the VIP group in Accellera. The elements of development that are underway for UVM are, we hope, going to have a positive impact in being able to extend the IP-XACT definition to also comprehend use of verification IP just as the community has done so with design IP. And that is just at its very beginning stages right now,” he said.

While not making any 2011 predictions as to deliverables, Brophy stressed that participants are interested to move forward sooner rather than later, and expects more verification IP companies to join in as they learn about the effort.

For more information, or to download the standard, click here.

It must be time to solve those pesky I/O issues no one got around to fixing last year. Mentor Graphics introduced a hardware-assisted solution for USB 2.0 verification called iSolve, which works with a variety of emulators. Cut the wait time wherever you can.

And Synopsys uncorked a couple new products for USB 3.0. One is a DesignWare protocol analyzer for verifying USB 3.0-based designs. It also introduced USB 3.0 models for TLM 2.0.

Virage Logic set up an R&D center of excellence in the Netherlands. This builds on the rather complex deal Virage inked with NXP last year. Note the analog business unit, which plays heavily into Virage’s ARC acquisition.

GlobalFoundries completed its acquisition of Chartered Semiconductor. It now owns two 300mm fabs and is building a third in New York State. The bottom line: It’s now down to the Common Platform (GlobalFoundries included) vs. TSMC at advanced nodes in the merchant foundry business. Watch out for falling shrapnel.

Speaking of TSMC, the foundry is developing its 28nm process technology with Qualcomm. Most process folks think 28nm is an evolution, but 20nm starts getting really tricky. This may be a good time to start reading up on FinFETs, air gap insulation, self-assembling components and new substrate materials like graphene. They’ll be filed in the science fiction section.

Intel seems to be doing okay these days. Its fourth-quarter income jumped 875%. No, that is not a typo. Revenue was up 28% year over year. And while the computer market pull-through isn’t what it used to be for electronics companies, it certainly can’t hurt.

By Ed Sperling

The new year is off to a gallop, which either means the economy is recovering or everyone took the holidays off and now they’re playing catch-up.

There were a barrage of press releases over the past week. While individually they look like the usual marketing, collectively they tell a different story—and probably the first really positive one since the downturn hit. Business is up, design activity is up, and executives are back to pitching financial success to Wall Street.

Virage Logic signed a partnership deal with eSilicon to become an IP partner in eSilicon’s value chain. Virage also inked a deal to provide its Sonic Focus software on IDT’s codecs for PCs. and another deal to license its ARC processor cores to Phison, which makes USB drives and memory controllers.

Canon is migrating its India Design Centre to OVM and is using Mentor’s Questa verification platform. Business is healthy in Asia.

Top execs are back on the road again doing more than just sales calls, too. CEOs from Synopsys (Aart de Geus) and Actel (John East) will be presenting at the Needham conference in New York next week.

And electronics companies began talking up the products that are running their latest technology at CES. ARM is showcasing its Cortex-A9 processor in an NXP set-top box  while MIPS is showcasing its cores in set-top boxes running Android.

Even jobs are beginning to return to the market, according to job boards. Some of this work is still on a consulting basis, but it’s at least a first step toward a broader recovery. Welcome to 2010.

By Geoffrey James

Intellectual property was once seen as the new growth market for EDA. Dozens of firms – large and small – jumped on the IP bandwagon, attracted to the “build once, sell many times” business model.

“As late as 2004, the industry was still thinking that as much as 90% of SoCs would be reused IP,” said EDA consultant Gary Smith.

The IP segment, however, hasn’t proven to be a profitability panacea, especially for smaller firms. There are the big players—Synopsys and Mentor in the EDA world, ARM and MIPS on the processor side, and Virage Logic in a variety of markets, which has broadened recently with the acquisition of ARC and NXP’s IP portfolio. There also are players like Rambus and Denali that have staked out strong market presence. For most other companies, though, IP has been more troubling than it has been worth, as evidenced by the continued consolidation in this sector.

For one thing, IP never achieved the promised level of penetration. Reusable blocks comprise only a little more than two-thirds of today’s typical SoC, according to Smith. Perhaps as a result, since 2007, IP revenue has stalled at or around 20% of total EDA market. (See figure 1.)

Source: EDAC

But there have been other problems as well, especially for smaller firms. Far from an easy way to make money, IP has become one of the most harrowing segments of the EDA market, with five major financial and technical challenges:

CHALLENGE #1: New IP always requires customization.
Back when IP first became big business, state-of-the-art circuitry was around 180nm. At those geometries, IP was pretty much plug and play. If a block of RTL did something on one chip, it would do the same thing on another chip. While the overall chip had to use the block correctly, there wasn’t much else that could go wrong. It didn’t matter what foundry made the chip, nor what other kinds of circuits were in the general vicinity of that particular block of IP.

That all changed at around 90nm. Suddenly, a circuit that worked perfectly on one chip would go all catawampus on another, simply because of leakage from surrounding circuitry. Even the same chip manufactured at different foundries might end up with wildly different yields, due to the peculiarities of the individual processes. As a result, IP, if it’s complicated or if it’s targeted for the smallest geometries, stops looking “plug and play” and starts looking like custom design work.

This screws up the “build once, sell many times” business model, says Smith. “Design firms selling state-of-the-art IP often find themselves spending more time tuning the blocks for specific designs than creating new IP to sell,” he says. In order to survive, smaller IP firms must extract revenue from the customization, rather than from the IP license. Unfortunately, this ties up their most precious resource—top engineering talent—thereby limiting their ability to continue to innovate.

CHALLENGE #2: New IP has a short market window.
Once a certain type of IP is well-understood and has been qualified for multiple manufacturing processes, it does begin to approach the plug-and-play status that would make “build once, sell many times” workable. However, once the IP reaches that state, it’s generally no longer unique enough to command a premium price. Instead, there will be multiple plug-and-play approaches to solving that problem. The IP becomes a commodity, making it more difficult to recoup the development expense.

For example, when USB 2.0 first came out, the IP to make it work commanded a premium license fee. However, once USB 2.0 had gone into enough designs, the problems making it work with different processes were largely solved and easily imitated. Because of that, chip designers can choose from a number of different versions of USB 2.0 IP and since none of them are noticeably better than the other, semiconductor firm are likely to pick the cheapest.

That’s probably OK, if you’re selling a knockoff. But if you invested a lot of time and money to come up with the first version, and then qualify it on multiple processes, you have a very limited amount of time to obtain the kind of high license fee that would provide a good return on that development investment, according to Richard Wawrzyniak, ASIC and SoC senior market analyst at Semico.

“The IP world is driven by your ability to differentiate your customer’s product,” he says. “If you can’t provide that differentiation, then your IP has limited value.”

CHALLENGE #3: IP Litigation can get expensive.
With chip designs costing more money every year, it’s not surprising that many semiconductor firms are outsourcing designs to India and China, where engineers are plentiful and cheap. Unfortunately, China (and to a lesser extent India) has an abysmal record of protecting high tech IP. “The entire idea of intellectual property is alien to Chinese culture; China didn’t even have patent laws until 1990,” explains Usha Haley, a business school professor at the University of New Haven and author of Asia’s Tao of Business: the Logic of Chinese Business Strategy (Wiley, 2004).

Unfortunately for their profitability, IP firms can find themselves involved in legal hassles related to the unauthorized use of their IP. That’s just a cost of doing business for large IP firms. Smaller IP firms, however, simply can’t afford that expense, according to Charlie Cheng, CEO of Kilopass, a company that holds IP patents for non-volatile memory. “Our only defense is to keep innovating so that people will keep doing business with us rather than stealing our IP,” he explains.

CHALLENGE #4: Semiconductor firms want to manage their risks.
Many semiconductor firms look a bit askance at IP because it makes them dependent upon the IP supplier. If something goes wrong with the IP during, say, verification or manufacturing, the IP supplier might not be willing (or able) to drop everything and run to fix the problem. And if the semiconductor firm hopes to move a chip design to a newer node, the IP supplier may need to get re-involved and possibly retrained on the design rules for a new process.

Under the circumstances, many semiconductor firms prefer to develop as much as possible of their circuitry in-house, so that they have control over development priorities if a problem occurs. Many firms only turn to IP when they lack the expertise to develop an in-house product. CPU IP is a case in point, according to Art Swift, vice president of marketing at MIPS. “We’ve been working on the RISC computing concept for decades, which has created a vast experience base and intellectual process that would be difficult, if not impossible to reproduce elsewhere,” he explains.

In other words, smaller IP suppliers entail risk that some semiconductor firms aren’t willing to suffer, according to George Zimmerman, chief technical officer at Solarflare, a company that makes 10 Gigabit Ethernet chips and controllers. “Going with a larger firm offers more risk mitigation,” he says. “We’ll only work with a smaller IP firm when what we need is highly specialized and can offer a substantial performance advantage.”

CHALLENGE #5: IP design favors economies of scale.
In contrast to their smaller brethren, the larger IP vendors have more resources to apply to making sure the IP behaves as expected. Synopsys is a case in point. “We have about 700 people working in our IP group who focus on adapting IP to run on different process nodes and for different customers,” says John Koeter, the company’s vice president of marketing for the solutions group. This massive application of manpower allows Synopsys to achieve the “build once, sell many times” business model.

Smaller firms, however, lack the economies of scale to imitate Synopsys’s success. Instead, they’re forced to marshal whatever resources they can to help a handful of customers, most of whom will require a significant amount of custom work. And while that still is revenue, it’s not as easy as getting a check every month for your IP licenses.

This is not to say that smaller firms can’t make money in chip IP, according to Smith. “The ones doing OK are making analog content because analog is difficult and there aren’t analog engineers available to be hired,” he says. But the idea that IP could be a short cut to big money for small firms remains a dream unfulfilled. “The reality is that it’s just not as easy as it looks to make money in this business,” Koeter says.

The barrier to entry also has escalated well beyond what it was at 130nm or even 90nm. The companies looking for IP typically are at the leading edge of design, which means the IP has to be qualified and tested for that process node.

“Prior to 45nm, there was no IP ready before silicon, said Brani Buric, vice president of marketing and strategic foundry relationships at Virage Logic. “Now you have to design complicated technology for SoCs, test it and verify it. So the skill level required on a scale of 1 to 10 went from 3 to 20. It’s tough to be a small player in this market.”

By Ed Sperling
Virage Logic cut an interesting deal with NXP, the former Philips Semiconductor. Assuming the deal goes through, NXP gets to use Virage’s IP for 44 months, pays $60 million to Virage, and gives Virage a large chunk of its standard analog IP—not to mention 160 of its employees. So is this a case of crossing the pond or everyone swimming in the same pond?

Mentor’s deal to buy Valor was much simpler. Mentor will simply pay $82 million for Valor, which makes PCB productivity improvement software. Considering the push for holistic design that extends well beyond the chip, this is an interesting acquisition.

Synopsys took the covers off its high-level synthesis tool Synphony. This had been rumored for some time, but no one outside the company knew for sure what was happening—or at least they weren’t talking. It’s an interesting extension of Synopsys’ Synplicity acquisition, though. It allows engineers to migrate algorithms written in floating point to fixed point, or from The Mathworks‘ Matlab to RTL. This has been a big hole in Synopsys’ product lineup. Consider it filled.

TSMC issued its September sales report, confirming what many already knew: much of the buildup of the past few months was largely the result of an inventory shortage. Net sales dropped 3% from August, and 0.8% from September 2008.For the first 9 months, sales dropped 24.6% compared to the same period in 2008. Some companies are coming out of the recession nicely—notably Google, Apple and Intel—but it certainly isn’t going to be a straight line back for everyone.

ARM’s Techcon (formerly the ARM Developer Conference) is next week, and a large portion of the industry is lining up on ARM’s side to make presentations. This is newsworthy largely because it’s in context of one of the biggest wars to be fought in years in the chip industry, this one between ARM and Intel. ARM’s strength is its low-power cores, while Intel’s is performance. Both are struggling to reach parity (or superiority) in each other’s stronghold—ARM is working on more cores and Intel is working on low-power versions of Atom—and it should prove to be an interesting fight.

By Ed Sperling

Acquisitions are beginning to pick up in the system-level design world, signaling that even if the market isn’t fully recovered top executives believe it has at least bottomed and started its journey back from the depths of despair.

Virage Logic has stated its intention to acquire some of NXP’s intellectual property—and pick up 160 of its employees. Because NXP—formerly Philips Semiconductor—is a Dutch company, it requires the approval of a workers’council.

“These are the pieces we don’t have in our portfolio right now, like analog IP,  high-speed I/O and SoC infrastructure IP,” said Alex Shubat, Virage’s president and CEO. “We will be able to bundle this and integrate it with the rest of our IP to create re-usable components.”

Analog IP as a whole has been a tough market for companies for companies to crack because much of the IP in this market isn’t re-usable. NXP’s approach has been to develop more standardized analog IP, such as video decoding for digital TVs and set-top boxes, but it lacks some of the other pieces required to make a complete solution. Coupled with Virage’s previous acquisition of ARC, this potentially can make Virage a powerhouse in a number of high-volume consumer electronics areas.

As part of the complex deal, NXP also gets access to Virage’s IP portfolio for 44 months and will receive 2.5 million shares of Virage stock, priced today at just under $6 a share. It also agrees to pay Virage $60 million over four years.

The NXP deal was the second significant deal in the past few days. Mentor Graphics also signed a deal to acquire Valor Computerized Systems, an Israel-based maker of PCB productivity software, for $82 million. The deal is a recognition by Mentor that system-level design now reaches well beyond the chip and out onto the entire printed circuit board.

Mentor is not alone in this recognition. Companies like IBM have been talking about holistic design that spans well beyond the semiconductor for several years.

By Cheryl Ajluni

In the world of system design, few technologies cut across as many lines as nanotechnology. Whether for use in better, cheaper sunglasses, sunscreen, next-generation body armor or regenerative medicine, its application seems limitless. It is so far reaching in fact that by 2015 some analysts predict the global market for nanotechnology will top $1 trillion.

As Viviane Reding, the European Union’s Commissioner for Information Society and Media, so aptly put it in a 2008 interview, “Today, it is the smallest technologies that are taking the largest leaps forward, and our industries must do the same. The possibilities offered by nanotechnology are only limited by our imagination. They underpin all aspects of everyday devices and so concern everyone in Europe.” These comments still ring true today in Europe and elsewhere around the world, particularly when it comes to nanoelectronics (see Understanding Nanoelectronics below). In this arena, advances continue to come in rapid succession.

At Lawrence Livermore National Laboratory, for example, researchers have devised a versatile hybrid platform that uses lipid-coated nanowires to build prototype bio-nanoelectronic devices. The idea behind this development is simple: to boost the operating efficiency of laptops and other electronic devices by combining manmade devices (nanoelectric transistors) with biological machines.

Research in this area has been ongoing for some time with no real progress. It wasn’t until small nanoparticles the size of biological molecules were created that researchers were finally able to integrate the systems at a more localized level. The bio-nanoelectronic platform that the LLNL team created uses lipid membranes because they can house an unlimited number of protein machines that perform a large number of critical recognition, transport and signal transduction functions in the cell (Figure 1). The membranes were incorporated into silicon nanowire transistors using a shielded-wire approach. In other words, the nanowire was covered with a continuous lipid bilayer shell that formed a barrier between the nanowire surface and solution species. This allowed the team to use membrane pores as the only pathway for the ions to reach the nanowire. The nanowire device monitors specific transport and controls the membrane protein. By changing the gate voltage of the device, the membrane pore could be opened and closed electronically.

Figure 1. This image by Scott Dougerty, LLNL, is a representation of a bioanoelectronic device incorporating an alamethicin biological pore. In the core of the device is a silicon nanowire (grey) covered with a lipid bilayer (blue). The bilayer incorporates bundles of alamethicin molecules (purple) that form pore channels in the membrane. Transport of protons though these pore channels changes the current through the nanowire.

Researchers at Berkeley Lab have been actively investigating a phenomenon known as phase inhomogeneity and how it can be engineered on the sub-micron scale to achieve desired properties like colossal magnetoresistance and high-temperature superconductivity. For the first time, they have been able to show that these highly coveted properties can be generated by applying external stimuli, in this case strain, to a correlated electron material like vanadium oxide (Figure 2). Colossal magnetoresistance occurs when the presence of a magnetic field increases electrical resistance by orders of magnitude. High-temperature superconductivity occurs when the materials lose all electrical resistance at temperatures much higher than conventional superconductors.

According to Junqiao Wu, a physicist with Berkeley Lab’s Materials Sciences division, “By continuously tuning strain over a wide range in single-crystal vanadium oxide micro- and nano-scale wires, we were able to engineer phase inhomogeneity along the wires. Our results shed light on the origin of phase inhomogeneity in correlated electron materials in general, and open opportunities for designing and controlling phase inhomogeneity of correlated electron materials for future devices.”

Figure 2. These optical images of a multiple-domain vanadium oxide microwire taken at various temperatures show pure insulating (top) and pure metallic (bottom) phases, and co-existing metallic/insulating phases (middle) as a result of strain engineering. Images courtesy of Junqiao Wu.

Nanoelectronics around the world

The discoveries made by researchers at Lawrence Livermore Labs and Berkeley Labs represent just the tip of the iceberg in terms of what’s going on, at a global level, in nanoelectronics today. Despite a tough economic climate, countries and companies around the world are still investing time and money into this potentially lucrative technology.

One such effort comes from CEA/Leti—the Electronics and Information Technology Laboratory of the CEA, based in Grenoble—and IBM. Earlier this year, the two announced a five-year collaboration that will focus on advanced materials, devices and processes for the development of CMOS process technology to be used in the production of microprocessors and integrated circuits at 22 nm and beyond. This collaboration will focus on three key areas: advanced lithography for fast prototyping and 22-nm chip technology, CMOS technologies and low-power devices for 22-nm chip technology and beyond, and technology enablement (e.g., nanoscale characterization techniques for research and monitoring manufacturing protocols).

Additionally, a European initiative aimed at improving engineering efficiency at the nanoscale just recently won funding under the European Union’s Seventh Framework Program. The initiative is being led by a consortium of microelectronics companies like Philips Applied Technologies, Fraunhofer IZM, Infineon, and NXP, as well as research institutions like the Georgia Institute of Technology Lorraine. The project, NanoInterface, hopes to realize a number of scientific, technological and societal advances, including the development of a multiscale design approach for microelectronic materials, a contribution towards the industry’s ‘zero defect’ objectives and the implementation of environmentally-friendly materials. As part of the project, partners will develop a software tool that incorporates chemical, physical and mechanical information from the atomic level directly into macroscopic models. It will be used to enable highly-reliable metal oxide-polymer systems for System in Package (SiP) products and complex micro- and nanoelectronic systems.

Even Saudi Arabia has gotten into the act by collaborating with Synopsys to form a Center of Excellence for Nanoelectronic Design at the King Abdulaziz City of Science and Technology (KACST)—both the Saudi Arabian national science agency and its national laboratories. The goal of the collaboration is to enable the development of a nanoelectronics-based ecosystem in Saudi Arabia. Toward that goal, KACST and Synopsys are working to create a nanotechnology and nanoelectronics infrastructure, state-of-the-art computing environment, electronic design environment, and nanoelectronics design flow. A hub will also be created to provide advanced electronic design automation software and curriculum to Saudi Arabia’s universities and research centers.

Conclusion

Nanotechnology, and in particular, nanoelectronics, is a topic of great importance and urgency these days. The current CMOS transistor architecture is expected to reach its limit some time around 2020. When that day comes, nanoelectronic technologies must be ready for prime time. The extensive research and development projects currently under way around the world will play a critical role in ensuring that goal is realized. While any discoveries may not translate into commercially viable devices just yet, they do serve to advance the study of nanoelectronics and the possible features it may enable in next-generation electronic devices. Whatever today’s researchers develop will undoubtedly end up benefitting the chip industry in ways that can not yet even be imagined.

All of the major EDA vendors and standards groups are pitching modeling as the next level of abstraction for advanced process nodes, but is it working as planned for the chipmakers? System-Level Design caught up with Frans Theeuwen, Department Manager for System Design at NXP Semiconductors Corp. to discuss system-level design and power modeling.

By Ann Steffora Mutschler

SLD: How long has NXP designed at the system-level for production chips?

Frans Theeuwen: It depends on what you call ‘system-level design.’ We have been doing hardware/software co-verification activities for quite some time, which goes back about eight years. Many things we are doing in system-level design are creating virtual prototypes and software development for virtual prototypes. We first did that for production designs about three or four years ago. There was one chip for identification, used in banking applications, and now we are using it more heavily in the area of television chips (consumer electronics). What we are doing now for consumer applications is transaction-level modeling and using that mostly for software development.

SLD: What works and what doesn’t in this area?

Theeuwen: The largest problem for introduction is you need to create all the models. That requires quite an investment if you want to reuse that within the company. In 2007 and 2008, we did quite an investment in creating lots of models for our standard SoCs, so for all the IPs that are there. That’s one thing that is important. The other thing is that most people want to use these virtual prototypes for accurate simulations – for really cycle accurate things. That is what you should not do because then the models are much too complicated and you are too late. If you do transaction-level modeling, you can still do software development, so convincing people they should use one use case for software development and create the models for that, and then do software development for that.

SLD: How long have you been doing power modeling on the transaction level, and are you using tools that you created or outside tools?

Theeuwen: For power modeling on the transaction level, I think we started four years ago. Before we started on the transaction level we did it for power estimation on the gate level. Then, later on, we extended this capability of power modeling at the gate level to go up in abstraction to the transaction level, and there we created our own tools.

SLD: How is the learning curve for the engineers in terms of power modeling?

Theeuwen: Our power models are part of the SystemC TLM models. First, you have to create TLM SystemC models, and then you can put the power models to that. First, you must have all the TLM models available and then you can think about power modeling. We’ve only been working on full-fledged TLM models for a few years, so now we can add the power models to that and the extra work is not that much. Once you have the TLM model, then adding the power view is really not so much work and we rely there on the gate level simulation. As most of the designs are reused – about 90% to 95% of large SoCs is reused – you can have quite accurate power models because you have the RTL so you can simulate. If you have that on the TLM level, you can have quite accurate power modeling on your whole SoC. There are only a few parts for which you do not have implementations and there you need high-level power estimates.

SLD: What are some other issues that need to be addressed at the system level?

Theeuwen: The largest problem with TLM modeling is that interoperability between models is still very difficult. TLM 2.0 is a step in a good direction, so it gives a bit of framework, but if you are modeling in TLM 2.0 there is no guarantee that everything works together.

SLD: What is missing from TLM 2.0?

Theeuwen: One part of being interoperable is being able to connect models to each other with the same buses and pins, and things like that. But also, in a complete system, how scheduling works or how different parts run on a multiprocessor design and how does that change, and how it interfaces to memory. All of those things are still not standardized.