By Ed Sperling
Synopsys continued its buying spree, acquiring verification IP developer ExpertIO. Synopsys will absorb the entire ExpertIO team, including CEO Craig Stoops, into its verification group. Terms of the deal were not disclosed. What’s particularly interesting is that ExpertIO’s partners include all of the Big Three EDA vendors.

Synopsys also is collaborating with Sigrity to accelerate signal integrity analysis, and it won a deal with Yamaha, which is standardizing on its Processor Designer tool for custom DSPs.

Mentor Graphics won a deal with Altera, which will use its Voloce emulator to verify its next-generation FPGAs.  Mentor also won a deal with Fujitsu Semiconductor, which is expanding its use of Mentor’s Calibre platform for physical verification and DFM. e

Open-Silicon rolled out a 28nm version of its Interlaken IP core for chip-to-chip packet transfers for networking products.

Arteris reported more than 100% growth in NoC technology licensees in 2011. The number is now 39, up from 18 at the beginning of last year.

By Ed Sperling
Estimates of how much time it takes to verify a complex SoC are still hovering around 70% of the total non-recurring engineering costs, but with more unknowns and more things to verify it’s becoming harder to keep that number from growing.

Verification has always been described as an unbounded problem. You can always verify more, and just knowing when to call it quits is something of an art. Moreover, with software now thrown into the mix, engineering teams have to decide what’s good enough for tapeout and what can be fixed once the chip is already in the market.

Making that decision is becoming tougher, though. The amount that has to be verified is less clear, in part because of the growing amount of outside IP that is now included in designs. Of the 70% or 90% of IP that is used or re-used in a complex SoC, less than 50% is now commercially purchased with the remainder internally developed, often for previous projects. The amount of commercially generated IP is expected to rise over the next few years, though, basically creating a series of black boxes that companies didn’t create internally.

While much of this commercial IP will be sold as pre-verified, what works in one design may not work exactly the same way in another. That’s particularly true with different process technologies. A general-purpose process built for speed may cause IP to behave completely differently than one optimized for low power. And in stacked die, two known good die may no longer work when they are packaged together.

“The new world is a broader supply chain for chips,” said Mike Gianfagna, vice president of marketing at Atrenta. “There is a need for better visibility in the supply chain, including everything from early predictions to yield to the track record of the supplier. There are multiple points of failure. For data management, planning, thermal and mechanical analysis you need fundamental enabling technologies. At the same time there is a re-invention of the industry into smaller, more niche markets.”

Knowing what to verify
Just knowing how much to verify is a challenge. Taher Madrawala, vice president of engineering at Open-Silicon, said this is not a simple decision because file sizes for verification are becoming enormous. That means what gets left out of the verification process may be as strategic as what gets included, because all of this can affect time to market. Verification budgets remain tight, both from a manpower and equipment standpoint.

“On top of that you don’t always have access to all of the functionality,” Madrawala said. “That’s especially true in 3D stacks or system-in-package. You don’t always have access to increased functionality because some things are encapsulated inside the package.”

He noted that from an NRE perspective, the percentage spent on verification has remained constant from 90nm down to 45nm. That has been helped by more standards, including modeling of IP in C or C++, an increased use of emulation, and the ability to run tests on multiprocessing computers. But with compressed schedules and greater complexity, those numbers can change.

There also are differences of opinion about what works, what will continue to work, and what needs to be changed in the future, both from a physical and a functional standpoint. Tools vendors insist that most of the capabilities are already there to do verification, even though they will need to be speeded up through better modeling at a higher level of abstraction with a greater reliance on multiprocessing servers. They also say that verification teams need to learn to use the tools that are out there better.

Chipmakers generally acknowledge the need for better training on the tools, but they say the growth in complexity will create the need for additional testbenches. In particular, there will need to be new tools for partitioning designs and verifying the results once stacked die become more mainstream.

“As complexity grows, integration will be the issue,” said Prasad Subramaniam, vice president of design technology at eSilicon. “You will need specialists for each part of the design. People’s specialties will get narrower. And then you will need people to manage more specialties. The generalists, who will be the architects and higher-level engineers, will define the problem. Once they have made the decision about what to do, then the specialists will take over. But there will also be a lot of feedback. This will be an iterative process. There will be meetings where you need to reconcile differences and make adjustments. There will be a lot of collaboration, and verification will start from the get-go.”

Verification strategies
There are two main approaches to verification. One is to verify the pieces. Another is to verify the system. Both are necessary, but the order in which they need to be done as part of a verification flow can vary greatly for even derivative chips.

Samta Bansal, 3D IC lead and silicon realization digital project manager at Cadence, said that in stacked die an incremental approach will be needed to do verification. “If you analyze it all together it overcomplicates the process,” Bansal said. “For one thing, not all of the pieces will be available at the same time. A more feasible approach will be to verify each chip in a stack as part of a verification flow, then focus on the microbumps, TSVs, LVS and DRC for alignment and ultimately create a single file.”

That’s not so simple, of course. In stacked die there are physical verification issues that can complicate the functional verification, notably stress and power. And there is now software that needs to be considered in the mix, with the trend toward an increasing portion of the stack.

“Functional and physical verification are both important but independent tasks,” said George Zafiropoulos, vice president of solutions marketing at Synopsys. “In both cases, verification is moving up in system complexity. We’ve gone from blocks to lots of blocks to lots of processes and I/O, and there is more stuff coming. Complex interface IP at the periphery of the chip has gone up by an order of magnitude. The design team can’t verify everything, though.”

Zafiropoulos said design teams used to think there was not enough time to do verification at the block level. He said that putting 100 blocks together increases the challenge exponentially.

“A lot of this is bottom up,” he said. “You build sub-circuits up to the chip and then in multiple chips. You can’t afford to have errors inside these blocks. But you also need to change the scope of what has to be done. In the past, one engineer could comprehend everything on a chip. Now we’ve gone from the guy who knows everything about a chip to teams that are in different companies and maybe different countries.”

The result, he said, will be a gradual change in three areas. First, more and more engineers will do verification, rather than just specific verification teams. Second, all engineers will become more software savvy. And third, new kinds of tools will be introduced, including formal approaches.

By Ed Sperling
Fabs and foundries frequently have been the savior of flawed designs, fixing problems such as power and performance, identifying design issues and often developing solutions to those problems.

Over the next couple of process nodes, and in stacked die that will span multiple processes, there will be far fewer saves coming from the back end. Double and triple patterning, stress effects, new materials and the laws of physics are forcing a change in direction. In fact, for the first time design teams will have to make up for a slew of changes and challenges on the manufacturing and packaging side, employing new methodologies, new tools and deeper levels of expertise.

In a keynote speech at the SEMI Industry Strategy Symposium last week, Applied Materials chairman and CEO Mike Splinter sounded the alarm over the changes ahead. “Change is accelerating,” said Splinter. “Compared with the last 15 years, the next five years will have more changes and more inflection points. And it’s not just about complexity. It’s happening at the foundational level of how an IC is made.”

He’s not alone in that assessment. Bernie Meyerson, an IBM fellow, said CMOS is now in “the end game.” While CMOS certainly isn’t going away, there are physical limits for what can be done to extend it. That has spawned extensive research into alternative materials such as silicon on insulator and graphene, new elements for insulation, as well as new structures such as FinFETs and carbon nanotube FETs.

So what does this mean for design at advanced nodes? Lots more work on design for manufacturability, more complexity in achieving the same kinds of boosts in performance and energy efficiency that were taken for granted at older nodes, and much more up-front checking of just about everything.

“From 40nm to 28nm to 20nm, the number of checks for physical verification will grow by leaps and bounds,” said Michael White, director of product marketing for Calibre. “There are almost 1,000 more DRC checks from 40nm to 28nm between early production and volume production. We are also capturing additional context-dependent yield detractors. For example, historically we have had spacing checks. Now we have spacing checks and we need to check all of the other geometries in the neighborhood, including lithography and fill issues. Those are extra constraints.”

Lithography used to be something design teams never had to consider. But the delay in EUV will require double patterning at 22/20nm and potentially even triple patterning of at least some portions of the chip at 14nm. This becomes particularly challenging for design teams, because one of the approaches under serious consideration is something called spacer-assisted double patterning. In simple terms, a polygon design may look nothing like what’s on the mask using SAPD. This is akin to driving a car in reverse using the rearview mirror where nothing that appears in the mirror resembles the road.

Stacking effects
One solution to these issues is stacking of die, whether in 2.5D or 3D configurations. The so-called “More Than Moore” approach bundles technologies together at nodes that make sense for a particular function, rather than trying to fit everything into the most advanced process. So while the logic or memory may be created at 22nm or 14nm, for example, analog may be developed at 130nm.

This all makes sense in theory, but it also adds a new dimension of complexity that ripples back and forth between the design and the manufacturing worlds. It also exposes the entire supply chain into the design process, because problems detected anywhere along the chain can affect multiple other areas—and it’s possible that no single segment can solve them alone.

“Over the next three to five years chips will go vertical,” said Naveed Sherwani, CEO of Open-Silicon. “The question is how we are going to put together 3D ICs and what will go into them. There is a lot that needs to be done in this area.”

Sherwani contends that tools and methodologies should make it easier and quicker to do derivative designs. That’s the goal, and at least part of the solution involves companies learning to use the tools they have more effectively, and to apply some discipline to their methodologies. It’s easy to get blinded by the number of permutations and choices from the growing complexity.

“As process geometries continue to get smaller and the amount of IP used increases, the complexity of the design process becomes a major issue, which puts pressure on the entire development team from a coordination and communication standpoint,” said Simon Butler, CEO of Methodics “Also, with software elements and power constants, which are really just other types of IP, added to the already very complex mix of things, design teams need better ways to manage the entire SoC development process and synchronize all the moving parts. Internal design organizations already struggle with managing remote design teams. Now, with a disaggregated design chain consisting of separate companies, the need for real-time collaboration and managed data exchange is critical.”

That sentiment is echoed across the industry. Frank Schirrmeister, senior director for the Cadence System Development Suite, said that in principal tools allow engineers to model almost everything they need. “This isn’t a tool problem. It’s a discipline problem. But the other side of this is that in 1993 logic synthesis was pretty simple. Twelve years later, the whole process is not longer understandable by any engineer.”

Margin call
One of the most effective ways to deal with unknowns in the past is guard-banding—the process of building extra safeguards into ICs. That worked until about 65nm, but at advanced nodes it can cause performance degradations or drain batteries more quickly, or both.

“The guard band for synthesis is a smaller percentage at 28nm and it’s even smaller at 20nm,” said Jack Browne, senior vice president of sales and marketing at Sonics. “So you’ve got to be able to interoperate with the right guys. We’re all trying to manage a horrible amount of complexity and simplify it. The problem is there is too much that’s new and not enough experience points so that people can make the safe choices. There are significant unknowns on everyone’s road map.”

One potential solution—and one that’s being considered by a number of large chip and IP companies—is to harden everything into pre-qualified, pre-verified subsystems. While this limits the number of permutations, it does take some of the risk out of using those blocks. But too many hardened subsystems also can limit the ability of companies to differentiate their designs. And while that works well at a company like Apple, it does not work so well at a chip company trying to sell technology to Apple’s competitors.

“With subsystems you’ve closed the black box and given up the chance to turn some of the dials,” Browne said. “We’re seeing this with the TI OMAP team, which has accumulated a significant number of libraries and with Broadcom. And Toshiba has created video and RF subsystems.”

Caution ahead
All of these issues have raised questions about what needs to be fixed in the design flow, what needs to be extended, and how this will unfold over time. The reality is that changes may be slow because there is serious uncertainty about exactly what problems will erupt, where and when.

“There’s always a risk of getting too far ahead with the tools,” said Steve Smith, senior director of platform marketing at Synopsys. “We will add capabilities to current tools to make them 3D aware, but the goal is to enable engineers to do what they do best. We’re already dealing with multicorner, multimode design, and 3D will be another dimension. We might have coupling effects and we certainly will have a challenge with temperature. But most of the processes are familiar, and changing things in a working flow is always risky.”

By Ann Steffora Mutschler
Model-driven design is coming into its own, in part because the old way of using models at advanced nodes doesn’t always produce usable chips and in part because of the need for making tradeoffs at the earliest stages of the design process.

The concept of developing models for IC design is hardly a new one, and it is being done today on a number of levels ranging from transactions in TLM 2.0 to power and software. Historically, though, it has been done at a very high, purely functional level, often for algorithmic verification. These models have enabled engineers to verify if a data stream or data object could be manipulated, and once the function was verified the model was disregarded. From there, little executable performance information was recovered.

More recently, engineering teams have begun to recognize those models can used and flowed down into the rest of the design process to help make architectural tradeoffs. A lot of engineering teams are running into problems in that their designs do what they are supposed to do, but they are not successful because they miss the performance, observed Jon McDonald, technical marketing engineer for the design and creation business unit at Mentor Graphics. “Those performance issues could be timing and power-related; often it’s both and it’s a tradeoff between the two.”

More and more, he said, engineering teams want to take the architectural models that they’re getting at the very high level to define what the system is, how they’re going to do manipulations and break that down to the level of an architectural refinement where they decide what should be implemented in software, what should be implemented in hardware, how fast it needs to be and how many processing engines are needed. These are questions around implementation choices that need to be made before implementation because once teams start writing RTL it’s much more difficult to make a change.

Tom De Schutter, senior product marketing manager at Synopsys, noted that years ago everybody was hoping those models would also be synthesizable and that they would be a starting point for the IP components. So rather than just creating a model for a specific use case and then ‘throwing it out,’ there would be an implementation path. “That just doesn’t seem to be a reality. There are high-level synthesis tools, but it’s a very specific type of model, not what you need for these type of use cases.”

One item coming more to the forefront, he explained, is that although the model is not synthesizable into a piece of IP it actually can provide a lot of value as a reference to create the IP and to create the testbench before the IP is available. More and more IP vendors are now doing a model-first approach. They create a SystemC model, they verify the functionality of the model, create the testbench around it, potentially also create software stacks, and so on based on the model. Doing that provides more debug ability. They can then re-use that model to develop and verify the actual IP model.

While there is no automated path, the goal is still to reduce the effort for IP development significantly by doing a model first. Varying results are seen based on whether engineering teams consistently develop the models or whether they just try one model.

“It’s really something that by just doing one model you can’t really prove or disprove that methodology works. ST is probably the best example of a company that’s really adopted this methodology and has a lot of documentation out there. Some IP vendors have done this, as well, and they’ve seen good results. But it’s really something that you completely adopt and go for it, or if you kind of step into it and assume that it won’t work then you can easily prove that it doesn’t. It’s like with all statistics, depending on the mindset and how you ask questions there’s always a way to prove or disprove certain assumptions,” De Schutter added.

Interestingly, what often today is called model-based design refers to these things that have UML models or MathWorks models, which are independent of hardware and software implementation, said Frank Schirrmeister, group director for product marketing of the system development suite at Cadence. “What you have there is the trend continuing and getting stronger that on the pure software side linking into to the software development piece you have these things like UML and MDA (model-driven architecture) and so forth, which you find in the OMG (Object Modeling Group) where UML sits. That’s progressing and there are certain application domains, which seem to be more sensitive to it.

The linkage to the hardware side is finding more interest, he said, with smaller companies linking UML type models to SystemC, which leads naturally into the hardware world. “That’s happening and it’s progressing, but it’s in the very early stage of adoption. It’s definitely pre-chasm and not something that you will find broad adoption next year,” he said.

Integrating IP into models
When it comes to integrating IP into models, a robust model based on standards is needed. “We’re seeing a lot of customers who invested significantly in SystemC and TLM 2.0 as the standard level of abstraction at which you can create a fairly abstract model of a piece of IP for your system. You can still define timing and power characteristics around that piece of IP, so you can do what-if analysis. If you take in a third-party piece of IP—and quite a few third parties are starting to offer SystemC models and TLM models of their IP—you can take that IP, plug it into your system, start exercising that IP in various ways, and see how it interacts with the rest of your system,” Mentor’s McDonald said.

By having those robust standards and having models that are developed and interoperable between the companies supplying the IP and their customers consuming the IP, there is now the opportunity to really make detailed tradeoffs before committing to the implementation. It is likely too that System C will need to be extended over time to address some of the outstanding technical barriers.

From the user perspective, Mike Berry, senior director of engineering at Open-Silicon, explained that in terms of integrating IP into models, “We would look for either vendor-provided models of the IP to put into a bigger environment or go off and build those models ourselves if they are not available. Many designs today obviously use a lot of off-the-shelf IP in conjunction with some amount of custom designed logic—the customer’s secret sauce so to speak. Where IP can play a role in the modeling approach is that you can build up a model of a chip or a system using the models of the individual IP blocks and then use those off-the-shelf again to develop a standardized or non-custom part of the total model environment. You can adjust focus on developing custom models for the pieces that aren’t available off the shelf so, much like with hardware design, they can help expedite things and reduce the load on the design team. The same can be said for the modeling environment. You don’t have to develop all those models yourself you can take advantage of existing models for standard IP.”

By Ed Sperling
The tradeoffs between performance, power and area are being fine-tuned to a degree never seen before in the IC business, driven partly by complexity, partly by better tools, and partly by the need to gain a competitive edge in specific applications.

Just being able to make these kinds of tradeoffs is a technological feat that marries everything from high-level modeling and synthesis to prototypes of hardware and software and better characterization of IP. But being able to use the data from these tools more effectively is changing what can be done in design.

“This is going to be a way of life going forward,” said Jack Harding, president and CEO of eSilicon. “If you look at the number of variations between process nodes, types of IP and voltage, no human can sort through all the permutations anymore and come up with an optimal design, and certainly not around PPA.”

This is particularly true at 28nm, where power, performance and area are not linear extensions from previous nodes. And in stacked die, where multiple generations of technology at different voltages are packaged together, those tradeoffs may be greater still.

“The fact is that we may not know the best combinations anymore because there are too many things to consider,” said Harding. “I’m convinced this is a permanent change, too. I liken it to place and route in the early 1990s, where it was used to help smart guys design chips. By the late 1990s that had to be automated in all chips because the gate count was too high. We’re now approaching tool-assisted SoC architectures.”

Cause and effect
At least part of what’s behind this shift is market demand for more customized solutions. The move to subsystems and off-the-shelf IP means that companies have to find a way to differentiate their chips, something that will become even more apparent as the industry begins shifting to 2.5D and 3D stacks over the next couple years. Even the software might not be enough to differentiate the product in some markets, such as Android phones.

“The stakes are higher and the tools are better,” said Wally Rhines, chairman and CEO of Mentor Graphics. “Now a microwatt matters. It can be the difference in a win or a loss.”

The same is true of area and performance. But the new wrinkle is those variables almost need to be tweaked for each customer. Naveed Sherwani, president and CEO of Open-Silicon, said that for some of the large search engine, cloud computing and social media companies, the emphasis is on performance at any cost. This is contrary to the direction of most data centers, where power has become the major focus due the cost of running and cooling racks upon racks of servers.

“The reason PPA is changing is because now we can change it,” Sherwani said. “There are a lot more tools that can play with more things that affect power, performance, area and cost. We’re heading toward a very platform-style approach to design, so the changes from one customer to another may be only about 20%. With 3D stacking and memory, the next few years should be very interesting.”

Why now?
As with all significant changes in the IC business, there is no single factor that is responsible. The push to advanced nodes has added more complexity to designs, starting with more transistors (with 3D transistor designs at 14nm), more leakage, more features that require more complex power management, more IP re-use, a larger software component that needs to be written more quickly and with energy efficiency in mind. On top of that there are better tools for making these kinds of tradeoffs, and all of the big EDA companies are working on better analysis of the data that can be added into major flows.

Still, getting sufficiently good data to make these kinds of tradeoffs isn’t easy—even with better tools.

“PPA perplexes everyone,” said Bernard Murphy, chief technology officer at Atrenta. “The time to do PPA tradeoffs is early on, but the challenge is that there are a lot of unknowns at that time. There is recognition that if you can’t solve the big problem you can break it into smaller pieces, and these days not all of the design is unknown.”

He noted that Atrenta has been examining the effect of bus fabrics on the whole PPA equation. He said the direct influence on power is less, but they do contribute heavily to idle mode power, something that will become particularly apparent once wide I/O becomes mainstream.

“One of the reasons the NoC (network-on-chip) exists in the first place, and why ARM is looking at pseudo-NoCs is to control congestion,” he said. “The bus fabrics are only getting more complicated, and there is very little expertise in detailed performance analysis.”

Education is critical across the board in PPA. Teams of software engineers working with hardware engineers on designs alongside groups that are focused on manufacturability have expanded the scope of many design engineers. To some extent, everyone will have to think like a systems engineer in the future, even if they have their own area of expertise. But the very fact that they are talking to other team members is eliminating some of the silo behavior that various teams have lived with for the past couple of decades.

The future
While PPA has always been a way to spin cost, increasingly it also is seen as a way to improve time to market. Stacked die, and re-use of IP, subsystems and even entire platforms and die, will alter this equation even more—and add far more options for trading off power, performance and area.’

Those tradeoffs already are being done on a localized basis, with one IP block versus another or one processor core or multiple cores versus one or more other cores. In the future, it could include entire chips, as well, which may be customized quickly for individual markets or customers.

These changes also are likely to bring shifts within the supply chain. How the pieces will be reassembled is unknown at this point, but most experts agree that more change is inevitable.

By Ed Sperling
It was a good week for emulation. Mentor Graphics joined forces with MoreThanIP to create emulation solutions for multi-gigabit Ethernet SoCs.  Mentor also won a deal from ZTE for its Veloce emulator, and it added emulation solutions for USB 3.0 products.

Cadence and Samsung have developed a 32nm HD digital camera SoC for Ambarella, which has been creating digital still cameras with high-definition video capabilities. Translation: lots and lots of pixels. Cadence also teamed up with Xilinx for system design, software development and testing of Xilinx’s Zynq platform. And Cadence announced its quarterly numbers, showing net income of $28.1 million for the quarter ended Oct. 1 ($37.3 million non-GAAP) vs. $126.8 million in the same period in 2010 ($11.2 million non-GAAP). Revenue for the quarter was $292 million vs. $238 million in 2010.

eSilicon inked a deal to use Synopsys’ Custom IC design solution for 28nm SoCs. And Synopsys’ DesignWare Audio IP achieved first-pass silicon for 65nm and 55nm process technologies from multiple foundries.

Open-Silicon launched an ARM Center of Excellence to provide complete SoC development solutions for low-power chip development for the networking, telecommunications storage and computing markets. This is becoming a very cozy relationship. Open-Silicon already has a multi-year licensing agreement in place with ARM.

Atrenta introduced early PPA analysis for ARM’s AMBA designer using its SpyGlass and GenSys products.  Atrenta also joined Cadence’s System Realization Alliance, which is no surprise considering it was one of the first to adopt Cadence’s EDA360 terminology.

Arteris won a deal from VIA Telecom for its high-speed inter-chip communications IP between mobile phone baseband chips and application processors.

Tensilica won a deal from EnVerv, which licensed Tensilica’s ConnX DSP cores for its smart grid power line communications SoCs.

By Ann Steffora Mutschler
By and large most designs today are derivatives, meaning they don’t start from a blank slate. And while that gives engineering teams a starting point, it also can make adding new IP blocks or changes to the design problematic, with the potential for increased routing and timing issues along with considerable pain to back-end engineers and delays in chip schedules.

Derivatives can be split into a number of categories, depending on the market or the evolution of technology at any point in time.

“Let’s say in a chip there is a certain amount of embedded memory and they want to remove it,” said Kalar Rajendiran, senior director of marketing at eSilicon. “Maybe the memory block they had was not efficiently implemented and it was taking too much space, so they only put in 1 megabyte. They release a product and then they may say they want to do a derivative product to increase memory capacity to run more programs. That’s a simple change conceptually–add more memory to it–and you would call that a derivative design because it is slightly different from the previous one.”

Other types of derivatives can involve changing the interface or functionality, regional adjustments to support different temperature conditions, or variants in terms of geography that would support differences in TV broadcast compliance, for example.

Neil Hand, group director of marketing for Cadence’s SoC realization group, observed that the definition of a derivative design has fundamentally shifted over the last couple of years. In the past, an engineering team could sit down, design a chip and develop five derivatives of it for each different market by swapping out the IP blocks and tweaking the system for each of those markets.

“That definition of derivative is dead because you can’t afford to do it,” Hand said. “If you look at how people approach it today, they use more of a platform. They put all of the IP they need for all the different applications on the design and then they’ll package it appropriately, depending on the target market, or will turn things on and off in software or hardware in order to make it fit that application. A good example of that is if you look at what Apple does with the A4 and the A5. It’s one design that targets multiple devices, whereas in the past that would have been multiple different chips.”

The stakes get higher along with Moore’s Law, too.

“With 40 and 28nm nodes, these are getting to be quite expensive from an SoC development perspective,” said Navraj Nandra, senior director of marketing for DesignWare Analog and MSIP at Synopsys. “What we are seeing at 28nm especially with our customers is they are developing an SoC but you can almost consider it an application platform and it is designed for a couple of market segments. The two big ones are smart phones and tablets.”

The methodology from an SoC perspective and the IP requirements to address those applications are similar but not exactly the same. “In order to ship the products out quickly to market and because the typical development cost of a 28nm SoC is at least $100 million now, if you want to get one of these chips out to market you’re going to have to invest at least $100 million—and that’s just on the SoC side. You’ve got way more costs on developing the software on top of that. So the expenditure is significant,” he continued.

Power consumption is often addressed in derivative designs. When the initial excitement about a product has gone away, customers want more battery life. Derivatives can focus on reducing power consumption, which in turn can have an effect on how you put your SoC design methodology together and how you develop the IP, Nandra said.

A recent customer visit illustrated this perfectly. “I was in Korea a couple of weeks ago and met with a company that develops TVs. I met the design team, and this particular design team develops the chipsets for the high-end TVs. Their SoC had all the latest IP requirements. The technology was designed with a very fast data path to do a lot of number crunching. This team now is looking at getting into the low-cost digital TV market, so they want to build a derivative chip that needs to have similar functionality to the high-end chip but that needs to be cheaper,” he added.

Managing complexity
As design platforms get bigger, and engineering teams must dealing with more IP blocks, the story really becomes about how to manage these huge IP platforms talking to each other, said Cadence’s Hand. “In the old days it was one monolithic design—easy to manage, no real problems, and it was a relatively small die. Then you got to the first realm of where we are today where you had tens of IP blocks and you could use relatively simple interconnects and the dies were relatively small. Now you look at the modern designs and every thing about them has become big.”

As a result, a holistic view must be taken of what it means to throw these connections together. “You can’t do necessarily what’s easiest for the system guys to the exclusion of the IP and the silicon. You can’t just do what makes the silicon guys happy because that may mess up your system performance. And you have to have that holistic view of cross all the realizations: silicon, SoC and system,” Hand added.

One of the most important considerations of starting with a baseline product with the intention to expand it in the future is time to market. Getting the chip out there, winning sockets and getting it into the customer’s hands so they can start working with it is critical.

“In some cases you can imagine going into a program development and at the beginning having very good intentions about designing in features, designing in configurability, parameterization, things like that to enable those future expansions to happen,” said Mike Berry, senior director of engineering at Open-Silicon. “But sometimes you can end up making tradeoffs as you go through the design flow. You may be losing some of that or not making it quite as robust as was originally envisioned by the product marketing guys or the architects of the program. Then, when you go to do that next version there could be some things you have to deal with, some warts that may, if they had been implemented in a slightly different way, have made the expansion a little bit easier. So you might have to go back and do some rework, either within the RTL or within the test environment to effectively roll in those new features.”

Sometimes however, the biggest challenges that come up with derivatives are not related to the technology but rather, the market.

“The bigger problem they run into is a market problem,” said Bernard Murphy, CTO of Atrenta. “So you build the super chip in anticipation that you’ll be able to do the low-cost version and the low-power version and the future phone version and then you find the super chip wasn’t that much of a home run so the derivatives become irrelevant. But that is not a design problem. I had somebody at one company tell me that happens 9 times out of 10. But how many home runs do you really see?”

Planning ahead
When an engineering team knows they will be doing derivatives, it makes sense to plan ahead to make it simpler to make the changes down the road….but do they?

“Yes and no,” said Kurt Shuler, VP of marketing at Arteris. “When they draw that block diagram and they create their internal roadmap slides and they have a block diagram of a chip and the derivatives, they have it tied together with a bunch of lines on the chart. You think that anything is going to be fine. But depending on the interconnect technology you use, each time you create one of those derivative chips can almost be like creating a whole new chip, and the reason is because of the back-end problems. To the SoC architect who is creating drawings of stuff, then the chip designers and the chip engineers are creating RTL, that then gets synthesized down into gates and eventually gets placed on the chip.”

Things don’t usually work out that smoothly, however.

“There is a disconnect between the architect’s drawing of a nice, clean, pretty picture of the chip, and nice, clean, pretty RTL and then when you go and try to design it in a chip, it looks like hell–you have all kinds of timing problems and what have you and you have to futz with it forever,” Shuler continued. “That is the biggest issue. A lot of companies say they are doing ‘the platform approach’ and are creating all these derivatives based off of this thing but are not seeing the benefits they expect. When you talk to the back-end people you find out the derivatives can take as long as the original chip did. That should be a red flag. If you don’t look at the platform holistically you’re going to be disappointed.”

By Ed Sperling
Synopsys created the first TLM Web portal, complete with an initial offering of 600 models, and inked a deal to distribute ARM’s Cortex processor models from its new TLMCentral site. Synopsys said it hopes the portal will spur investment in virtual prototyping.

Mentor Graphics won a deal with Fujitsu for its embedded software development environment, which will be used for Fujitsu’s general-purpose 32-bit microcontrollers. What’s interesting here is that Fujitsu chose Mentor’s Embedded Sourcery CodeBench for ARM’s microcontroller IP, which will be included in the Fujitsu product. It’s an unusual keyhole into the microcontroller space.

ARM cut another deal, too, which must have had the corporate lawyers hopping. Open-Silicon signed a multi-year agreement to license a broad portfolio of ARM technology, which allows Open-Silicon to offer ARM’s IP with its own design and manufacturing services. We may be witnessing a change in the wholesale distribution model.

Tensilica inked a deal with Fraunhofer IIS, which allows Erlagen, Germany-based Fraunhofer to become a design center partner for Tensilica’s HiFi Audio DSPs. Fraunhofer, incidentally, is part of the Fraunhofer-Gesellschaft research organization, which is partly funded by the German government.

ST-Ericsson reportedly gained a 10x improvement in time by using using Cadence’s mixed-signal flow for its 40nm baseband chip. Create automation tools for analog engineers, force them to hit tight schedules within budget, and apparently they’ll use these tools.

By Ann Steffora Mutschler
Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a thing of the past for most SoC design teams, and so will portability between designs.

Specifically, the ability to randomly add in new IP or substitute IP will be severely limited because the DP coloring constraints have a lot of interaction problems between cells, explained David Abercrombie, program manager for advanced physical verification methodologies at Mentor Graphics. “If the cells don’t follow the same methodology in regard to coloring boundary conditions in something as simple as an IP library of standard cells, and they know the cells are going to butt each other (share the power and ground), then because they have to be colored you can’t allow the power rail in one cell to be on mask zero and the power rail on the next cell to be on mask one. They have to end up on the same mask. So you need to enforce that all the powers have a certain coloring and all the grounds have a certain coloring.”

That all works fine in theory until someone else designs an IP library and make all of theirs zeroes. The two of those cannot be combined together. And as with all new processes, the design rules and process details are not clear.

“I’ve heard two schools of thought,” said Manoj Chacko, product marketing director at Cadence. “One school says everything will be decomposed from a cellblock IP level and designers will have to work with decomposed layouts. There is another school of thought saying, ‘Meet our rules, don’t worry about decomposing it, go through your traditional flow but you have to meet all these additional double patterning rules in addition to the traditional design rules. When you come to the end there are qualified double-patterning decomposition tools/engines that all the EDA vendors have. They can decompose it, and then there is a small iterative cycle just to ensure that you have no issues and conflicts and that this is all compliant with what the foundry has.”

But this hasn’t just happened overnight. Hans Bouwmeester, director of IP engineering at Open-Silicon, said that at 40nm, we started seeing limitations on what we could do related to the memories. “In 28nm you see more of those limitations requiring a single poly direction for the entire chip. Portability of IP becomes more and more a concern especially when it concerns analog IP. It doesn’t scale well so you don’t get the area benefits going to the deeper submicron process. So it is definitely a factor that comes more and more into play as we go into deep submicron processes.”

Since 65nm, Jean-Marie Brunet, marketing director for DFM products at Mentor Graphics, has observed a fundamental shift with respect to IP design. In the past, IP designers used to create their IP without regard to where it was going to be used and in what context. Now, with DFM lithography proximity effects, IP vendors have to design their IP knowing it will be used in context No. 1 with one chip and context No. 2 with a different chip. “Unfortunately with advanced nodes, optical radius and OPC effects, the context started to severely affect the intrinsic behavior of the IP. And that is a fundamental shift. They have to make the IP very context free, which is very difficult.”

These contextual issues call for examination of the lithography context to an IP, such as CMP effects, and analysis of contextual problems. The contextual issues get more intense the smaller the node.

Due to contextual issues and other challenges, IP re-use at 20nm with double-patterning will be very complicated. “There’s no question that at 20nm and below those are going to be very different nodes. Design flow, design methodology that we are working on right now, as well as other competitors, is going to be very difficult. I’m not too sure yet if the industry has found an easy way to do IP re-use with double-patterning. We are all going through test chips right now, validation vehicles for reference flows, and re-use of blocks. And each time we are struggling,” Brunet said.

“Solutions are being put together, but I will not say this is a done deal. We will go through issues with double-patterning. Unfortunately, it is going to be very high in cost–not only in mask and silicon, but in design flows as well. I think we’re going toward actually having severe limitations on the type of design styles and rules just because of the nature of double-patterning,” he added.

With each more advanced manufacturing node, the problem will be significantly more painful for tier-two and tier-three SoC developers, as industry players discuss in this video.

Open-Silicon’s Bouwmeester is a bit more optimistic about IP portability in the future. “I’m not completely sure whether it is going to be completely a thing of the past, but I would certainly agree that the expenses IP vendors have to take in order to port IP between foundries are going up. There is more work involved for them to bring a piece of IP they may have for example in a TSMC 28nm process to Global Foundries, and that is expected to continue or become worse as we go to more deep submicron processes. I guess there also may be more business considerations in that TSMC being the lead foundry is getting more and more protective to prevent other foundries from copying parts of their process. In other words, TSMC has a business interest in making it harder to support portability between foundries.

But Abercrombie insisted, “Even though IP vendors would sell you a library for one foundry versus a library for another foundry, honestly, we all know under the hood they built one library and it took the least common denominator. The rules were close enough that just being a little bit intelligent you could make a set that would run on either one. At 20nm and below, no. We talk to these guys and they have to build completely different, from-scratch libraries. There’s no possible way to make one. It says portability is out the window.”

It’s not all bad news, though. Navraj Nandra, senior director of marketing for analog/mixed-signal IP at Synopsys said, “If you are doing libraries and IP development you have to nowadays be early with the technology such that when customers are ready to work in these new nodes they see a bunch of IP available. We see some of these stresses early on. Some of the customers I’m speaking to at the moment are scoping out their 20 nm options—for the ones that are considering 20 nm.”

While he recognizes that IP development complications with 20nm are at least twice the complications of 28nm, he pointed out, “That’s my problem but it’s not my customer’s problem. My customers don’t care. All they care about is making sure schedules and performances are met.”

Walter Ng, vice president of GlobalFoundries’ IP ecosystem, acknowledged there is fear surrounding IP portability at 20nm. “We do see a good amount of concern among the design community with regard to the impact of double patterning on each of them and what it will mean to them and how much it will increase the complexity and difficulty of their task. We are always sensitive to that. In this case, as we go down the technology curve, it’s going to be more and more challenging to achieve the entitlement that maybe over many of the technology nodes previously has just been an expectation.”

“Double-patterning is the only way at this point that we or anybody else can achieve the 2X density that is expected. And we certainly are trying to minimize the requirement because it goes back to balance. We understand the economics of this in addition to the technical challenges, and we are trying to minimize the double-patterning requirements such that it can stay an economically viable technology node both from a processing cost as well as a design cost,” he continued.

As such, GlobalFoundries does real-time collaboration with the top EDA companies, as well as major IP providers.

On top of double patterning, Ng agreed that from an IP portability standpoint 20nm brings another challenge. “The reality among the design community is that even at 28nm, its been very challenging with regard to wanting to preserve portability where it wasn’t intended from the outset.”

“If you want to achieve optimal IP implementation, even if you wanted to try to look at a superset approach and be satisfied with ‘fat’ IP, it hasn’t been easy,” he said. “We have whittled away at the ability to easily port unless it is by design. When it comes to double-patterning and 20nm it certainly ups the bar, and it does make IP portability across random manufacturers a nearly impossible task because of certain aspects of the process definitions as well as the decomposition rules themselves. It’s not going to be the same. With the level of detail, unless it is planned for up front by design, it will be virtually impossible.”

However, he concluded, “It starts subtracting from the value statement of moving to that next technology node. If you’re going to do that superset where you’re not taking advantage of optimizing your IP and optimizing your design for a specific technology node, then you really should be considering whether you should be moving to that node because you’re just leaving so much on the table.”

By Ed Sperling
Mentor Graphics is working with TSMC to add automated fill functionality into Calibre YieldEnhancer, starting at 65nm. The approach uses continuous, multidimensional functions rather than linear pass/fail conditions, which allows the use of more complex fill algorithms. This becomes particularly important at advanced geometries.

Open-Silicon received a patent for its low-power design methodology. By creating standard cells using on-the-fly design-specific libraries, the designs can be optimized for power, performance and/or noise. All of this is done using post-layout patterns, as well, which minimizes problems with dynamic libraries that have surfaced in the past.

Tensilica issued a slew of announcements involving customer wins and partnerships. Cavium chose Tensilica’s baseband IP for its next-generation wireless products based on performance and programmability. Tel Aviv-based EtherWaves ported Tensilica’s dataplane processor architecture to its digital radio IP for cars and SoCs.  In addition, Tensilica and Audyssey are working together to add sound correction to Tensilica’s HiFi audio DSPs for digital TV, automotive and mobile applications. And SRS Labs expanded its surround-sound and audio enhancement IP portfolio for Tensilica processors.