By Ann Steffora Mutschler
Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up.

The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending on the packaging technology used, certain system parameters are either limited or not. For these reasons packaging is being considered up front in the design process—even at the very earliest planning stages. Moreover, the cost of packaging comprises a non-trivial portion of the total system cost. Throw 2.5D and 3D ICs into the mix and things get really interesting.

These issues are breaking down the brick walls between the IC designer and the packaging designer, observed Brad Griffin, product marketing director for Cadence’s Allegro product line. “I think we have hit a point where if you don’t at least consider some of the aspects simultaneously you’re going to end up with a system that either doesn’t perform like you would like it to or has additional cost than you would like it to have.”

Shafy Eltoukhy, vice president of manufacturing operations at Open-Silicon, agrees. “Essentially when we talk to the customer initially we try to understand from them what their thermal requirements are, like power, the footprint of the package, the thickness of the package and the cost. Also, if it’s a consumer part it will be different than if it’s a networking part. The cost has a big impact on the selling price. There are a lot of factors that come in at the very beginning, that being the power dissipation, signal integrity, form factor of the package and so on.”

There’s a complicated matrix to designing a package. “In some cases, at the very beginning, you don’t know exactly what the die size is going to be because customers keep adding functions and the die size keeps changing in the early stage. Having all the requirements from the mechanical to power to this and that, as well as the layout or the floorplan of the die, is also changing up front. The package has to be part of the very early stage of the design,” he said.

The company ties the package to the floor planning and the requirement as far as the speed and other considerations. Package design engineers get on board very early in the process—even before designing the die itself—to look at it from the floor planning point of view. That includes where to put high-speed interfaces, how fast these are going to be, packaging technology, i.e. flip chip or wirebond, power expectations, and so on. “It’s very complicated and people have started putting a very good interface between the packaging and floor planning engineers,” Eltoukhy added.

Broadcom recently detailed its experience making early tradeoffs during Cadence’s CDN Live event in March. The presentation can be viewed here (registration required).

In this case, using Cadence technology under development, Broadcom enabled its PCB designer to look at what the package footprint should be to best match the components on the board. From there it drives up from the package footprint to the bump matrix for the chip. They were able to determine the ideal bump matrix for the chip to be able to match the package footprint. Then from the bump matrix that drove the I/O pad ring to get the I/Os and chips placed properly.

Then, when it comes to 2.5D design, packaging issues are actually more complex than what they will be with true 3D ICs, according to John Park, methodology architect for IC packaging and pathfinding technologies in the Systems Design Division of Mentor Graphics. “I believe—and many of my customers believe—it is more complex because you have this intermediate substrate in which the die connect through these small microbumps, and there’s this die-to-die connectivity that happens on some unknown number.”

Engineering teams really want to save costs, or at least make the tradeoff of cost and thermal, etc., Park added. “They want some global routing technology that allows them to say, ‘What if, on the interposer, I limit it to three metal layers? Does that mean I need to add two more layers to my package substrate or does it mean that I have to add eight more layers to my package substrate?’ In that case, maybe they say, ‘I’m going to add one more metal layer to my silicon interposer so that I can reduce the layer count of the package.’ Now the costing gets very complex because you have this new intermediate routing structure that sits in between the traditional die to package connectivity that greatly impacts cost, routability, signal quality—all these types of things.”

Although some of these issues won’t be a problem with 3D, don’t expect a mass exodus from 2.5D when 3D becomes mainstream because it may be more expensive, noted Cadence’s Griffin. “You’re going to have to get to a certain quantity before you’re going to realize the value in going to 3D IC, so there’s going to be still a fair amount of chips in the lower to mid quantities for which they want to realize the performance gains of going to a silicon substrate to connect things together but they can’t necessarily go to the expensive TSMC to be able to connect all these things together properly. [Systems companies] will rely on less-expensive silicon interposer technology; it will have a little less performance but cost-wise, it will just be more efficient for them. I think you’re going to see both for quite some time, but i think you’re going to see the very-high-quantity things move to 3D IC as much as possible.”

By Ed Sperling
Mentor Graphics rolled out the next generation of its Veloce2 emulation platform, adding virtualization capabilities. The key here is that it allows software engineers to use the platform to verify their software from their PCs, rather than having to go into a lab to work on their code. This is a new wrinkle in emulation, which is now being used as much for software verification as for hardware. Appealing to software engineers is a whole different world.

Cadence roared back to life in Q1, with revenue increasing to $316 million compared to $266 million in Q1 of 2011. Net income was $31 million compared with $6 million in the same period last year. On a non-GAAP basis, net income was $47 million compared with $23 million in 2010. The company expects revenue of between $315 million and $325 million this quarter.

Synopsys extended visibility in HAPS debug FPGA prototypes, adding about 100 times more storage capacity for signal traces while slashing memory utilization for complex designs.

Open-Silicon expanded its solutions portfolio to include architectural analysis and modeling, pre-silicon prototyping, embedded software, co-silicon system design and test and post-silicon validation. It also expanded its ARM Center of Excellence and boosted staffing at its design center in Pune, India.

Tensilica added support for China’s Dynamic Resolution Adaptation standard to its audio encoder/decoder library for its HiFi Audio DSPs. That should open up a huge market.

Soitec said it is ready to provide fully depleted silicon-on-insulator wafers for both 2D and 3D customers. The company claims significant cost savings over bulk CMOS at advanced nodes—a major shift from previous nodes.

By Ann Steffora Mutschler
For the past 30 years, semiconductor designers have increasingly relied on automated CAD tools to complete their projects. Over time, these tools have indeed improved from a functionality perspective, but sometimes usability has not kept up with users’ needs.

Depending on which tools and what type of use, some tools are easier to use than others, according to Mike Berry, senior director of engineering at Open-Silicon.

“In general, if you’re talking about the smaller, simpler sorts of designs, it’s fairly easy to go into a tool even if you are reasonably new to it and figure out how to do some of the basic functions. If you’re doing simulation, how do you actually start a simulation running? How do you bring a waveform up in a viewer to look at it? Those sorts of things are easy. If you are doing place and route, you find the button to push to say, ‘Go do a placement,’ or ‘Go insert clocks for me,’ ‘Go do detailed routing.’ It’s when you start getting into the more complex designs where things quickly start to become a lot more challenging because as the tools have evolved over the years, one of the things that we’ve seen happen is that more and more knobs and switches get added to tools, but old ones often aren’t taken away even though they might either be redundant or they might be obsolete or they might not even work anymore or they might contradict some other things that are in the tools. We run into that sort of thing sometimes,” he explained.

What makes a tool easy (or not) to use often comes down to the user interface. “If you’re working with a single tool and using it year after year after year, you get a feel for how it works and how to navigate. But moving between tools is very challenging,” Berry said. As Open-Silicon does a lot of design services, it often is requested or required to use different tools from program to program—a very difficult transition because the user interfaces are so different and in some cases, they’re just not very good.

“One of the things that we’ve talked about here for years is that it seems like in many cases the people developing the tools and developing those user interfaces are software people. This kind of makes sense that that’s who would be writing the underlying code but we can’t help but wonder do those software people ever really talk to the people that use the tools—the hardware designers—and understand, ‘It’s great to have this knob, but I don’t understand what it does or why I care that you did it.’ It’s a really cool programming exercise to figure out how to do that but it’s just not necessarily useful in the real world. That’s been a complaint of ours for years and years. The tools are not geared toward the users’ needs for the tools, even some of the functionality they provide,” he said.

Another issue that complicates EDA tool usage is error messages that come out of the tools. “In many cases the word I think you’ll hear from most people is ‘cryptic.’ You get this error message: ‘Stack trace fault at hex 3279,’ and then the tool sits there with a blinking cursor waiting for you to do the next thing, and it’s like, ‘What do I do with that?’” Berry pointed out. “That one may be an extreme but something about ‘couldn’t find net to query’ or something really, really cryptic. You have no idea what line number in the script it was at, or anything about it, and you just stare at it and think, ‘I don’t know what to do.’ We start doing binary searches through the code. Let’s delete the bottom half of the code, and run the top half and see if we still get that message. We start trying to start zero in on where the problem is and eventually usually you can find out what’s going on but the amount of debug time is really painful sometimes.”

One particular set of tools that Open-Silicon is using now is just terrible in terms of some basic features that should exist but don’t, Berry said. As a result, his team has resorted to writing their own TCL algorithms to access very low-level database functions to do some things that just should be there. “The database obviously has all of the information you need and you can in fact query it, but instead of right clicking on a net and asking for some information about it, you have to write 20 lines of code that essentially uses the API that exists to get into the database.”

Tool providers chime in
Jeff Wilson, Calibre product marketing manager at Mentor Graphics, noted that users always want the tools to be easier to use. “We have is a spectrum. For example, in a fab there are people who really understand Calibre so other people have someone they go to and ask about. In fabless companies we probably need something that’s a little more turnkey. They do have expertise they can go to ask questions. But fabless guys are all over the spectrum as well. They are leading-edge guys who basically take the deck and run stuff. If it’s a test engineer we’re learning what particular applications we want to lead with and which ones we would probably not lead with just because of the learning curve involved. We’ve had very good success being able to work with customers to be able to prove out the data points, but now we’re in this space of fine tuning that to be able to say for this particular customer, this is the message and the packaging that we’d need to go with.”

Connected to this is the work EDA vendors do on an ongoing basis to broaden the reach of the tools.

Robert Ruiz, senior product line manager for test automation at Synopsys, noted that last year the company started addressing the ability for a broader set of users to easily set up the tools rather than just the traditional person using volume diagnostic tools. Additionally, Synopsys test tools now support the LEF DEF standard as well as a SEMI standard that describes tester output in order to allow users to gather data from many different types of testers.

Similarly, Geir Eide, DFT product marketing manager at Mentor Graphics, said usability is becoming extremely important as lines blur between domains. “We have tools that are made for yield or product engineers that are based on test technology. We have to make sure it doesn’t look like another test tool because it’s not really for test people. This is something we have tried to take into account and it’s going to continue to be important as we see technology versus domain crossover-type things. People always want easier to use tools but the meaning of ‘easy to use’ is changing a little. A lot of the tools we have are built on DFT technology but the users are either product engineers or failure analysis engineers that know absolutely nothing about DFT or the underlying technology so we have to try to make that part of it invisible. You don’t have to force everybody to take courses in DFT just to utilize some of the data that that provides.”

At the end of the day, Open-Silicon’s Berry gave credit to the EDA tool companies for the advances in the algorithms tools are using, and the way they approach doing certain functions. “There’s been a lot of algorithmic development and lots of optimizations within the tools to help with runtimes and help with making it possible to manage huge sets of data in ways that were just not possible not very many years ago. Certainly there’s a lot of development work going on there. The advent of some of the new design verification methodologies starting back with Specman, Vera, VMM, OVM and now UVM—that’s been a huge improvement in verification productivity and thoroughness. That’s a very, very powerful recent addition to the tool flows.”

By Ann Steffora Mutschler
As semiconductor manufacturing technology continues its march toward 20nm, SoCs are plagued with advanced interconnect delays, cross capacitance, and process variability, as well as area and power constraints—and the significance of these factors is increasing with each passing node.

“With lower nodes we are getting advantage on area, more and more logic is getting included onto the dies, which means many interfaces are also integrated on the same die. All the interfaces may have their own unique requirements of clocking and when they interface with each other there are many constraints that come into picture which result into complex clocking schemes for the ASICs,” explained Shrikrishna Mehetre, engineering manager at Open-Silicon.

In advanced SoCs additional modes of operation dictate that extra tradeoffs in timing closure must be made to make sure the device works in all of the different modes and with the minimal amount of power, said Andy Inness, place and route specialist at Mentor Graphics. “Fixing power in one mode may break an operation in another mode. You need to make sure you take both into account, so when you optimize one you don’t break a different one.” The physical effects of advanced nodes can have varied impacts because as the voltage is varied, the physical effects are different in different voltages.

Advanced timing closure requires the P&R tool to account for all operating modes, and all process corners. This significantly reduces the number of timing violations and helps for faster timing convergence. Source: Mentor Graphics

In recent designs, Open-Silicon has seen that additional complexity as it has integrated numerous such interfaces and ended up with as many as 400 clock domains, many of which are generated clocks and dependent on each other. While so many interdependent clocks interact with each other on a 18mm x 18mm die, the insertions delays and skews for all these clocks and their impact on the overall timing optimizations is huge.

In addition to the clocking requirement for the design functionality, complexity also comes from the DFT logic addition and the test requirement for such huge logic and memories in the designs because the clocking requirements for DFT logic add to the complexity of the design. In this scenario, the timing optimization is not just restricted to achieving better data path delays. It also requires consideration of physical effects such as interconnect delays, cross cap, the clocking skews and variability.

High frequencies = extreme variability
Companies like Open-Silicon are working with clocks ranging from hundreds of MHz to a few GHz at 40nm and 28nm technology nodes. At such high frequencies achieving the required skews and insertion delays for such a big clock network over large dies is very challenging. The variability across different functional/DFT modes and different process corners is very high. When combined with clock distribution over a huge die and the variability at smaller nodes, timing optimization needs to consider these large overheads, Mehetre said. Power optimizations using clock gating has become the norm, but achieving timing closure for clock-gating latches is an additional complexity the needs to be addressed.

In addition, timing optimization is not a standalone task anymore. It needs to consider all the parameters such as clock period available, physical effects (interconnect delays, cross talk, variability), and clock skews across different corners and modes. Adding in excessive margins at different stages (such as data-path optimization before CTS, clock skew opt after CTS, variability optimization after CTS is completed, SI optimization after routing is done) is becoming inefficient at smaller nodes. EDA tools needs to model these effects right from the initial optimizations rather than relying on margins at different stages. For instance, instead of applying a single OCV number for the entire design, Mehetre said it’s better to use AOCV (local OCV), and all the IP vendors need to support AOCV models at smaller nodes. So instead of trying to achieve a global skew number, effort should be put in to utilize the useful skew and planning for the useful skew should be done from initial optimizations.

The impact of shrinking process nodes
While there was an era when interconnect delays were marginal with respect to cell delays, the situation seems to be reversing beginning at 28nm. Enhanced physical synthesis considering the clocking and modeling of the interconnect/cross-talk delays, variability is needed to replace added margins for these designs. Also, logical optimizations that consider variability and different corners needs to be part of the initial optimizations, Mehetre asserted.

As such, there needs to be change in the way clocks are used for such huge designs. Rather than looking at how to optimize timing and clocks for the effects, the approach should be how to minimize the impact of these effects during the architecture and RTL design phase itself. This is especially true if the clocks are to be shared or if they are interdependent, and during the logic design the goal should be to reduce interdependency.

Paul Cunningham, senior group director of R&D at Cadence agreed that smaller geometries are having an impact and that, by far, the biggest impact is on the wires rather than scaling of the transistors. “The transistors are getting smaller faster than the wires. We went from being all about the transistors to more about the overall wire capacitances and then at the very advanced nodes—28nm and below—we’re seeing it’s more and more about the resistances in the wires.”

All of these issues require engineering teams to rethink the algorithms, which has led to a clock concurrent optimization process, he said. “The underlying model in timing terms is, rather than thinking about a path in the design—I call them chains—where a chain would be a sequence of functions that span multiple register boundaries. Eventually these functions form some kind of a feedback loop and it’s that loop that really dictates the speed. In a traditional flow, if I’ve got a four-pipeline stage loop, my speed is driven by whichever of those four pipeline stages is the longest. In a clock concurrent world, I’m going to take the average of those four pipeline stages and that’s what drives the speed of my chip.”

Embracing that approach has required major changes to the tools themselves. “It’s a complete genetic rewrite in terms of the algorithm,” Cunningham asserted. “To the end user, it just looks like a new kind of next-generation step in the flow. So I’ve just rewritten step ‘n.’ What comes into step n, what goes out of step n is still the same but the actual result is now much better for power, performance and area. You are really optimizing the clock parts and the logic parts at the same time.”

Overall, boundaries are blurring throughout the entire optimization flow and the trend in the industry is towards the different optimization steps becoming more and more intimately linked so it’s a very, very smooth transition and possibly its a more fine-grained transition as you go from step n to step n+1 to step n+2. Twenty years ago they were really very distinct, isolated steps almost as if you were running different tools, he observed.

“It’s really the sum of all the steps—making the combination greater than the sum of its parts—that’s where the industry is focused these days,” Cunningham concluded.

By Ed Sperling
Among tools vendors it’s been standard practice to listen closely to customers but not deliver everything they ask for—or at least not always on the customers’ timetable.

This strategy has worked well enough for both sides in the past, but at 20nm and in stacked die configurations, the level of tension between these two worlds is increasing, and the gaps in the tool chain are becoming more noticeable. Part of the problem is that skyrocketing complexity is forcing more automation, but integration issues, physical effects, process variation and the realities of physics make it more difficult and time-consuming to develop tools to make that complexity more manageable. R&D budgets for EDA companies already are hovering around 30% or more, compared with average R&D investments of about 10% to 20% in other areas of chip development and manufacturing, and betting on the wrong area can have a significant impact on EDA company’s earnings.

The other part of the problem is that chipmakers’ own internal tools are running out of steam at advanced nodes because of the need to bridge both hardware and software design environments and because old methods of doing things are way too slow and very often ineffective. This is clearly reflected in the fortunes of EDA tools vendors, which have been rising steadily for the past couple of years, with the strongest growth in areas such as ESL, including hardware-software co-design and software prototyping, and emulation.

Add in stacking of die, in both 2.5D and 3D configurations, and the number of issues that have to be dealt with by both chipmakers and tools vendors increases by orders of magnitude. On top of that there are double patterning issues at 20nm, finFETs at 14, and potentially 450mm wafers that will require significantly higher yields to be cost-effective, but which may be harder to test in wafer-on-wafer or die-on-wafer configurations.

Where chipmakers see challenges
Riko Radocjic, director of design for silicon initiatives at Qualcomm, breaks the design process down into three areas—design authoring, which is the actual chip design; pathfinding, which includes exploration for how to best build a chip; and tech tuning, which is physical space exploration. Most of the EDA tools have been effective in the design-authoring phase, with some point tools now finding their way into the pathfinding area. But the real challenges are in the tech-tuning area.

Mechanical stress becomes a serious issue in 3D stacks, ranging from the effects of TSVs to die alignment. “You cannot solve the problems with a tool. They have to be solved in a flow,” he said. “It’s a debug nightmare. You need a separate domain that takes external stresses and produces a set of rules. You also need hotspot checking to make sure you have caught all of the interactions.”

Also missing, he said, are EDA tools that understand the materials inside a stacked die, and a standard PDK for all mechanical and thermal properties.

“Thermal is the next frontier,” he said during a presentation at the Electronic Design Process Symposium this month. “You need to manage for hotspots and overall system power. On a global level you have skin temperature and overall system power. On a local level you have to manage hot spots, junction temperatures and power density. And there is also the compounding factor that all advanced systems use some form of thermal management. We need a system-chip co-design methodology and tools to deal with this. We cannot solve thermal issues only at the component level. It must be system and component, and we will need tools for pathfinding thermal issues. We don’t even know where to put our thermal sensors. We need thermally aware floor planning.”

Summing it up, he said it amounts to 3D-aware co-design tools for package, system and thermal, and a flow to integrate everything.

A stacked die of the future; memory on top left, with logic/memory in middle on top and I/O and analog RF blocks on top right. All feed into interposer stack in the middle. Source: Qualcomm.

Altera, which has just developed its first 2.5D stacked FPGA prototype, is encountering similar thermal and mechanical issues. While the company continues to offer scaled down tools for FPGA development, it needs the most advanced tooling for creating those FPGAs in the first place. Topping his list are robust standards for cells, IP and stacked ICs, as well as tools to help quickly identify some of the problems that Altera encountered while developing its prototype stacked die.

Signal integrity issues encountered and addressed by Altera in stacked die using interposers.

“We’re looking for more of a divide and conquer strategy,” said Arif Rahman, product architect at Altera. “Die stacking will be an enabler for a complete solution in the future, but it will not just be an FPGA. It will be an FPGA plus other accompanying functions.”

Where EDA tools vendors see challenges
For the tools vendors, the list of problems that need to be solved is exploding. So many things need to be fixed and solved that it’s imperative just to focus on both what will have the most impact and what will provide the greatest long-term returns.

At least part of that effort involves existing tools, which have to be run faster and do more things than in the past. This is particularly true in areas such as emulation, which in the past were used almost exclusively for hardware. They are now becoming the tool of choice for software verification because the complexity of the software makes it far too slow to run using simulation. What takes hours or days in simulation can be measured in seconds in emulation. And given the fact that verification is still the lion’s share of the NRE, anything that can be done to solve this problem is considered a big win.

Mentor Graphics’ announcement this week of enhancements to its emulation tools is a case in point. Recognizing that software engineers are using the emulation tools as much as the hardware engineers, the company has added a virtualization layer that allows a workstation to be a front end—matching the way software engineers work—rather than doing work in a lab the way hardware engineers typically work.

“This allows one workstation per user,” said Jim Kenney, director of marketing for Mentor’s Emulation Division. “We’ve also been working to improve performance and capacity so you have more robust software execution and debug.”

Mentor isn’t alone in this quest. Cadence has been updating its own emulation, and all the EDA vendors have been racing to improve the reach and integration of their tools. Bassilios Petrakis, product marketing director at Cadence, noted that building smaller die that yield better is still a challenge that needs to be solved—particularly before stacking becomes mainstream.

“When you look at multiple die with TSVs, the cons are that the ecosystem is still emerging, there is no volume production yet and there are thermal issues,” Petrakis said.

Samta Bansal, senior product marketing for SoC Realization at Cadence, predicts that stacking memory on logic using an interposer will become mainstream beginning in 2013 to 2014, with TSVs becoming mainstream by 2015. She said work in EDA typically needs to begin three to four years before these efforts, noting that it began in earnest at Cadence in 2009. Synopsys rolled out its 2.5D tool flow last month and is working on a full 3D flow, and Mentor has been working on a variety of areas ranging from test to modeling of stacked die over the past several years.

But EDA vendors also need to pick new areas for the future, and this is where even the best educated guesses become difficult.

“EDA traditionally has been an industry where big companies acquire small companies doing interesting things,” said Wally Rhines, chairman and CEO of Mentor, noting that markets that have shown strong growth include DFM, formal verification, ESL and power analysis. He said the next wave of electrical design challenges include low-power design at higher levels of abstraction, optimizing embedded software for power, in-circuit emulation, design for test, physical verification, stacked die verification, and system design that extends beyond the PCB.

That concern is echoed by Drew Wingard, chief technology officer at Sonics: “From an EDA perspective, the next layer up in the power hierarchy is how we convince ourselves that the hardware and software are working together correctly. This is a different protocol check than we normally do. You have dependencies, because you can’t turn off one until another turns off. The mix of hardware and software makes it difficult to prove what’s correct. Right now there is not even enough time to test the power management until the second spin.”

He noted that just trying to get software to turn on the power management features in a chip is a challenge. “The thermal/power reduction to be gained by turning on features already in a chip can be significant.”

One issue that almost certainly needs attention is derivative designs. Getting them out the door is painful, expensive, and time-consuming.

“A lot of engineering that’s being done is derivative engineering,” said Naveed Sherwani, president and CEO of Open-Silicon. “This is not something that EDA vendors focus on, but it’s something that’s definitely needed. What’s out there is a kluge of methodologies and flows. EDA so far has not woken up to this opportunity. They certainly listen to their customers, but they’re still not close enough. You have to do the work to understand it, and the revisions and changes that are needed are painful. A derivative is almost like a new project. There can be 1 million degrees of improvement here.”

Conclusions
All of this requires tools—notably more and new capabilities built into existing tools—as well as new tools that can integrate all of these pieces. But what gets addressed first is a difficult balance.

While chipmakers at the leading edge are used to developing some of their own tools, methodologies and dealing with poor yields, their existing development is running out of steam. That means moving forward at advanced nodes and in stacked configurations will require developing entirely new versions of tools, methodologies—an enormous expense by anyone’s calculations.

Qualcomm's proposed tech-tuning flow.

EDA vendors, meanwhile, have their work cut out for them just updating their existing tools, and they are cautious about massive investments in new areas that may not return dividends within an appropriate time frame—or within an immature supply chain when it comes to stacking of die.

“To get ROI back on tools of this complexity you need more than 20 customers,” said Mike Gianfagna, vice president of marketing at Atrenta. “That means you’re going to be negative on that investment for three or four years. So you really have to pick your battles, and small companies probably can’t do this at all.”

Gianfagna noted that for chipmakers the challenge is too many options. “You need a way to prune the solutions space fast. You have to figure out which architectures to choose quickly and which roads to pursue further. The real gap is not in the tech tuning. It’s coming up with the right architecture that supports meaningful decision-making.”

The question now is when the gaps that each side sees will merge, and when it will become profitable enough to take an investment risk.

By Ed Sperling
UMC certified Synopsys’ StarRC extraction tools for its 28nm PolySiON and high-k/metal gate processes. Synopsys also uncorked a new release of its Synplify FPGA synthesis tool, which it claims reduces runtime by up to 30% through better algorithms.

Open-Silicon rolled out version 6 of its Interlaken IP core, a high-speed chip-to-chip interface protocol that supports speeds of up to 600Gbps. The company also announced that it had integrated 25 Analog Bits IP cores into complex SoC designs. Those cores are aimed at a variety of vertical markets ranging from networking and telecom to storage and computing.

By Ed Sperling
System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), and Charlie Cheng, CEO of Kilopass.

SLD: SoCs have always been on the high end of the cost curve. Will that change as they become more mainstream?
Schirrmeister: There are FPGA SoCs, which may have a dual A9 subsystem on which you can run Linux. And you also have 4 million gates in the large version where you can put your own RTL into it. That’s what’s approaching the ASIC side. You can get it pre-defined and add your components in RTL into the programmable fabric. And that’s already integrated into the system level with virtual platforms and high-level synthesis. Those are making these designs accessible to different markets.
Cheng: There will not be generic SoCs replacing ASSPs. Cost is very high at the system level, and every integration point costs something. It’s hard to say a generic SoC has a place. Every SoC I know is slated for a specific market.

SLD: We start doing different tradeoffs as we move down the curve, right? Time to market is arguably as valuable as paying an extra dollar for a chip.
Janac: Mobility SoCs are selling in huge volumes. That will continue to grow. But they’re designed for a specific purpose. What we’re starting to see is people building FPGA co-processors that can manage the functionality of the SoC at a very low cost because they are in huge volumes and there are very big contracts that can drive the price down. They are using those co-processors to take the SoCs into markets that they were never intended for. The FPGA business is getting very interesting.

SLD: Does software change, as well? Do we move away from a general-purpose operating system, or do we still have a big operating system and many little ones?
Janac: Virtualization allows you to run multiple operating systems at once, invisible to the user and the application software.
Schirrmeister: I was at an automotive conference recently and one executive was talking about a hypervisor to switch between different operating systems even in the car. They’re looking at things like that. But if you look at some classic semiconductor companies making application processors, they’re starting to differentiate in software. Android democratizes everything, and then you add other software. The differentiation can be in hardware and software.
Zahiri: One area that hasn’t been tapped is software controlling the power. Our high-end customers are doing 50 to 100 power domains, mostly for mobile processors. We’re enabling people to design this way. And yet there’s not a significant way from a software point of view where, if you’re dialing your phone, another part of the chip should be shut down. There’s nothing software has done in a big way to control the power.
Janac: It’s a cultural problem. The software people don’t understand the hardware and they don’t want to use the APIs that are available. There is a gap. Computer science graduates want to write Java.
Schirrmeister: When engineers write their iPhone app for the hardware, there is one example where they ignored an API and it sucked the battery dry within an hour. Those are things that need to be validated. They’re an integration problem of hardware and software. I have seen software controlling power domains in the wireless world, though. There are power management ICs that can pull down areas of the processors and certain power areas to a lower voltage. That is software controlled. From my perspective, integration is a huge issue there at several levels. There is the software-hardware integration. There is the issue of verification that the application is running correctly on the chip, which has become so big at an advanced technology node. Then there is the subsystem integration and validation. It’s quite a challenge.

SLD: And from a verification standpoint, you’re never really done, right?
Schirrmeister: The designer has to be confident at the end of the day that it’s not the last thing he does in his career to tape out that chip.

SLD: As we move to 14nm and beyond, will we be involved with the chip at the same level or will it be more an integration of platforms?
Sherwani: We are already doing 14nm chips in development. I don’t see that happening. Our customers are willing to pay the money required, even though there will be fewer customers who do that. But even at 14nm there are still a whole bunch of companies doing chips. There are applications that need that.
Janac: But you do need more and more volume. At 90nm you needed about 100,000 units to break even. At 65nm you needed probably 6 million units. At 40nm, you needed between 10 million and 15 million units. At 28nm you need 50 million to 60 million. At 20nm you will need 100 million units. The markets to support those volumes are fewer and fewer, which is why I see the SoCs and 3D silicon will be prevalent in markets that don’t justify those very complicated deep-submicron dies.

SLD: But you may have a 14nm known good die that is part of that chip, right?
Janac: Yes, you become an assembler.
Sherwani: The other problem we see is that IP companies are not willing to warranty their IP. That’s one of the big problems of known good die. If I buy $5 million to $6 million in IP, one piece of IP out of 100 or 200 pieces that doesn’t work can force me to re-spin that chip. Yet, most IP vendors do not warranty their work. They are not willing to pay us a re-spin cost even if we can prove their IP is the problem. That means I have to go to a model where I can save myself from that problem, but at the same time Open-Silicon has to warranty the chip. That’s why we want to go to known good die. Once IP is proven in a piece of silicon I don’t want to re-integrate again and again. Every time I re-integrate it, I have a chance that I have missed a problem. The world is moving toward 3D kinds of chips that will allow us to address smaller markets but still have high volume for chips. The same chip will go into multiple 3D chips.

SLD: You basically define what a derivative chip is, right?
Sherwani: Yes.
Janac: About 25% of our revenue comes from being able to link die together inside a system in package. It becomes one of the key enablers. You don’t have to be part of the 28nm or 20nm problem because some things like analogs and modems don’t require it. You maintain Moore’s Law by stacking the die.

By Ed Sperling
System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), and Charlie Cheng, CEO of Kilopass.

SLD: Where will biggest challenges be at future nodes?
Schirrmeister: For us it’s the combination of hardware and software that gets interesting. You may have a network operator determines he wants coverage for the NFL on Sundays. That trickles through the design chain of what the network needs in terms of bandwidth and what the devices need to be able to process. As an EDA vendor, there are huge challenges for us because what used to be a small IP model has grown into a subsystem. People are building chips as an assembly of subsystems. The integration and the verification become a big issue at both the subsystem and the system level. There are lots of ways to grow.
Janac: I see things getting fragmented, concentrated and disintermediated. Nobody can afford to do everything themselves, so you wind up focusing on your core competencies. The people in those core competencies become more concentrated. The chip world also gets more concentrated because there won’t be many people who can afford to build a platform at 20nm. But the components for that platform are going to be disaggregated. Companies will have to outsource a big chunk of those designs and a lot of the tools they used to do themselves. So the little chip companies die. They will have a really tough time, particularly at the leading edge. The EDA industry has a lot of problems because it will be sharing the volume, which is going to explode, and it will be hurt by the fact that the number of projects will decline. You wind up with someone owning 80% of the processor market, someone owning 80% of the interconnects, and someone owning 80% of the memory. The DSPs get concentrated. Tools get concentrated, where someone owns place and route and someone owns simulation and ESL.

SLD: But you have to redefine what’s a chip company, don’t you? Are Open-Silicon and eSilicon chip companies?
Janac: Yes. And if I’m a small company I have to go to Open-Silicon or eSilicon because I can’t afford a staff of engineers to get a chip out.

SLD: But traditionally they were not considered chip companies.
Zahiri: They’re an aggregator of chip demand. Maybe eSilicon and Open-Silicon become the equivalent of midsize to large chip companies, aggregating the demand of the little companies that have to go to that model to be competitive and survive in the marketplace.
Sherwani: Along these lines, one of the challenges I see is that we’ve set up the market to expect 50% gross margins and 30% net margins. If your IP is coming from ARM and Kilopass and other companies, then how do you achieve those kinds of margins? You can’t. And if you can’t achieve those kinds of margins then you also have a business problem, and your business structure has to change. If you do everything in-house you’re not paying all the up-front fees to IP vendors. So first there is a problem of size. And second, even if you have the size there is a profitability problem with respect to the expectation that has been fed to Wall Street.
Janac: If your gross margin goes down, your operating margin has to improve, which means you can’t do enough R&D. So instead of using 25% of revenue for R&D you can only afford to do 10%. The PC guys are reasonably profitable at 25% margins because they don’t do any R&D. Intel does it. That’s why people are starting to outsource the IP. They can’t afford to do the R&D as the gross margin drops.
Sherwani: That’s one piece. But if you look at what’s going on in chip companies, the R&D budget goes down for IP, but it doesn’t go away. It goes into software. The number of software engineers is increasing. The market expectation still remains for hardware gross margins, but your expenses are going up.
Schirrmeister: You can’t just look at the chip in isolation. You have to look at it holistically. One large OEM says it’s losing money on every TV it sells. They have to get it back other ways. You can’t look at these things in isolation.
Janac: It gets back to the business model. If you don’t have a good business model and you just keep squeezing the margins then you’ll go out of business. But there are people who have innovative business models, like Amazon and Apple, that can afford to sell the hardware at cost.
Cheng: Worrying about margins and R&D is like worrying about the 120 companies that went out of business selling cars. As businesses mature, the technology content gets very high and it costs a lot. It’s not that companies don’t have good gross margins. There are a lot of companies with margins of 60% or more. But the ones that assemble IP and add 10% original content are not going to be very successful if they don’t differentiate, and they won’t be good customers long-term for the EDA vendors because 70% of those chips are memory and another 20% are IP that’s licensed from the outside. So they may only be doing 10% of the chip. This is why EDA revenue has been flat. If you look at the surviving car companies, they’ve been very profitable over time because there’s a high barrier to entry and it’s a fixed market.

SLD: But more pieces have to go together into something that’s coherent, and that’s more difficult than ever before, right?
Janac: I just met with a customer that spent $500 million on their platform and they have 180 IPs. They still make most of those IPs themselves, but integration is the issue.
Cheng: Integration isn’t any worse today than in the past.
Janac: It’s absolutely worse. And the reason is that you have an incredible amount of computing in smartphones, and that’s even trivial compared to what it’s going to be. You can’t afford to keep that device turned on except at times when you need it. One of the complexities of 20nm and 14nm is that you need a portion of the chip to do its job and then you shut it down. From a power perspective, you can’t afford to keep it on. And you don’t want it to be big, so you can’t afford a huge battery. It is very complex. You have frequency domains, power domains, power regions. You have as many as seven modems—WiFi, Bluetooth, CDMA, GSM and LTE.
Schirrmeister: What customers are telling us is that getting to an acceptable confidence level in verification is a very difficult thing, driven by the integration of all the components they have. Given that you’re taping out a chip and you can’t make a change tomorrow—that’s the pivotal point where you have to have enough confidence. The integration challenges are huge.

SLD: The promise of stacked die is that if you have a base platform you can start shifting into vertical markets quickly because a lot of the integration is already done, right?
Janac: Yes. The application processors that are being made for phones can be shifted into dashboard control, automotive infotainment and home gateways. What’s also going to happen is that the low end of the SoC market is going to disappear because the costs are too high. You’ll get 3D silicon, where people are selling dies with specific functionality on trailing-edge processes. You’ll wind up with FPGA SoCs.
Sherwani: But that’s a good thing. You could build viable chip companies that are on trailing processes with known good die that we can put into 3D stacks. You don’t have to push them all the way to 22nm. There’s no need for that. A lot of people will stay on 65nm, and that will justify keeping those fabs alive for a long time. It actually helps with the overall investment we need to put into 14nm.

SLD: Are the specialty fabs that are coming online capable of doing all this integration work?
Sherwani: They don’t need to. The interposer technology we have today doesn’t have to be much better. At 22nm you’ll see many people bringing 3D chips buying known good die from a bunch of people and putting these MCM-style 3D chips together. That will lead to many companies, which we consider sub-optimal today, becoming viable. And I don’t think these small SoC companies will disappear. They will start doing specialty silicon.
Janac: They will be the known-good-die companies.
Sherwani: Yes. They will be working with GlobalFoundries and TSMC at 65nm. They don’t have to run at 1.2GHz. They can run at 300MHz and be just fine. And you don’t have this area constraint. So area constraints and power constraints can be reduced. Today you have one chip and something that is 1.2GHz can run fine at 100MHz. Not everything is being pushed to that level.
Janac: And then you’re moving from 2D integration to 3D integration. That opens up a whole bunch of opportunities that are untapped today.
Sherwani: Just because of 3D, there are huge opportunities. I also think that IC design and computing will completely change if we can change the memory. The idea in the past was to dumb down the memory because you could pull the gross margin into the microprocessor. After 25 years of dumbing down the memory we do have standard interfaces, but memory isn’t doing much. When you look at 3D memory, it has 20X the performance of DDR3. It is one-sixth the power and one-tenth the space of DDR memory. A new era of intelligent memory will do a lot more than just keeping the bits. It will become very close to the processor, which changes the processor design. And many new applications are possible. If the architecture changes and memory and processors are very close together, many new things can happen. That is what you will see in the next five to seven years. You will be able to put terabit memories on top of processors in the same 3D package.

By Ed Sperling
The monolithic ASIC, which has been the bread-and-butter of chipmakers for decades, is giving way to systems on a chip among mainstream chipmakers and at mainstream process nodes.

This shift has been overhyped, overpromised and slow to materialize. While SoCs have been common for years in mobile electronics and for high-performance platforms such as gaming consoles, they have always been more expensive to design and manufacture. But at 40nm and beyond—and increasingly even at 65nm and 90nm—physics, an increasing amount of software and the inclusion of more third-party IP are forcing changes in best practices for designing chips. And as the industry heads into 2.5D stacking over the next couple years, subsystems that can be part of systems in package will add even great emphasis, as well as some new wrinkles, to the shift.

“It’s happening now and it will continue to happen,” said Tom Lantsch, executive vice president of corporate development at ARM. “We’re seeing application processors that are heterogeneous multicore on the same chip with graphics engines and video engines and they’re now running Symbian instructions. A lot of this shift is based on power. There’s a realization that you can do things other ways more efficiently.”

So what exactly is the difference between an SoC and an ASIC? The common definition is that an SoC includes one or more processors plus software and peripherals, making it a complete system rather than a ASIC, which is suited for a very specific task.

“The ASIC customer used to be the system house,” said Hans Bouwmeester, director of IP at Open-Silicon. “But now the system houses and fabless semiconductor companies are focusing on horizon tasks. It’s not divided by front end and back end anymore. It’s horizontal and vertical, which is re-use or availability of IP and competence. If you look at ARM’s chips, they’re applicable across multiple domains and customers are willing to outsource that development to them.”

This shift hasn’t been lost on Open-Silicon or eSilicon, both of which are shifting from an ASIC to an SoC approach. And both say the SoC world will explode once the once the industry begins adopting 2.5D stacking over the next couple years—a move that also may include more emphasis on FPGA platforms as part of the 2.5D stack.

Partition issues
At least part of what an SoC brings to the design table is flexibility. There is an ability to try different things, and at each new process node more room to experiment. But silicon is never free, even if it is available. Shrinking feature sizes creates its own set of problems at each new process node.

The typical method of deal with these problems is a “divide and conquer” approach. If there are 500 blocks, those blocks can be aggregated according to function, shared resources, or some other scheme. But in an SoC, finding the right line on which to base that partitioning is more difficult. Even worse, it can change, depending upon which market a chip will serve.

“If you do a flat design you always get the best quality,” said Sudhaker Jilla, product marketing director at Mentor Graphics. “But as the chip grows the runtime becomes unbearable. It can go from hours to more than a week. The alternative is to use a hierarchical approach, but then you have a problem of performance. You want the turnaround time of a hierarchical flow, but the quality of a flat one.”

The reality is both are needed for SoCs, but that also means a significant learning curve for the design teams. They need to learn new tools, figure out how to partition their designs—whether it’s by blocks, geography, or IP.

“The key is that companies need to figure out how to divide and conquer,” said Jilla. “Will it be dual-core or quad-core? Or will it be multiple different cores?”

More tools, more IP
For EDA and IP vendors, this is only good news. Selling to the biggest chipmakers has always been lucrative, but continuing to sell to those same customers while also adding incremental business is a big win. FPGA tools have been sufficient, for example, to do basic layout and verification, but put that same FPGA into an SoC or a stacked die configuration, add software and third-party IP, and then try to integrate it all together and the complexity easily outpaces what the typical FPGA tool can do.

“The biggest trend is that people are spending 35% to 40% of their effort writing software,” said John Koeter, vice president of marketing for Synopsys’ solutions group. “When you get down to 28nm or 20nm, companies are spending more than 50% of the time to market developing software. If you look at an SoC today, it’s usually two to four host CPUs, two to four GPUs, and it’s increasingly heterogeneous.”

He said that opens up huge opportunities for linking software to hardware, and virtualizing the hardware and software. It also opens up opportunities for IP, tools to help integrate that IP, exploratory tools that can show the tradeoffs at the architectural stage, and a suite of verification tools and verification IP.

“Just from a verification standpoint you’ve got to tackle this at several levels,” said Pete Heller, senior product line manager at Cadence. “You’ve got to look at it from the subsystem and block level for functional reasons. And you’ve got to look at the full SoC and pump real data through the system so you can get as much real-life validation as you can. Then there’s a third level, which is to put it into the hands of 100,000 people and let them be the guinea pigs after you’ve already worked out all the bugs you can.”

What is a subsystem?
That leads to the next phase of this whole development scheme—fully integrated and tested subsystems, which are expected to begin hitting the market over the next year in preparation of more SoCs and 2.5D stacked die.

“If you look back 10 years when Gartner was tracking design starts, in 2000 there were about 20,000 chip designs a year,” said Drew Wingard, CTO at Sonics. “Now we’re seeing more SoCs because you have processors sprinkled around the chip that may or may not even show up in the bill of materials and that you may or may not have access to.”

Increasingly, those pieces will be combined into fully integrated systems that include IP, possibly processors, and perhaps even shared resources such as memory with standardized interfaces. That approach will become particularly useful when chips can be stacked, either in 2.5D or 3D, and it will completely render the number of design starts meaningless. There will be more design starts, but the final outcome may be subsystems rather than chips—or chips that are part of a stack rather than the fully integrated stack itself.

“A general-purpose processor may not be the most efficient way to accomplish a task,” said Wingard. “This has led to a huge discussion around subsystems. Not everyone believes each function needs a processor. But how independent is a subsystem going to be? You can quickly get into a situation where you have enough performance most of the time, but there may be specific and critical sequences where you don’t have enough.”

There has been a lot of talk about subsystems across the industry lately, and companies are positioning themselves to take advantage of this shift. But the challenges of making this all work are huge.

“This is similar to the challenge embedded companies have faced for a long time,” said Simon Butler, CEO of Methodics. “It’s one thing if you’re dealing with a homogeneous environment where the tools talk together. But when you have to bring all these different pieces together and make sure all the parts are aligned, it’s going to be very difficult.”

Past, present and future
Still, the road to SoCs has been set and it’s gaining momentum. That became very obvious at the Consumer Electronics Show over the past couple of years.

“What’s changed is the user experience is now a combination of hardware and software,” said Mike Gianfagna, vice president of marketing at Atrenta. “We’re seeing the consumerization of electronics. The idea isn’t new. Joe Costello was talking about this a decade ago. But it’s finally happening. The semiconductor content is enabling the user experience.”

That will only increase as future designs allow more choices of IP, software, processors and ultimately subsystems on a chip—and more intelligent tradeoffs to make it all work faster and cheaper while using less energy.

By Ed Sperling
System-Level Design sat down to talk about design at future process nodes with Naveed Sherwani, president and CEO of Open-Silicon; Charles Janac, chairman and CEO of Arteris; Frank Schirrmeister, group director of product marketing for Cadence’s System Development Suite; Behrooz, Zahiri, vice president of marketing at Magma (and currently director of marketing at Synopsys), and Charlie Cheng, CEO of Kilopass.

SLD: As we move to 28nm and below, what will we have to do differently than in the past?
Sherwani: We see issues at the system level. One involves 3D chips (stacked die). How do you actually put these together? Memory already has gone 3D. Electrical, physical and mechanical tools, both on the simulation and analysis sides, are not that sophisticated. Most of that work is being done manually today. Second, we have several customers that have come to us and asked us to put two or three chips together at 22nm. The science to combine the chips is not well known. This exercise is costing more than if it had been done from scratch. You should be able to do this very quickly. We don’t have tools like that, so we will have to develop them. A third area is that we see our design teams growing, but our verification is growing super-linearly. Right now verification teams are almost 3x the time of other teams. That is not sustainable.
Schirrmeister: Somewhere around 40nm software became more dominant. It passed the effort needed for hardware. How do you create for this vast mass of available space new things to differentiate your chip? And how do you integrate all of these pieces together? The whole integration and verification in the context of the software and the hardware together is the big challenge.

SLD: Does that software include just just the drivers, or is it more?
Schirrmeister: It goes all the way up to the application level. The more enabling hardware you have, the higher up to the software you reach because you need to partition which component runs, which processor it uses. There are different layers from the very low-level bare metal to applications that may be split across different processors.

SLD: Let’s go back to the original question. What challenges are ahead?
Janac: One of the things we’re trying to do is to bring computing closer to the person. It’s going from the mainframe to PC to smartphone, which will be the new personal computer. What people are trying to do is build things of frightening complexity into something as small as a smartphone and with the functionality of a PC. They’re not quite there yet, but they’ll get there. At 28nm, we’ve got power domains, frequency domains, disparate pieces of IP on disparate chips, and we’re trying to re-use software. You have to make all of that work together. That’s one of the biggest challenges. You have IP with different protocols and sources. There are requirements that looked like science fiction a few years ago. And you have to make it all work. It’s a very big challenge and it’s very costly. Some of these things cost hundreds of millions of dollars to build.
Cheng: Integration of software and miniaturization are a challenge we’ve been dealing with over the past three decades. It’s not just 28nm that’s the problem. But what 28nm does bring is very different packaging, which drives the silicon decision, as well as confusion in transistors. That will cost the industry $10 billion to $30 billion. The reason is that 28nm is supposed to be the generation of high k/metal gate. I’m not sure that’s going to happen. TSMC has re-introduced bulk silicon with no metal gates. The question is do you want to take a chance on bulk silicon and save 30% in cost, or go with high k/metal gate that will be more expensive but may not work. That’s a lot of money for an experiment.
Zahiri: Design costs are rising. With 28nm, you’re spending 20% or so more than what we spent in the past. Semiconductors are not growing at that pace. Something has to give. So chipmakers will go in two directions. One is to figure out how to use the same resources and the same schedule and the same number of people to get these 28nm chips out, which are more complex and much bigger. Those that can’t do that will go away. So 28nm, and especially 20nm, will be the test to see which companies will re-tool, re-position and re-architect to take advantage of this real estate. We’re trying to understand which companies will survive and how we can help them.

SLD: We’re talking about complexity and convergence, as well as business issues. As they become more entangled, do we have to rethink everything?
Schirrmeister: According to IBS, at 28nm the price of fab construction is $3 billion; process R&D is $1.2 billion R&D; the design cost is $50 million to $90 million and each mask set is $2 million to $3 million. For 22nm/20nm, fab construction is $4 billion to $7 billion; process R&D is $2.1 billion to $3 billion; design cost is $120 million to $500 million, and a mask set costs $5 million to $8 million. As an EDA vendor, our investment is huge, as well. What you will see, more and more, is the whole notion of collaborative design. It’s hard to do it all by yourself. The business dynamic behind this is becoming very interesting for who can afford to do a design.

SLD: So who can afford to do a design?
Janac: The business models and technology are getting intertwined. There are a bunch of people getting squeezed in a traditional business model, where they have to do more and more to save a lot of money, and their margins are suffering. Their R&D footprints are expanding and they’re trying to fight that with outside IP and more efficient EDA tools. But you also have companies like Apple and Amazon, where they don’t care what the cost of silicon is. They make money in different ways. The silicon is an enabler, and they can afford to make chips that are 50% bigger or to give away their tablets at cost because they have a different business model that supports that silicon effort.

SLD: Can the industry survive on four or five of these large companies?
Janac: One of the key issues will be access to silicon. Where it starts to get problematic is, at some point, even though you have this business model you have to make silicon. So what fabs are able to give you that cost advantage? There are starting to be fewer and fewer of them. As you go to 28nm, you only have a choice of a few players. You have TSMC and GlobalFoundries, plus Samsung and Intel, and then some smaller players on the periphery like ST and Panasonic.
Sherwani: That’s a good point. At 14nm, who are the players going to be? You can basically say it will be four players.

SLD: And what will they be building? Will it be platforms for a stacked die, or just their own chips?
Sherwani: These guys cannot afford to have fabs and make chips just for themselves. That model won’t work. Even Intel is being forced to revisit that model, which is why they’ve got a custom foundry. They’re projecting a need for five to seven years out. Intel is one of the biggest producers of silicon on the planet, and even they are forced to think like that. What will emerge is that people will move more and more toward platforms, with software as a differentiator rather than hardware. So if you look out four years, you may have a home gateway that is a standardized platform with a processor core and I/O chips and some custom silicon, and then a huge software investment that differentiates one platform from another. The hardware differentiation will be less. There will be some custom hardware, but that may only account for 10% or 15% of the hardware. That will be a platform you can get from a few suppliers working with these foundries. That’s how you cut down the costs. You don’t do those kinds of chips. We see a lot of chips, but there isn’t much difference between them. There may be six or seven chips that are essentially the same.
Schirrmeister: If you look at ITRS (International Technology Roadmap for Semiconductors) data, they already have characterized the design challenges in those platforms. There is a networking platform, which is essentially a bunch of packet processing engines with a smart interconnect. There is a stationary platform, which is a compute platform where you have the embarrassingly parallel portion that plugs into a wall outlet. And then there is a mobile platform, where you try to distribute software across different cores. There is a lot of similarity in how the chips are structured at the block level. But there also are a lot of challenges for how IP providers get their design ready for 28nm and beyond, how to integrate all of that. Some of the integration challenges are very complex. And the software on top of that is very difficult to create.

SLD: Where do the tools vendors see their future?
Sherwani: Once the platform is stable, you can always have disruptions. There are very few of those disruptions, though. When Android becomes stable, phones will look very much the same. Then someone will invent a new generation of phones, and until that stabilizes a lot of innovation will happen.
Zahiri: As EDA vendors, we are trying to intercept that innovation. We don’t see the world as just software or hardware. It’s a combination of both. But more important, we see that we are moving this forward. Whether it’s graphics or something that will allow a battery to last two days instead of a day, or whether it’s just making our industry more productive, the consumer market will remain demanding. We are trying to figure out the ways to meet that need and facilitate innovation.