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Posts Tagged ‘OVM’

Yikes! Why Is My SystemVerilog Testbench So Slooooow?

Thursday, August 23rd, 2012

It turns out that SystemVerilog != Verilog. OK, we all figured that out a few years ago as we started to build verification environments using IEEE 1800 SystemVerilog. While it did add design features like new ways to interface code, it also had verification features like classes, dynamic data types, and randomization that have no analog (pardon the pun) in the IEEE 1364 Verilog language. But the syntax was a reasonable extension, many more designs needed advanced verification, and we had the Open Verification Methodology (OVM) followed by the standardized Accellera Systems Initiative Universal Verification Methodology (UVM) so thousands of engineers got trained on object-oriented programming. Architectures were created, templates were followed, and the verification IP components were built. Then they were integrated and the simulation speed took a nose dive. Yikes, why did that happen?

To view this white paper, click here.

Comprehensive UVM/OVM Acceleration

Thursday, October 20th, 2011

Today’s traditional design flow involves design at multiple levels of abstraction. As the design implementation is refined and the verification vehicle changes, the testbench needs to adjust to abstractions from transaction-level simulation, and RTL simulation to hardware acceleration. But the challenge is that separate verification components, testbenches, tests, and plans are developed by separate teams at different abstraction levels. This requires more expertise to learn and understand, more code to develop and maintain, and larger teams to fund and manage.

This white paper describes a consistent and comprehensive Universal Verification Methodology (UVM)/ Open Verification Methodology (OVM) that prescribes substantial reuse across multiple levels of abstraction and facilitates a metric-driven verification (MDV) flow. While this document focuses on UVM/OVM acceleration, it also touches on other abstraction levels, such as transaction-level modeling (TLM).

To download this paper, click here.

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