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Posts Tagged ‘packaging’

More space for satellites and a roadmap for data protection

Monday, February 12th, 2018

Blog Review – Monday, February 12, 2018
This week’s selection includes 100G Ethernet for data centers; Satellites will vie for space; A roadmap for data protection, and more from the blogsphere

The rise of data centers and increase in cloud-based computing has prompted Lance Looper, Silicon Labs, to examine how wireless networks are changing to meet the demands for performance and low latency and implementing 100G Ethernet.

https://www.silabs.com/community/blog.entry.html/2018/02/05/ethernet_s_role_inh-pTeJ

Marveling at how connectivity has ‘shrunk’ the world, Paolo Colombo, ANSYS, looks skywards to consider the growth of connected devices. He looks at the role of space satellites and how small satellites will have their day for critical applications and introduces ‘pseudo sats’ which are vying for space in space.

An article about medical device design and manufacturing challenges has prompted Roger Mazzella, QT, to address each and provide a response to reassure developers. Naturally, QT’s products play a role in allaying many fears, but it is an interesting insight into the medical design arena.

An interesting case study is recorded by Hellen Norman, Arm, featuring Scratchy the robot. She asks German embedded systems developer, Sebastian Förster how he used a Cortex-M4, some motors, Lego bricks and cable ties to create a four-legged robot, programmed to walk using artificial intelligence (AI).

It’s not unusual to feel bewildered at a technology conference, so we can sympathise with Thomas Hackett, Cadence, who has a twist on the usual philosophical question of “What am I here for?” A walk through DesignCon caused a lightbulb moment, illuminating the real world interplay of IP, SoC and packaging.

With the IoT there are no secrets, and Robert Vamosi, Synopsys examines how data sharing may not be as innocuous as companies would have us believe, if it is not configured flawlessly. The Strava heatmap which reveals secret military locations has thrown up some serious issues which, we are assured, are being addressed, and which Vamosi sees as a model for other IoT and wearable device manufacturers.

Tackling software-defined networking (SDN) head-on, Jean-Marie Brunet, Mentor Graphics, presents a clear and strong case for accelerating verification using virtual emulation. Of course he advocates Veloce VirtuaLAB PCIe for the task, but backs up his recommendation with some sound reasoning and guidance.

By Caroline Hayes, Senior Editor

Blog Review – Monday, December 11, 2017

Sunday, December 10th, 2017

Looking through the blogshphere, we find packaging issues ahead of the holidays; Life on the IoT edge; billions of connected devices – what does it even mean? and taking nature’s lead in 3D printing

According to Paul McLellan, Cadence, Moore’s Law is running out of steam. He spoke to John Park about advanced packaging and heterogeneous integration.

Living life on the edge, Jeff Miller, Mentor Graphics, sets out a step program for IoT design and advocates a standardized directory structure.

Anticipating one trillion smart, connected devices, Christine Young, Maxim Integrated, looks to the future and what the predicted scale of connectivity will mean for intelligence gathering and sharing, and their role in emerging technologies, such as blockchain.

Taking a cue from nature’s own materials, Scott Goodrich, Fortify guest blogs for ANSYS to explain how magnetic fields were used in 3D printing to align fibers for high strength-to-weight ratio printed parts.

Consumer trends that signal the end of wired audio connections has set Mark Melvin, ON Semiconductor, thinking about hearing aids and adding intelligence via wireless connectivity with smartphones.

Trends for the semiconductor chip market are discussed by John Blyler and Jim Feldan, Semico Research. The complexity is increasing which could impact the number of design starts. One trend is IP reuse and this informative report looks into the facts and figures in great detail to provide an understanding of the industry direction.

By Caroline Hayes, Senior Editor

Blog Review – Monday, August 31, 2015

Monday, August 31st, 2015

HPC for cancer analysis; body power: game on for animation; DDR challenges; aviation fascination; packaging checks; Arrow explains USB3.1; IDF meets IoT

It would take 5.6Exabytes to synchronize the data of the 14million cancer patients worldwide, just once, points out Kristina Kermanshahche, Intel. She explains how Intel’s HPC is a helping scientist access and share data, with relationships such as Pan-Cancer Analysis of Whole Genomes, and at the German Cancer Research Centre (DKFZ) and the European Molecular Biology Laboratory (EMBL).

Distasteful things like a body’s sweat could charge phones, speculates Catherine Blogar, Dassault Sytemes. She speaks to some experts in wearable and implantable engineering for some futuristic power advice.

Some helpful tips on creating animation is offered by Laura Mengot, ARM, in her blog. Although the software used is Autodesk Maya and Unity, Mengot says that the detailed, illustrated theories are applicable to any 3D engine and game engine.

Ely Tsern, Rambus, identifies five trends in server memory and speculates on DDR4 capability in particular, and even beyond to DDR5.

Welcoming the RTCA/DO-254 (Design Assurance Guidance For Airborne Electronic Hardware) standard, Graham Bell, Real Intent, delves into what it means for verification tools.

Reminiscing about a European design classic, Nazita Save, Mentor Graphics, remembers Concorde. Pre-CAD modification and with no CFD software, how did they do it?

While end users may love smaller package sizes, they are a headache for manufacturers. IC Packaging Pros, Cadence, discuss layout tools for validating and verifying, with some easy-to-follow advice.

Four bloggers contribute to the latest update to USB3.0. Anand Shirahatti, Thejus Shanbhogue, Kanak Singh, Deepak Nagaria, Arrow, discuss the implementation and verification challenges – with a link to a USB3.0 vs USB3.1 USB cheat sheet thrown in.

Richard Solomon appears confused as to what day it is, but makes up for it with a round up of what’s what at this year’s IDF, from characters encountered, travel tips to his own takeaways from this month’s event in San Francisco.

System Design Enablement – Looking Beyond the Chip

Thursday, July 23rd, 2015

By Craig Cochran, VP Corporate Marketing Cadence

Rapid changes are occurring in the way electronic products are developed. Driven by increasing integration and complexity, a growing number of systems companies are assuming more control over hardware, software, and mechanical development. Semiconductor makers are dealing not only with the physics of advanced process nodes, but are also expected to provide much of the embedded software for each system on chip (SoC). It’s time for the EDA industry to expand its focus beyond hardware IC design and to embrace System Design Enablement (SDE), an expanded mission that will provide tools, design content, and services for the development of whole systems or end products.

Until very recently, most electronic products were created from the bottom-up by isolated groups of developers with minimal interaction. This was true across intellectual property (IP), semiconductor, software, foundry, packaging, and systems companies. The complexity of modern-day systems, the compression of development timelines, and the pressure for product differentiation make this kind of development unfeasible, driving a shift towards the integrated design efforts we’re seeing from system companies.

While semiconductors are at the heart of any electronic system, there is much more to consider. In many electronic systems, software represents the greatest cost and biggest bottleneck.  Thermal and power restrictions apply across the chip, package, and board. Form factor and user experience impact mechanical design. Every part of the resulting system is interrelated and must be optimized concurrently to produce a leading product.

For many years, the EDA industry has focused on delivering tools to semiconductor companies to enable chip design. We call this “core” EDA, and it will remain a vital technology. With an eye to the future, successful core EDA companies will move up to system design with SDE. As shown below, SDE calls for the convergence of electrical, software, and mechanical domains, and its outcome is not just a chip but an end product.

Vertical Aggregation and Disaggregation Drive SDE

There was a time when chip design was confined to large companies with the capability to fabricate chips. Now we are in an era of fabless semiconductor companies and pure-play foundries, and as a result, hundreds of companies are engaged in IC and/or IP design. This has enabled a tremendous wave of innovation and creativity, but it has also resulted in a disaggregated product design chain.

Today, some systems companies across a variety of vertical markets are choosing to re-aggregate (albeit without chip manufacturing), with the end goal of ensuring a high-value product. For example, some of the world’s largest systems companies have created in-house chip design teams. These vertically integrated systems companies form a natural market for SDE tools and flows.

Meanwhile, semiconductors are representing a larger part of the overall value of the end products. This is one reason why systems companies are adding semiconductor design capability to their engineering teams. And systems companies expect that their semiconductor suppliers, be they in-house design groups or third parties, provide much of the software stack including drivers, OS, and middleware.

Tooling and IP for SDE

Embedded software development traditionally begins very late in the overall cycle, thereby becoming the critical path to product shipment. Hence there’s an urgent need to “shift left” and allow embedded software development and hardware/software verification to begin much earlier. SDE tools and flows support this added software responsibility by providing a continuum of pre-silicon development platforms that support hardware/software co-design and co-verification, virtual platforms, emulation, simulation, and FPGA-based prototyping.

Other tools and capabilities that support SDE include multi-fabric power, thermal, and signal integrity analysis; chip/package/PCB co-design; incremental co-design between EDA and Mechanical CAD (MCAD) tools; design of MEMS devices within custom/analog IC flows; and the development of 2.5D and 3D IC packages. All these capabilities are available today.

System Design Enablement is not just about design tools – it requires design content as well. At the chip level, that content is increasingly provided by reusable semiconductor IP blocks. Today as much as 80% of an SoC may be composed of such blocks, which may include processors, memory, communications protocols, analog functions, and verification IP (VIP).

Conclusion

As system complexity grows, the various components of an electronic system can no longer be designed in isolation. The focus of EDA needs to expand from single chips and boards to entire systems. This new challenge is addressed by System Design Enablement, and it requires tools, IP, software content, and services aimed at making whole systems possible. SDE opens a new chapter in the history of electronic system design, and it will greatly expand the reach of EDA technology to meet the challenges of today’s vertically integrated companies and their highly differentiated designs.

Craig Cochran is the vice president of corporate marketing at Cadence Design Systems, Inc. He has more than 20 years of corporate, strategic and product marketing expertise at EDA and electronics companies including Real Intent, ChipVision Design Systems, Jasper Design Automation and Synopsys. He began his career as an applications engineer at Valid Logic Systems and a digital design engineer at General Electric. Cochran holds a bachelor of science degree cum laude in electrical engineering from the Georgia Institute of Technology.

Experts Share Unique Challenges in Wearable Designs

Monday, April 28th, 2014

By John Blyler, Chief Content Officer

Wearable devices will add a new twist to traditional embedded designs according to experts from ARM, Freescale, HillCrest Labs, STMicr, Imec and Koinix.

Wearable technology design presents challenges different from other embedded markets. To understand these challenges, “System Design Engineering” talked with James Bruce, Director Mobile Solutions for ARM; Mike Stanley, Systems Engineer at Freescale; Daniel Chaitow, Marketing Communications Manager at Hillcrest Labs; Jay Esfandyari, Director of Global Product Marketing at STMicroelectronics; Siebren Schaafsma, Team Leader at Holst Centre and Imec, and; Thea Rejman, Financial Analyst at Kionix, Inc. What follows is a portion of that conversation. – JB

System Design Engineering: What unique technical challenges are designers facing in the wearable smart connected market – as opposed to other markets?

Bruce: The big challenge for wearable designers is that the use cases are still very new.  There is a lot of innovation and diversity taking place. People are trying out many different operational scenarios. Designers need low power processors that are right for these evolving workloads. One of the benefits is that there is a strong ecosystem with a large number of system-on-chip (SoC) available to developers to create initial wearable solutions. Once they have taken the initial designs to market, they can stay with it, use a different SOC, or even customize it.

Another key consideration for designers is improving quality of sensor data integrated into the device, which have traditionally been not in the domain of digital designers. Traditional digital designers need to worry about the analog portions of a wearable device, i.e., accelerometers, gyros, humidity sensors, etc as there are several choices of sensor fusion solutions for low power application processors available off-the-shelf.

Stanley:  Managing power consumption and communications are currently the two largest hurdles for wearable hardware. Looking ahead to truly wearable sensors that can be embedded into clothing, athletic equipments, name badges, etc., means that every component in the system must become even smaller and thinner.  This drives the trend of consolidating multiple sensors into one package, and then shrinking that combo sensor even more. Chip scale packaging will be replacing QFN and LGA for many applications.  This requires close cooperation across all disciplines as the traditional package disappears.

Low power, wireless communications and small form factor are keys to driving IoT applications. In many ways, these are closely related to some wearable applications in that they use similar sensors and common software libraries for communication, data abstraction and signature recognition.

Chaitow: The challenges of timing, power, availability, and security are similar to but different from the typical embedded design problem.  Perhaps the main difference is that, instead of a single circuit board or chip to worry about, the designer must consider the whole system.  This adds network and systems engineering problems to the job of a typical embedded design engineer.  It’s one thing to optimize the power and security of a single device; it’s totally different to do that across a various set of devices in a variable network.  Then add in the fact that the number of devices or versions of the devices might change in a given network over time and the design problem gets even bigger.

An additional unique challenge is the need for calibration of sensors. MEMS sensors used in commercial products have variable performance. This variable performance is true both at the point of manufacture and over the lifetime of the product, as each sensor reacts differently to changes in environmental factors such as temperature, voltage, interference, and sensor aging, to name just a few. These variations make calibration essential for sensor-based products.

Esfandyari: Wearable-device requirements are currently driving significant changes in the MEMS industry. They are driving the development of even smaller components with even lower power consumption but with more embedded features. To satisfy these needs, sensor manufacturers are creating highly integrated devices with multiple sensors (e.g., accelerometer, gyroscope and magnetometer) embedded in a single package.

Finally, from a design perspective, wearable-device manufacturers must be very careful with the appearance of their product because many people are conscious of their appearance and would prefer not to wear accessories that make them look strange. The challenge is to make wearable technology “invisible” to the final user and the external world.

Various implementations of systems that moni-tor activity of the human body. (Courtesy of Imec)

Siebren: An important part of wearable technology will be in the design of body area networks (BANs) – a collection of miniature sensor and actuator nodes. Such devices will require innovative solutions to remove the critical technological obstacles such as shrinking form factors that require new integration and packaging technology. Battery capacities will need to be extended. Indeed, the energy consumption of all building blocks will need to be drastically reduced to allow energy autonomy. System design will have to focus on overall system power consumption where trade-offs have to be made between security, privacy, precision, availability and storage of the data. For example a high power streaming mode over radio of high resolution, medical grade ECG data in case of an emergency compared to average heart rate monitoring once a minute in the low power mode.

Rejman: Stringent power requirements drive the majority of sensor applications in the wearables market. Therefore, it is essential that both the sensors and the software are low power.  Designers should look for a sensor fusion solution that offers embedded power management functionality to help manage sensor interaction and data processing with minimal overhead, resulting in lower power and better performance.

System Design Engineering: Thank you.

From SEMICON West 2013: Luc Van den hove of imec

Wednesday, August 14th, 2013
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John Blyler interviews Luc Van den hove, CEO of imec.


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