Part of the  

Chip Design Magazine

  Network

About  |  Contact

Posts Tagged ‘PCB’

Blog Review – Monday, June 12, 2017

Monday, June 12th, 2017

This week, we find traffic systems for drones and answers to the questions ‘What’s the difference between safe and secure?’ and ‘Can you hear voice control calling?’

An interesting foray into semantics is conducted by Andrew Hopkins, ARM, as he looks at what makes a system secure and what makes a system safe and can the two adjectives be interchanged in terms of SoC design? (With a little plug for ARM at DAC later this month.)

It had to happen, a traffic system designed to restore order to the skies as commercial drones increase in number. Ken Kaplan, Intel, looks at what NASA scientists and technology leaders have come up with to make sense of the skies.

Voice control is ready to bring voice automation to the smart home, says Kjetil Holstad, Nordic Semiconductor. He highlights a fine line of voice-activation’s predecessors and looks to the future with context-awareness.

More word play, this time from Tom De Schutter, Synopsys, who discusses verification and validation and their role in prototyping.

Tackling two big announcements from Mentor Graphics, Mike Santarini, looks at the establishment of the outsourced assembly and test (OSAT) Alliance program, and the company’s Xpedition high-density advanced packaging (HDAP) flow. He educates without patronizing on why the latter in particular is good news for fabless companies and where it fits in the company’s suite of tools. He also manages to flag up technical sessions on the topic at next month’s DAC.

Reporting from IoT DevCon, Christine Young, Maxim Integrated, highlights the theme of security in a connected world. She reviews the presentation “Shifting the IoT Mindset from Security to Trust,” by Bill Diotte, CEO of Mocana, and In “Zero-Touch Device Onboarding for IoT,” by Jennifer Gilburg, director of strategy, Internet of Things Identity at Intel. She explores a lot of the pitfalls and perils with problem-solving.

Anticipating a revolution in transportation, Alyssa, Dassault Systemes, previews this week’s Movin’On in Montreal, Canada, with an interview with colleague and keynote speaker, Guillaume Gerondeau, Senior Director Transportation and Mobility Asia. He looks at how smart mobility will impact cities and how 3D virtual tools can make the changes accessible and acceptable.

Caroline Hayes, Senior Editor

System Design Enablement – Looking Beyond the Chip

Thursday, July 23rd, 2015

By Craig Cochran, VP Corporate Marketing Cadence

Rapid changes are occurring in the way electronic products are developed. Driven by increasing integration and complexity, a growing number of systems companies are assuming more control over hardware, software, and mechanical development. Semiconductor makers are dealing not only with the physics of advanced process nodes, but are also expected to provide much of the embedded software for each system on chip (SoC). It’s time for the EDA industry to expand its focus beyond hardware IC design and to embrace System Design Enablement (SDE), an expanded mission that will provide tools, design content, and services for the development of whole systems or end products.

Until very recently, most electronic products were created from the bottom-up by isolated groups of developers with minimal interaction. This was true across intellectual property (IP), semiconductor, software, foundry, packaging, and systems companies. The complexity of modern-day systems, the compression of development timelines, and the pressure for product differentiation make this kind of development unfeasible, driving a shift towards the integrated design efforts we’re seeing from system companies.

While semiconductors are at the heart of any electronic system, there is much more to consider. In many electronic systems, software represents the greatest cost and biggest bottleneck.  Thermal and power restrictions apply across the chip, package, and board. Form factor and user experience impact mechanical design. Every part of the resulting system is interrelated and must be optimized concurrently to produce a leading product.

For many years, the EDA industry has focused on delivering tools to semiconductor companies to enable chip design. We call this “core” EDA, and it will remain a vital technology. With an eye to the future, successful core EDA companies will move up to system design with SDE. As shown below, SDE calls for the convergence of electrical, software, and mechanical domains, and its outcome is not just a chip but an end product.

Vertical Aggregation and Disaggregation Drive SDE

There was a time when chip design was confined to large companies with the capability to fabricate chips. Now we are in an era of fabless semiconductor companies and pure-play foundries, and as a result, hundreds of companies are engaged in IC and/or IP design. This has enabled a tremendous wave of innovation and creativity, but it has also resulted in a disaggregated product design chain.

Today, some systems companies across a variety of vertical markets are choosing to re-aggregate (albeit without chip manufacturing), with the end goal of ensuring a high-value product. For example, some of the world’s largest systems companies have created in-house chip design teams. These vertically integrated systems companies form a natural market for SDE tools and flows.

Meanwhile, semiconductors are representing a larger part of the overall value of the end products. This is one reason why systems companies are adding semiconductor design capability to their engineering teams. And systems companies expect that their semiconductor suppliers, be they in-house design groups or third parties, provide much of the software stack including drivers, OS, and middleware.

Tooling and IP for SDE

Embedded software development traditionally begins very late in the overall cycle, thereby becoming the critical path to product shipment. Hence there’s an urgent need to “shift left” and allow embedded software development and hardware/software verification to begin much earlier. SDE tools and flows support this added software responsibility by providing a continuum of pre-silicon development platforms that support hardware/software co-design and co-verification, virtual platforms, emulation, simulation, and FPGA-based prototyping.

Other tools and capabilities that support SDE include multi-fabric power, thermal, and signal integrity analysis; chip/package/PCB co-design; incremental co-design between EDA and Mechanical CAD (MCAD) tools; design of MEMS devices within custom/analog IC flows; and the development of 2.5D and 3D IC packages. All these capabilities are available today.

System Design Enablement is not just about design tools – it requires design content as well. At the chip level, that content is increasingly provided by reusable semiconductor IP blocks. Today as much as 80% of an SoC may be composed of such blocks, which may include processors, memory, communications protocols, analog functions, and verification IP (VIP).

Conclusion

As system complexity grows, the various components of an electronic system can no longer be designed in isolation. The focus of EDA needs to expand from single chips and boards to entire systems. This new challenge is addressed by System Design Enablement, and it requires tools, IP, software content, and services aimed at making whole systems possible. SDE opens a new chapter in the history of electronic system design, and it will greatly expand the reach of EDA technology to meet the challenges of today’s vertically integrated companies and their highly differentiated designs.

Craig Cochran is the vice president of corporate marketing at Cadence Design Systems, Inc. He has more than 20 years of corporate, strategic and product marketing expertise at EDA and electronics companies including Real Intent, ChipVision Design Systems, Jasper Design Automation and Synopsys. He began his career as an applications engineer at Valid Logic Systems and a digital design engineer at General Electric. Cochran holds a bachelor of science degree cum laude in electrical engineering from the Georgia Institute of Technology.