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Posts Tagged ‘PCIe’

More space for satellites and a roadmap for data protection

Monday, February 12th, 2018

Blog Review – Monday, February 12, 2018
This week’s selection includes 100G Ethernet for data centers; Satellites will vie for space; A roadmap for data protection, and more from the blogsphere

The rise of data centers and increase in cloud-based computing has prompted Lance Looper, Silicon Labs, to examine how wireless networks are changing to meet the demands for performance and low latency and implementing 100G Ethernet.

Marveling at how connectivity has ‘shrunk’ the world, Paolo Colombo, ANSYS, looks skywards to consider the growth of connected devices. He looks at the role of space satellites and how small satellites will have their day for critical applications and introduces ‘pseudo sats’ which are vying for space in space.

An article about medical device design and manufacturing challenges has prompted Roger Mazzella, QT, to address each and provide a response to reassure developers. Naturally, QT’s products play a role in allaying many fears, but it is an interesting insight into the medical design arena.

An interesting case study is recorded by Hellen Norman, Arm, featuring Scratchy the robot. She asks German embedded systems developer, Sebastian Förster how he used a Cortex-M4, some motors, Lego bricks and cable ties to create a four-legged robot, programmed to walk using artificial intelligence (AI).

It’s not unusual to feel bewildered at a technology conference, so we can sympathise with Thomas Hackett, Cadence, who has a twist on the usual philosophical question of “What am I here for?” A walk through DesignCon caused a lightbulb moment, illuminating the real world interplay of IP, SoC and packaging.

With the IoT there are no secrets, and Robert Vamosi, Synopsys examines how data sharing may not be as innocuous as companies would have us believe, if it is not configured flawlessly. The Strava heatmap which reveals secret military locations has thrown up some serious issues which, we are assured, are being addressed, and which Vamosi sees as a model for other IoT and wearable device manufacturers.

Tackling software-defined networking (SDN) head-on, Jean-Marie Brunet, Mentor Graphics, presents a clear and strong case for accelerating verification using virtual emulation. Of course he advocates Veloce VirtuaLAB PCIe for the task, but backs up his recommendation with some sound reasoning and guidance.

By Caroline Hayes, Senior Editor

Blog Review – Monday, April 25 2016

Monday, April 25th, 2016

System validation partnership; Cloud’s blue sky thinking; Happy 50 th optic fiber; Back to PCIe basics; Pointing the fingerprint; Financial forecast

Retracing his steps, Richard Solomon, Synopsys, looks at the progress of PCI Express, and more specifically, how to handle the bandwidth increases. This blog details some solid principles and extends an offer of help for developers.

Fresh from rubbing shoulders with attendees of the SAE World Congress automotive industry technical conference and tradeshow, Pete Decher, Mentor Graphics, clearly has his eye on the latest Tesla model and its plans for autonomous driving. He reviews reactions to V2X (Vehicle to Infrastructure & Vehicle to Vehicle) and ECU (Electronic Control Unit) Consolidation.

Another review is delivered by Steve Brown, Cadence Design Systems, who attended the Optical Fiber Conference. He manages to celebrate the 50 th anniversary of fiber optic communications technology and looks at how it started and where it’s going.

Poring over financials is not everyone’s idea of fun, but Chris Ciufo, eecatalog, takes one for the team and compiled this blog about the economical outlook for the technology industry. He considers the role of the IoT, autonomous vehicles and their role on productivity.

Best practice for cloud computing is set out in the blog from Wim Slagter, ANSYS. He elaborates on eight Dos and Don’ts for High Performance Computing (HPC) and cloud computing to maximize it for engineering simulation.

Identifying the bottleneck of functional validation in SoC design, Eoin McCann, ARM, examines some of the IP tools the company offers to its ecodesign partners

New tools reduce the risk of IP reuse, believes Warren Savage, IP Extreme. He sets out a clear case for fingerprinting IP, a brief checklist and explains how Chip DNA Analysis software can be used in SoC design.

Caroline Hayes, Senior Editor

Blog Review – Monday, October 12 2015

Monday, October 12th, 2015

IoT issues of security and PCIe Gen 4; AMD’s graphic focus; Industry funding; Verification philosophy; Plant life; from sensors to servers

How will the IoT use PCIe Gen 4? Sadiya Ahmed, Anunay Bajaj and Anand Shirahatti, Synopsys, anticipate the boost the 16T transfer/s Gen 4 and outlines, with some useful graphics, the company’s single PCIe VC Verification VIP offering. There are also regional workshops running and the blog includes a link to free registration for Shanghai-China, Tokyo-Japan, Austin-Texas and Herzelia-Israel.

A guilt-ridden, but hopefully healthy, Chris Ciufo, eecatalog, ponders on how AMD continues to turn its attention to embedded graphics and provides an overview of three new embedded graphics families, how they are differentiated and used.

The semiconductor industry has trusted innovation and been guided by Moore’s Law for long enough but could be running out of steam without breakthroughs soon. Dustin Todd writes on the Semiconductor Industry Association site that the industry’s significant R&D budget should be supplemented by government funding.

Injecting a touch of philosophy into the world of electronics, Christine Young, Cadence, recalls the thoughts of Alex Orr, Broadcom, on “My First 100 Days in Formal Land.” Among the advice for formal verification, there is even some tactical philosophy from Sun Tzu, The Art of War.

Grown your own has never been more virtual, than with HUI!, the virtual garden assistant that provides real-time environment condition updates and care instructions for those with not-so-green fingers. Some appetising leaves illustrate the Atmel post, describing the role of the ATmefa328 from the company.

Imagination has joined the IoT Security Foundation and Alexandru Voica attended the launch and reports on some of the IoT’s vulnerable points, with some interesting graphics and analyst support.

The final instalement in a popular Sensors to Servers series by Eric Gowland, ARM, focuses on the server role. He chronicles the contribution from the company from CES this year, relates it to clients and the role of visualisation, both standard and custom.

Caroline Hayes, Senior Editor

ASIC Prototypes Take the Express Lane for Faster System Validation

Thursday, February 12th, 2015

Troy Scott, Product Marketing Manager, Synopsys Inc.
Demand for earlier availability of ASIC prototypes during a SoC design project is increasing because of the effort and cost to develop software drivers, firmware, and applications. Industry surveys show that design teams now spend up to 50% of engineering budget on software development. This urgency is pushing commercial vendors of FPGA-based prototypes to field products that can demonstrate improved productivity for the engineers that are responsible for hardware/software integration and system validation. In this article we’ll examine the state-of-the-art in FPGA-based prototyping tools and the benefits they deliver.

Design teams that have adopted commercial FPGA-based prototyping systems versus custom built or adapting FPGA evaluation boards typically do so to stretch the investment dollars over multiple  chip designs. Commercial systems tend to be modular and flexible, by stacking or tiling FPGA modules, so that capacity can be scaled up or down for a project’s resource demand and interface peripheral boards featuring interface PHYs can be selectively assembled around FPGA modules. The best commercial systems provide embedded system control elements for rapid programming, FPGA module chaining, clock and reset distribution, heat mitigation, and fault monitoring. All of which contribute to reliability and uptime that is superior to custom-built systems.

One of the major tasks of a physical prototype project is to map ASIC RTL and IP into the hardware resources of an FPGA which, in comparison to an ASIC design, provides a limited number of low-skew clock trees and dedicated memory resources. Replacement and substitution can be a time consuming effort to make the RTL “FPGA-friendly.” This is where FPGA logic synthesis tailored for FPGA-based prototypes helps speed the conversion task.  Synopsys’s ProtoCompiler, design and debug automation tool, provides two clock conversion techniques for the Synopsys HAPS Series. The first called HAPS clock optimization (HCO) is typically applied very early in the bring-up phase when it’s urgent to get the design operational quickly on the live hardware. HCO automatically chooses a master synchronizing clock and all registered elements are synchronized to it. The conversion is quick and easy since it does not depend on careful identification of clock and data signals or constraints by the prototype developer. When higher performance or asynchronous relationships must be modeled then ProtoCompiler provides advanced clock conversion that logically separates the gating from the clock and routes the gating to the dedicated FPGA clock to enable inputs of sequential elements. Separating the gating from the clock allows a single global clock tree to be used for all gated clocks that reference the same base clock.

The Verilog HDL language in the context of a prototyping flow can help address module replacement or exclusion of non-logic elements of the ASIC design. In ProtoCompiler’s design flow for HAPS, the Verilog Force replaces existing driver of internal signals in the hierarchy with new drivers and Verilog Bind inserts a module instance into the design hierarchy. These constructs are ideal for substituting circuitry, changing a clock tree, or to stub out part of an ASIC design that is not needed in the FPGA prototype. The commands when collected into a new file will override the RTL of the design which allows the prototype engineer to make surgical changes to the logic without touching the “golden” source of the RTL drop.

Another significant trend in the physical prototyping space is for vendors to deliver prototypes integrated with a CPU software development platform. These combinations are a popular architecture for hardware/software integration scenarios and ideal for software-driven testing and driver development.  The reprogrammable FPGA allows for testing of various IP configurations, connecting to analog PHYs implemented on test ICs, and clock, reset, and power management circuit integration between control and PHY.

Figure 1 illustrates a commercial implementation of an FPGA-based prototype with a CPU subsystem. The Synopsys DesignWare IP Prototyping Kits take this integration paradigm even further by pre-packaging various IP subsystems from the DesignWare IP catalog with reference drivers and example application running on Linux OS. The kits feature popular interfaces like USB, PCIe, and MIPI and can be assembled, powered on, and running within a few minutes making them ideal for rapid delivery to software developers.

Figure 2. Synopsys DesignWare IP Prototyping Kit Architecture

The demand for shorter bring-up schedules and more efficient work flows are driving innovations by commercial providers of FPGA-based prototyping tools. Many of the benefits come from the co-design of prototype hardware, firmware, and software elements that help expedite the migration from raw ASIC RTL and IP. Today the state of the art in ASIC prototyping and software development tools join software development platforms running reference designs with pre-packaged IP configurations. Prototyping kits are operational out of the box and allow hardware and software developers to immediately engage in integration and validation tasks necessary to ship the next great SoC design.

PCI-SIG-nificant Changes Brewing in Mobile and Small form Factor Designs

Wednesday, June 26th, 2013

Of five significant PCI Express announcements made at this week’s PCI-SIG Developers Conference, two are aimed at mobile embedded. It’s about time.

The big news from the PCI-SIG is speed. From PCI to PCI Express to Gen3 speeds, the PCI-SIG is an industry consortium that lets no grass grow for long. As the embedded, enterprise and server industries roll out PCIe Gen3 and 40G/100G Ethernet, the PCI-SIG and its key constituents like Cadence, Synopsis, LeCroy and others are readying for another speed doubling to 16 GT/s (giga transfers/second) by 2015.

The PCIe 4.0 next step would likely become known as “Gen4″ and it evolves bandwidth to 16Gb/s or a whopping 64 GB/s (big “B”) total lane bandwidth in x16 width. The PCIe 4.0 Rev 0.5 specification will be available Q1 2014 with Rev 0.9 targeted for Q1 2015.

Yet as “SIG-nificant” as this Gen4 announcement is, PCI-SIG president Al Yanes said it’s only one of five major news items.

Five PCI-SIG announcements at this week’s Developers Conference
The other announcements include: a PCIe 3.1 specification that consolidates a series of ECNs in the areas of power, performance and functionality; PCIe Outside the Box which uses a 1 – 3 meter “really cheap” copper cable called PCIe OCuLink with an 8G bit rate; plus two embedded and mobile announcements that I’m particularly enthused about. See Table 1 for a snapshot.

Table 1: There were five major announcements made by the PCI-SIG at June’s Developers Conference.
Figure 1: The PCI-SIG’s impending M.2 form factor is designed for mobile embedded ultrabooks, tablets, and possibly smartphones. The card will have a scalable PCIe interface and is designed for Wi-Fi, Bluetooth, cellular, SSD and more. (Courtesy: PCI-SIG.)

New M.2 Specification
One of two announcements for the mobile and embedded spaces, the new M.2 specification is a small, embedded form factor designed to replace the previous “Mini PCI” in Mini Card and Half Mini Card sizes (Figure 1). The newer, as-yet-publicly-unreleased M.2 card specification will detail a board that’s smaller in size and volume, but is intended to provide scalable PCIe performance to allow designers to tune SWaP and I/O requirements. PCI-SIG marketing workgroup chair Ramin Neshati told me that M.2 is part of the PCI-SIG’s deliberate focus on mobile in a fundamentally changing market.

The scalable M.2 card is designed as an I/O plug in for Bluetooth, Wi-Fi, WAN/cellular, SSD and other connectivity in platforms including ultrabook, tablet, and “maybe even smartphone,” said Neshati. At Rev 0.7 now, the Rev 0.9 spec will be released soon and the final (Rev 1.0?) spec will become public by Q4 2013.

Figure 2: The Mobile PCI Express (M-PCIe) specification targets mobile embedded devices like smartphones to provide high-speed, on-board PCIe connectivity. (Courtesy: PCI-SIG.)
Figure 3: M-PCIe by the PCI-SIG can be used in multiple high speed paths in a smartphone mobile device. (Courtesy: PCI-SIG and MIPI Alliance.)

Mobile PCIe (M-PCIe)
The momentum in mobile and interest in a PCIe on-board interconnect lead the PCI-SIG to work with the MIPI Alliance and create Mobile PCI Express: M-PCIe. The specification is now available to PCI-SIG members and creates an “adapted PCIe architecture” bridge between regular PCIe and MIPI M-PHY (Figure 2).

Using the MIPI M-PHY physical layer allows smartphone and mobile designers to stick with one consistent user interface across multiple platforms, including already-existing OS drivers. PCIe support is “baked into Windows, iOS, Android,” and others, says PCI-SIG’s Neshati.  PCI Express also has a major advantage when it comes to interoperability testing, which runs from the protocol stack all the way down to the electrical interfaces. Taken collectively, PCIe brings huge functionality and compliance benefits to the mobile space.

M-PCIe supports MIPI’s Gear 1 (1.25-1.45 Gbps), Gear 2 (2.5-2.9 Gbps) and Gear 3 (5.0-5.8 Gbps) speeds. As well, the M-PCIe spec provides power optimization for short channel mobile platforms, primarily aimed at WWAN front end radios, modem IP blocks, and possibly replacing MIPI’s own universal file storage UFS mass storage interface (administered by JEDEC) as depicted in Figure 3.

PCI Express Ready for More
More information on these five announcements will be rolling out soon. But it’s clear that the PCI-SIG sees mobile and embedded as the next target areas for PCI Express in the post-PC era. Yet the organization is wisely not abandoning the PCI Express standard’s bread and butter in high-end/high-performance servers and systems.

ciufo_chrisChris A. Ciufo is editor-in-chief for embedded content at Extension Media, which includes the EECatalog print and digital publications and website, Embedded Intel® Solutions, and other related blogs and embedded channels. He has 29 years of embedded technology experience, and has degrees in electrical engineering, and in materials science, emphasizing solid state physics. He can be reached at

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