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Posts Tagged ‘PPA’

eSilicon Launches Integrated ASIC Design And Manufacturing Platform

Tuesday, May 26th, 2015

Gabe Moretti, Senior Editor

Since 2001 eSilicon has helped system companies with some of the most time consuming tasks needed to successfully manage a chip development project.  Today the tools provided by eSilicon allow customers to: browse and buy IP, Optimize a design, get quotes from foundries and compare them, and track a project.  Just in time for DAC, the company announced the availability of its second-generation online ASIC design and manufacturing platform the groups all of the tool under a unified and coherent environment.

Figure 1: The STAR Logical Architecture

Named eSilicon STAR (self-service, transparent, accurate, real-time), the platform supports eSilicon’s existing IP browsing, instant quoting and work-in-process tracking capabilities along with a new chip optimization offering that leverages design virtualization technology. The platform also delivers an enhanced user interface with simplified account setup and access. Tool names have also been unified under the STAR platform as follows:

  • Navigator: Search, select and try eSilicon IP online
  • Optimizer: Versatile self-service IC design optimization for power, performance and area
  • Explorer: Evaluate options and get fast, accurate quotes for MPW and GDSII handoffs
  • Tracker: Real-time design progress and IC delivery tracking, including order history, forecasts and yield data

Figure 2: Details of STAR’s  Components

The newly introduced STAR Optimizer provides ASIC designers with an easy way to access eSilicon’s block- and chip-level optimization services. Users can download free software that will analyze their design’s register transfer language (RTL) description to check for robustness. If the design passes these tests, users can then request a design optimization service engagement online. eSilicon’s design optimization service uses unique design virtualization technology to find the optimal design implementation from a power, performance or area perspective. The service is built on a “pay for results” philosophy – the customer pays for the service only if a pre-determined optimization result is achieved.

At first such income scheme may appear naïve when judged in a traditional EDA practice of quarter by quarter revenue measurement, but I think that the approach has great value from a strategic point of view.  It builds not customers but partners that feel they are being treated fairly, and this is the secret to the success of eSilicon: find partners, not just sources of income.

“We have been using our design virtualization technology to optimize the PPA of customer designs for years,” said Prasad Subramaniam, Ph.D., vice president of design technology at eSilicon. “We’ve achieved some significant results in literally minutes with this technology. We are now making this powerful capability available to all design teams worldwide through the STAR Optimizer interface.”

Optimizer is based on design virtualization technology, which rapidly explores all possible ASIC implementation scenarios to identify the best fit for a particular set of PPA and cost requirements. Design choices such as cell libraries, memory architectures, process options, operating conditions and Vt mix are enumerated instantly, without the need to perform time-consuming what-if implementation trials. Design virtualization uses big data analytics and machine learning to rapidly deliver the business and technical insights needed to build an optimized design.

“Our market research told us that the semiconductor community was ready for online technology and big data analytics,” said Mike Gianfagna, eSilicon’s vice president of marketing. “With over 500 users who have generated over 1,000 custom quotes in 47 countries, we have validation that our research was correct. The new eSilicon STAR platform takes the user experience to the next level, both from an ease-of-use and capability point of view.”

The eSilicon Star platform is available now. There is no cost or obligation to use any of the STAR tools. See for yourself how easy to use and how powerful it is in the eSilicon booth at DAC.

Cadence Introduces Genus Synthesis Solution

Wednesday, June 3rd, 2015

Gabe Moretti, Senior Editor
Historically synthesis tools have targeted the transistors, keeping in focus the architecture of the silicon and optimizing it while not paying much attention to the system architecture.  it was, of course, a natural thing to do since given a design, EDA tools focused on implementing it in the best of possible way.

This is the main reason that System level tools have been slow to gain traction, and only lately are showing that they can indeed contribute significantly to efficient products.  In fact by analyzing an architecture it is often possible to improve the efficiency of the design and, in turn, deliver a circuit that meets timing, power, and area requirements in less time than by optimizing the gate level netlist.

Genus does just that.  Its goal is to optimize the RTL netlist before logic synthesis by forecasting the physical characteristics of the resulting gate level netlist.

Cadence’s Genus Synthesis Solution is a next-generation register-transfer level (RTL) synthesis and physical synthesis engine.  The company stated that Genus Synthesis Solution incorporates a multi-level massively parallel architecture that delivers up to 5X faster synthesis turnaround times and scales linearly beyond 10M instances. In addition, the tool’s new physically aware context-generation capability can reduce iterations between unit- and chip-level synthesis by 2X or more. This combination enables up to 10X improvement in RTL design productivity.

Figure 1: Genus integrated optimization architecture

Key Genus Synthesis Solution features and capabilities include:

  • Massively parallel architecture –The tool performs timing-driven distributed synthesis of a design across multiple cores and machines. All key steps in the synthesis flow leverage both multiple machines and multiple CPU cores per machine.
  • Physically aware context generation – The complete timing and physical context for any subset of a design can be extracted and used to drive RTL unit-level synthesis with full consideration of chip-level timing and placement, significantly reducing iterations between chip-level and unit-level synthesis runs.
  • Unified global routing with Innovus Implementation System – Genus Synthesis Solution and Cadence Innovus Implementation System, a next-generation physical implementation solution, share an enhanced 4X faster timing-driven global router that enables tight correlation of both timing and wirelength to within 5 percent from synthesis to place and route.

  • Global analytical architecture-level PPA optimization – The solution incorporates a new datapath optimization engine that concurrently considers many different datapath architectures across the whole design and then leverages an analytical solver to pick the architectures that achieve the globally optimal PPA. This engine delivers up to 20 percent reduction in datapath area without any impact on performance.

Cadence Introduces Innovus Implementation System

Friday, March 13th, 2015

Gabe Moretti, Senior Editor

Cadence Design Systems  has introduced its Innovus Implementation System, a next-generation physical implementation solution that aims to enable system-on-chip (SoC) developers to deliver designs with best-in-class power, performance and area (PPA) while accelerating time to market.  The Innovus Implementation System was designed to help physical design engineers achieve best-in-class performance while designing for a set power/area budget or realize maximum power/area savings while optimizing for a set target frequency.

The company claims that the Innovus Implementation System provides typically 10 to 20 percent better power/performance/area (PPA) and up to 10X full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes as well as at established process nodes.

Rod Metcalfe, Product Management Group Director pointed out the key Innovus capabilities:

- New GigaPlace solver-based placement technology that is slack-driven and topology-/pin access-/color-aware, enabling optimal pipeline placement, wirelength, utilization and PPA, and providing the best starting point for optimization
- Advanced timing- and power-driven optimization that is multi-threaded and layer aware, reducing dynamic and leakage power with optimal performance
- Unique concurrent clock and datapath optimization that includes automated hybrid H-tree generation, enhancing cross-corner variability and driving maximum performance with reduced power
- Next-generation slack-driven routing with track-aware timing optimization that tackles signal integrity early on and improves post-route correlation
Full-flow multi-objective technology enables concurrent electrical and physical optimization to avoid local optima, resulting in the most globally optimal PPA

    The Innovus Implementation System also offers multiple capabilities that boost turnaround time for each place-and-route iteration. Its core algorithms have been enhanced with multi-threading throughout the full flow, providing significant speedup on industry-standard hardware with 8 to 16 CPUs. Additionally, it features what Cadence believes to be the industry’s first massively distributed parallel solution that enables the implementation of design blocks with 10 million instances or larger. Multi-scenario acceleration throughout the flow improves turnaround time even with an increasing number of multi-mode, multi-corner scenarios.

    Rahul Deokar, Product Management Director added that the product offers a common user interface (UI) across synthesis, implementation and signoff tools, and data-model and API integration with the Tempus Timing Signoff solution and Quantus QRC Extraction solution.

    The Innovus common GUI

    Together these solutions enable fast, accurate, 10nm-ready signoff closure that facilitates ease of adoption and an end-to-end customizable flow. Customers can also benefit from robust visualization and reporting that enables enhanced debugging, root-cause analysis and metrics-driven design flow management.

    “At ARM, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets,” said Noel Hurley, general manager, CPU group, ARM. “We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM Cortex-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target. Based on our results, we are confident that the new physical implementation solution can help our mutual customers deliver complex, advanced-node SoCs on time.”

    “Customers have already started to employ the Innovus Implementation System to help achieve higher performance, lower power and minimized area to deliver designs to the market before the competition can,” said Dr. Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. “The early customers who have deployed the solution on production designs are reporting significantly better PPA and a substantial turnaround time reduction versus competing solutions.”


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