Two 32bit processor IPs have been released by Cortus, the company’s second generation of processor IP that takes a minimalist approach to the ‘third wave’ of applications. Caroline Hayes spoke to Roddy Urqhart, Vice President Sales & Marketing, Cortus.
Cortus challenges the dominance of ARM in connected, intelligent devices, with the introduction of two processor cores that are power and silicon-efficient. Urqhart classifies the third wave of computational devices as connected and intelligent and now with sensors, connectivity and intelligence. They mark, says Urqhart (pictured), the edge of the IoT (Internet of Things).
“There are similar requirements to automotive sensing,” says Urqhart. “There is little standardisation, as for example, in the mobile market, with LTE for communications. RTOS will be suitable, and WiFi, Bluetooth and ZigBee will all play a part.”
The connected devices will need to have a small form factor and low power consumption. Batteries cannot be changed every night – they will need to last months, he points out. This will require minimalist cores. “The third wave of connected devices will require a new set of design rules,” he asserts.
The company licenses low-power, 32bit processor cores for intelligent connected devices. It is the first to use the v2 instruction set which reduces the size of a system’s instruction memory in always on/always listening systems or Bluetooth Smart applications, which use lower clock frequencies.
The Harvard architecture has 16 32bit registers, a three-stage pipeline and a sequential multiplier. It supports the AXI4-Lite bus as well as Cortus APS peripherals. The core delivers 2.83DMIPS/MHz and 1.44CoreMarks/MHz in computational performance.
The CPU starts at 9.8kgates, when optimised for area and delivers dynamic power of 12µW/MHz with a 90nm process.
The second release, the APS25 IP core supports extendable, dual- and multi-core systems. The core is aimed at embedded systems, increased computational performance and system complexity, with maximum code density and extendibility.
It has been designed to support accelerating computation by using coprocessors or symmetric multiprocessing. It is intended to be used as a building block in dual-, or multi-core systems.
It also has a Harvard architecture, 16 32bit registers, a five-stage pipeline, a sequential multiplier. It supports the AXI4 bus as well as APS peripherals.
Up to eight co-processors can be added to a core.
The coprocessor interface allows licensees to add custom coprocessors, to accelerate functions such as cryptography or signal processing, without knowing details of the internals of the core. Co-processor instructions can be inserted into C-code appearing as function calls.
Its size make it possible to be used where two cores are required. For example, two cores to execute the same code in lock step and to trigger an alarm if the results do not match. Another use is secure execution, to physically separate the execution of secure software by running it on a supervisory CPU, while application code runs on another CPU core.
For both cores, the v2 instruction set allows the seamless mixing of 16-, 24- and 32bit instructions without mode switching. (The company will continue to offer products based on the v1 instruction set in parallel with those based on the v2 instruction set. All C/C++ or assembler code can be used unmodified on the v2 cores. If changes are needed, however, that does not pose a major upset, according to Urqhart. “Recompilation and assembly is not onerous, says Urqhart, “you have to that for embedded software, anyway.”
All cores interface to the company’s peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the APS bus. They also share the simple vectored interrupt structure, which ensures rapid, real time interrupt response, with low software overhead.
The APS tool chain and IDE (for C and C++) is available to licensees free of charge, and can be customised for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium μC/OSII.
Security will be a challenge in the third wave of devices, as the connected devices will present a bigger attack surface, says Urqhart. “The minimalist core, and the many licensees are focused on security,” he says “With continuity but new instruction sets and two cores, based on an instruction set. The small core means there are less circuits to switch and dynamic power is reduced in proportion.” The complexity of firmware has increased,” maintains Urqhart, “so the instruction memories have got bigger. The key is to balance memory, core size and the instruction, with 16, 24 and 32bit instructions.”
Cortus cores have already been designed into a wide range of embedded applications and have been adopted by over 35 licensees.
Caroline Hayes – October 09, 2014