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Behold the Intrinsic Value of IP

Monday, March 13th, 2017

By Grant Pierce, CEO

Sonics, Inc.

Editor’s Note [this article was written in response to questions about IP licensing practices.  A follow-up article will be published in the next 24 hours with the title :” Determining a Fair Royalty Value for IP”].


Understanding the intrinsic value of Intellectual Property is like beauty, it is in the eye of the beholder.  The beholder of IP Value is ultimately the user/consumer of that IP – the buyers. Buyers tend to value IP based upon their ability to utilize that IP to create competitive advantage, and therefore higher value for their end product. The IP Value figure above was created to capture this concept.

To be clear, this view is NOT about relative bargaining power between buyer and the supplier of IP – the seller –  that is built on the basis of patents. Mounds of court cases and text books exist that explore the question of patent strength. What I am positing is that viewing IP value as a matter of a buyer’s perception is a useful way to think of the intrinsic value of IP.

Position A on the value chart is a classification of IP that allows little differentiation by the buyer, but is addressing a more elastic market opportunity. This would likely be a Standard IP type that would implement an open standard. IP in this category would likely have multiple sources and therefore competitive pricing.  Although compliance with the standard would be valued by the buyer, the price of the IP itself would be likely lower reflecting its commodity nature. Here, the value might be equated to the cost of internally creating equivalent IP. Since few, if any, buyers in this category would see advantage for making this IP themselves and because there are likely many sellers, the intrinsic value of this IP is determined on a “buy vs buy” basis.  Buyers are going to buy this IP regardless, so they’ll look for the seller with the proposition most favorable to the buyer – which often is just about price.

Position B on the value chart is a classification of IP that allows for differentiation by the buyer, but addresses a more elastic market. IP in this category might be less constrained by standards requirements. It is likely that buyers would implement unique instantiations of this IP type and as a result command some end competitive advantage. Buyers in this category could make this IP themselves, but because there are commercial alternatives, the intrinsic value is determined by applying a “make vs buy” analysis. The value proposition of the sellers of this type of IP often include some important, but soft value propositions (e.g., ease of re-use, time-to-market, esoteric features), the make vs buy determination is highly variable and often buyer-specific. This in part explains the variability of pricing for this type of IP.

Position C on the value chart is a classification of IP that serves a less elastic market and empowers buyers to differentiate through their unique implementations of that IP. This classification of IP supports license fees and larger, more consistent, royalty rates. IP in this category becomes the competitive differentiation that sways large market share to the winning products incorporating that IP. This category supports some of the larger IP companies in the marketplace today. Buyers in this category are not going to make the IP themselves because the cost of development of the product and its ecosystem is too prohibitive and risky. The intrinsic value really comes down to what the seller charges.

This is a “buy vs not make” decision – meaning one either buys the IP or it doesn’t bother to make the product. A unique hallmark of IP in this position is that so long as the seller applies pricing consistently, then all buyers know at the very least that they are not disadvantaged relative to the competition and will continue to buy. Sellers will often give some technology away to encourage long-term lock in. For these reasons, pricing of IP in this space tends to be quite stable. That pricing level must subjectively be below the level that customers begin to perform unnatural acts and explore unusual alternatives.  So long as it does, the price charged probably represents accurately the intrinsic value.

Position D on the value chart is a classification of IP that requires adherence to a standard. Like category A, adherence to the standard does not necessarily allow differentiation to the buyer. The buyer of this category of IP might be required to use this IP in order to gain access to the market itself. Though the lack of end-product differentiation available to the buyer might suggest a lower license fee and/or lower to zero royalty rate, we see a significantly less elastic market for this IP type.

This IP category tends to comprise products adhering to closed and/or proprietary standards. IP products built on such closed and/or proprietary standards have given rise to several significant IP business franchises in the marketplace today. The IP in position D is in part characterized by the need to spend significant time and money to develop, market and maintain (defend) their position, in addition to spending on IP development. For this reason, teasing out the intrinsic value of this IP is not as straightforward as “make vs buy.” Pricing is really viewed more as a tax. So the intrinsic value determination is based on a “Fair Tax” basis. If buyers think the tax is no longer “fair,” for any reason, they will make the move to a different technology.


Position A:  USB, PCI, memory interfaces (Synopsys)

Position B:  Configurable Processors, Analog IP cores (Synopsys, Cadence)

Position C:  General Purpose Processors, Graphics, DSP, NoC, EPU (ARM, Imagination, CEVA, Sonics)

Position D: CDMA, Noise Reduction, DDR (Qualcomm, Dolby, Rambus)

Why Customer Success is Paramount

Sonics is an IP supplier whose products tend to reside in the Type C category. Sonics sets its semiconductor IP pricing as a function of the value of the SoC design/chip that uses the IP. There is a spectrum of value functions for the Sonics IP depending upon the type of chip, complexity of design, target power/performance, expected volume, and other factors. Defining the upper and lower bounds of the value spectrum depends upon an approximation of these factors for each particular chip design and customer.

Royalties are one component of the price of IP and are a way of risk sharing to allow customers to bring their products to market without having to pay the full value of the incorporated IP up front. The benefit being that the creator and supplier of the IP is essentially investing in the overall success of the user’s product by accepting the deferred royalty payment. Sonics views the royalty component of its IP pricing as “customer success fees.”

With its recently introduced EPU technology, Sonics has adopted an IP business model based upon an annual technology access fee and a per power grain usage fee due at chip tapeout. Under this model, customers have unlimited use of the technology to explore power control for as many designs as they want, but only pay for their actual IP usage in a completed design. The tape out fee is calculated based on the number of power grains used in the design on a sliding scale. The more power grains customers use, the more energy saved, and the lower the cost per grain. Using more power grains drives lower energy consumption by the chip – buyers increase the market value of their chips using Sonics’ EPU technology. The bottom line is that Sonics’ IP business model depends on customers successfully completing their designs using Sonics IP.

Blog Review, Monday, September 12, 2016

Monday, September 12th, 2016

This week, we find the legacy of Star Trek at 50; celebrate design challenges from NXP and; investigate criminal activity and speculate on Bluetooth 5 and headphone design; arriving late for an FPGA verification tutorial and how depth sensors make sense of a 3D world

The enduring appeal of Star Trek on its 50th anniversary sets Tom Smithyman, Ansys, thinking about communications, and how Qualcomm challenged engineers to emulate the great and the good of the USS Enterprise and create Dr McCoy’s medical tricorder.

Another challenge is laid down by NXP, which has teamed up with, for engineers to fulfil the potential of NXP’s Kinetis FlexIO for the IoT. Donnie Garcia, ARM, tracks how engineers can maximize the, often over-looked, microcontrollers at the edge of the IoT, with some arachnid-like illustrations.

Quoting a bank robber is an unusual opening for a technology blog, but Matthew Rosenquist, Intel, uses Willie Sutton to help us understand the cybercriminal. His blog about cryptocurrencies, like Bitcoin, and how to protect transactions is a detailed look at the cyber economy – and this is just part one.

Apple’s decision to remove the headphone jack in its latest phone has been met with derision, but one positive is that it has prompted Paul Williamson, ARM, to speculate on the whether wireless accessories could be boosted as Bluetooth 5 brings faster data rates.

How have I missed the first three parts of Mentor Graphics’ Harry Foster’s blog about Functional Verification? Part 4 looks at FPGA verification and some handy ‘escapes’ for effective verification, written by an engineer, for engineers.

Anyone designing consumer electronics will be familiar with the DDR PHY interface (DFI) protocol for signal, timing and transfer. Deepak Gupta, Synsopsys has written a clear, comprehensive analysis of how and why it is needed and used most effectively.

Continuing a theme he has explored before, Jeff Bier, Berkeley Design Technology, looks at depth sensing and what companies are doing with varieties of depth sensors.

We all love Whiteboard Wednesdays, and Corrie Callenbach, Cadence Design Systems, highlights Michelle Mao’s hierarchical CNN design for traffic sign recognition, highlighting Tensilica Vision DSPs.

Caroline Hayes, Senior Editor

Blog Review – Tuesday, May 31 2016

Tuesday, May 31st, 2016

Security issues around IoT and maritime vessels; CCIX Consortium accelerates data centers; Cheers for metering; Noise integrity in ADAS; Virtual Reality in practice

Protecting IoT devices is clearly and elegantly outlined by Jim Wallace, ARM, he includes illustrations, a lot of information and guidelines on advice on how security can produce new business models.

Accelerating data centers always raises interest and when names like AMD, ARM, Huawei, IBM, Mellanox, Qualcomm, and Xilinx come together. Steve Liebson, Xilinx, describes how the companies, via the CCIX (Cache Coherent Interconnect for Accelerators) Consortium are developing a single interconnect technology specification whereby processors using different instruction set architectures can share data with accelerators and enable efficient heterogeneous computing to improve efficiency.

Advocating an alternative to the plan to drink beer when the fresh water runs out, David Andeen, Maxim explains the importance of an ultrasonic water meter which can accelerate design cycles and reduce the cost of meters.

All in the name of research, Alexandru Voica, Imagination, tries his hand at Daydream, the Virtual Reality (VR) platform built on Android N and outlines the rules of VR.

Another cyber threat is identified by Robert Vamosi, Synopsys. His blog looks at research from Plymouth University and how vulnerable marine vessels can be at risk.

The undeniable increase in Advanced Driver Assistance Systems (ADAS) needs careful design consideration, and Ravi Ravikumar, ANSYS, discusses how the ANSYS CPS simulation helps power noise integrity to be met. His blog is informative, with some clear graphics to illustrate ADAS design.

For a quick catch-up on USB 3.1 and the Type-C connector, turn to Chris A Ciufo, eecatalog, for a quick reference guide. He includes some handy links for extra reading.

A review of the Bangalore, India, Design&Reuse event is provided by Steve Brown, Cadence Design Systems. A rundown of keynotes ends with a head-up for the next event.

Apple vs Qualcomm. It Is More Than Money

Wednesday, February 1st, 2017

Gabe Moretti, Senior Editor

On the surface the various legal actions by the Korean and US governments as well as Apple against Qualcomm appear to be about money, or how to split revenue from product that uses a standard that Qualcomm helped to develop.  But there is more to the suit.

The Background

I t would be impossible to grow an industry without standards that make it possible for various portion of the industry to cooperate and allow tools and methods to work together.  To this end that are organizations that develop, distribute, and manage such standards.  The IEEE is the one most familiar in the US.  Qualcomm and Apple are both members of ETSI, an SSO based in Sofia Antipolis, France, which includes more than 800 members from countries across five continents. ETSI produces globally accepted standards for the telecommunications industry. For example, ETSI created or helped to create numerous telecommunication standards, including the 2G/GSM, 3G/UMTS, and4G/LTE cellular communication standards.

Developing a standard requires the contribution of Intellectual Property (IP) by entities, usually corporate entities, universities, or other research organizations.  Offering IP without restrictions would, almost always, hurt the offering entity financially, so a legal tool that protects it has been developed.    For patents that companies have declared “essential” to the standard, patent law is reinforced by contractual obligations to license such patents on Fair, Reasonable, And non-Discriminatory commitments.  The legal wording of the tool is called a FRAND (or RAND) commitment.  The entire issue revolves around the definition of the term “Reasonable”.  In a meeting on February 2015 the IEEE defined the term as follows:

“Reasonable Rate” shall mean appropriate compensation to the patent holder for the practice of an Essential Patent Claim excluding the value, if any, resulting from the inclusion of that Essential Patent Claim’s technology in the IEEE Standard. In addition, determination of such Reasonable Rates should include, but need not be limited to, the consideration of:

  • The value that the functionality of the claimed invention or inventive feature within the Essential Patent Claim contributes to the value of the relevant functionality of the smallest saleable Compliant Implementation that practices the Essential Patent Claim.
  • The value that the Essential Patent Claim contributes to the smallest saleable Compliant Implementation that practices that claim, in light of the value contributed by all Essential Patent Claims for the same IEEE Standard practiced in that Compliant Implementation.
  • Existing licenses covering use of the Essential Patent Claim, where such licenses were not obtained under the explicit or implicit threat of a Prohibitive Order, and where the circumstances and resulting licenses are otherwise sufficiently comparable to the circumstances of the contemplated license.

The licensing assurance shall be either:

  • a) A general disclaimer to the effect that the Submitter without conditions will not enforce any present or future Essential Patent Claims against any person or entity making, having made, using, selling, offering to sell, or importing any Compliant Implementation that practices the Essential Patent Claims for use in conforming with the IEEE Standard; or,
  • b) A statement that the Submitter will make available a license for Essential Patent Claims to an unrestricted number of Applicants on a worldwide basis without compensation or under Reasonable Rates, with other reasonable terms and conditions that are demonstrably free of any unfair discrimination to make, have made, use, sell, offer to sell, or import any Compliant Implementation that practices the Essential Patent Claims for use in conforming with the IEEE Standard. An Accepted LOA that contains such a statement signifies that reasonable terms and conditions, including without compensation or under Reasonable Rates, are sufficient compensation for a license to use those Essential Patent Claims and precludes seeking, or seeking to enforce, a Prohibitive Order except as provided in this policy.

The ETSI interpretation of “reasonable” is essentially the same as that of the IEEE.

The Apple Claim

Apple filed a claim in the US District Court in Southern California against Qualcomm.  The entire claim is exactly 100 pages long, so I am reporting only the key elements of it.  It is a fact that Qualcomm produces and licenses to semiconductor companies designs that implement connectivity between a device and the network that uses 3G or 4G standards.  Intellectual property of Qualcomm that is protected by patents was offered to ETSI in the development of both standards under the Essential Patent Claims and therefore it falls within the FRAND rules.  Apple’s claim states:

The description of the FRAND arrangement in the official claim is worth reading even if some of the terminology is slightly different from the usual ones used in our industry.

“Like other SSOs, ETSI requires participants to commit to abide by its Intellectual Property Rights (“IPR”) Policy, which sets forth the rights and obligations of its members. Pursuant to the IPR Policy, members are required to disclose standard-essential and potentially standard-essential patents and patent applications in a timely fashion. [ETSI Rules of Procedure, Annex 6, Clause 4.

The IPR Policy further requires that SEP owners submit a written commitment that they are prepared to grant irrevocable licenses on FRAND terms. If no FRAND commitment is made, the IPR Policy provides for ETSI to investigate alternative technology options for the standard to avoid the patent in question.

According to ETSI’s self-reporting portal, Qualcomm has declared over 30,000 global assets to be “ESSENTIAL IPR.” No objective party has tested the actual essentiality or validity of these assets.

Qualcomm has submitted IPR undertakings to ETSI with regard to each of the patents at issue in this matter. By submitting those declarations, Qualcomm promised that “[t]o the extent that the IPR(s) . . . are or become, and remain ESSENTIAL in respect of the ETSI Work Item, STANDARD and/or TECHNICALSPECIFICATION,” Qualcomm is “prepared to grant irrevocable licenses under this/these IPR(s) on terms and conditions which are in accordance with Clause 6.1of the ETSI IPR Policy.

Qualcomm, therefore, is contractually obligated to grant licenses on FRAND terms to these patents to Apple and other manufacturers of products that, through the baseband processor chipsets they use, conform to ETSI standards, as well as to third-party suppliers of baseband processor chipsets. Qualcomm made similar promises to other SSOs as well.

Because Apple is a third party that wishes, through the baseband processor chipsets it uses, to implement 3G/UMTS and 4G/LTE standard-compliant technology in the products it sells, Apple is a third-party beneficiary of the contracts between Qualcomm and ETSI.

Apple relied on Qualcomm’s promises to ETSI. Specifically, Apple and other wireless device manufacturers made a conscious choice to develop and sell products compatible with 3G/UMTS and 4G/LTE, relying on Qualcomm’s promise hat any third-party supplier of baseband processor chipsets or products using them could avoid patent litigation and obtain a license to any patents that Qualcomm has declared essential to the 3G/UMTS and 4G/LTE standards.

Qualcomm’s breach of its FRAND commitments, described insignificant detail below, is a foundation of its scheme to acquire and abuse monopoly power in the cellular industry.”

The claim also describes how the FRAND rule is to be implemented.

“FRAND royalties must start with the proper royalty base and a proper royalty rate, as required by the patent laws, but also must meet additional criteria designed to prevent misuse of the monopoly power conferred by adoption of a standard. In particular, FRAND royalties must be limited by the actual technical contribution of the patented technology to the standard, rather than (a) the “lock-in” value that arises from standardization of technologies, i.e., the value gained simply because companies are forced to use the technology mandated in the standard,(b) the value of all the technologies incorporated in an entire standard, or (c) the competing value of the many technologies, and many other standards that make up the actual device.”

Later the claim states:

“Qualcomm broke its promise and has breached its FRAND commitments. Qualcomm illegally double-dips by selling chipsets that allow mobile telephones to connect to cellular networks and then separately licensing (but never to competitors) the purportedly necessary intellectual property. By tying together the markets for chipsets and licenses to technology in cellular standards, Qualcomm illegally enhances and strengthens its monopoly in each market and eliminates competition. Then, Qualcomm leverages its market power to extract exorbitant royalties, later agreeing to reduce those somewhat only in exchange for additional anticompetitive advantages and restrictions on challenging Qualcomm’s power, further solidifying its stranglehold on the industry.”

Issues to Consider

The first thing to be realized is that this claim is about how to share revenue, not about standard making processes.  Apple wants a larger share of revenue from the sale of its product, while Qualcomm wants to protect what it gets right now by re-defining how royalties are computed.  Yet, there are other issues raised that may impact the electronics industry and EDA vendors.

Should royalties be fixed at a certain amount regardless of the sale price of the unit that use the licensed IP?  Or, as Qualcomm contends, should royalties be a percentage of the price charged to the customer?

I do not think that an IP more valuable when used to control the temperature in a passenger cabin of an airplane or in a home.

What is the intrinsic value of an IP?

The IP should have a value that is independent of the sale price of a system in which it is used.  The value of an IP, I think, is the result of three components: the cost of developing the IP, the profit margin desired by its implementer, and the market demand for it.  The IP has an intrinsic value that is independent of the value of the product in which it is used.

How many times can he owner of the IP charge for its use in the same system to the same customer?

Qualcomm charges a royalty for every chipset used in the system and another royalty for the use of the same IP as a functionality of the system.

    System Integration Requires a Shared Viewpoint

    Tuesday, December 17th, 2013

    By John Blyler

    Qualcomm uses Dassault Systemes’ dashboarding tool in its Hexagon DSP chip to incorporate multiple design metrics from key EDA tools.

    The EDA tool market has longed talked about its need to expand beyond the creation of silicon-based system-on-chips (SoCs) to provide packages that integrate the larger hardware and software system. Specifically, the major tool vendors emphasized the need to move beyond EDA-centric issues like electronic system level (ESL) design, functional verification, design-for-yield or any similar so-called crisis issues. The goal has been to move beyond chip creation to system integration to deal with both hardware and software at the chip, board, and end-user product levels.

    “It begins with a shift from design creation to integration in the electronic systems industry,” states the Cadence’s EDA Vision 360 report. EDA tool companies have had to expand their coverage into the larger system market, thanks to changes in the semiconductor supply chain.

    Regardless of the drivers, the expansion from creation to integration tools for the larger system has not been easy move for a variety of technical and cultural reasons. Consider but one aspect of the problem: How to provide higher-level integration when your customer uses a variety of internal and competitive tools? For example, most IDMs like Intel, Samsung and Apple, as well as fabless chip companies use a variety of EDA tools for synthesis, place and route (P&R), time and power closure, etc. Further, many use a mix of internal tools that have been tailored to the needs of the customer.

    To become a system integrator – at least from the chip design space viewpoint – tool providers will need a mechanism to gather, analyze and display useful data metrics from a variety EDA packages. One of the few companies that come close to such an application is not an EDA company at all, but rather comes from a higher-level, project lifecycle management (PLM) provider.

    Qualcomm recently shared their challenges in integrating the metrics from a mix of chip design tools. Their problem was how to put together all of the disjointed design pieces for development of its Hexagon DSP-based multithreaded CPU architecture. With a global design team (San Diego, India and Austin), the company had to communicate all of the traditional design metrics like timing and area, with secondary metrics like power and signal integrity. Adding to this technical complexity was the diversity of professionals that needed access to these metrics, from system architects, RTL coders to logical and physical designers.

    The answer was simply to use dashboards to display data and metrics in such as way as to quickly show trends and trouble spots. Good dashboards highlight the metrics data in a graphical analysis format while also providing a transition from high-level to detailed low-level views. This abstraction-level zoom-in/zoom-out capability helps designers quickly spot trouble areas and then probe down into the details.

    Dwight Galbi, Principle Manager of Qualcomm

    Dashboarding is nothing new. “Qualcomm has many internal dashboards,” explained Dwight Galbi, Principle Manager of Qualcomm’s physical design team at a recent Dassault Systemes’s Customer Forum. “We have dashboards that cover some of the (design metrics) … but not one that incorporated all of them.” What was needed was a dashboard to provide design metrics from a variety of EDA tools throughout the chip design process.

    That’s where Dassault Systemes’s dashboarding tool called Pinpoint came to into play.  In his presentation, Galbi listed the mix of life cycle tools (albeit from one vendor, i.e.,, Synopsys) used in his recent DSP project. The list included Design Compiler for synthsis;  IC and Talis for P&R; and Prime Time for sign off.

    “The beauty here is that these are four different tools but you can incorporate all of the reports into the same web-based server,” said Galbi. Equally important (though not mentioned by Galbi) was that the tool provides a graphical visualization of physical design, timing paths, etc., without needing to reload the entire design block. This saves both time and money – since the user doesn’t need to activate a license from the EDA tool vendors.

    Further, using a dashboard can provide a way for geographically dispersed teams to communicate via a common view of the design. This is a key requirement for any system integration. For example, the chip’s Register-Transfer-Level (RTL) codes are often developed by teams in different geographic locations. Complicating the geographic challenges is the need to incorporate third party-IP and reused internal design blocks with the various RTL designs before the implementation process even begins. This is a problem since the physical layout and design team requires the RTL synthesized code (with all the IP), design planning and place-and-route (P&R) data to decide if the primary chip design constraints can be met.

    Getting the detailed RTL design team to work with the physical layout-design teams as soon as possible encourages communication and successful design practices. It helps mitigate the problems of siloed design activates. Also, a dashboard approach incorporates the essential data metrics from several different EDA tools into one place. This single, global view increases the likelihood of a successful SoC design as well as integrating that design – and the team – with the next level of system development.

    Surprises Abound As Subsystem IP Gains Prominence

    Thursday, February 28th, 2013

    By John Blyler

    What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation.

    SLD: You mentioned that the cost of semiconductor intellectual property (IP) at 20nm and below is increasing. Why is that?
    Wawrzyniak: The reason is complicated. For sure, the cost of hard IP (offered in a GDSII format and optimized for a specific foundry process) at lower nodes will increase due to changes in the actual transistor device—among other things. However, the cost of soft IP wouldn’t necessarily go up because it’s synthesizable (in a high-level language like RTL, C++, Verilog or VHDL). Thus, the cost of soft IP is not really tied to the process node. Still, if an IP vendor needs to devote more effort to developing IP for a non-regular CMOS process, such as a finFet device, then the cost of even the soft IP might increase.

    SLD: Wouldn’t significant changes in the device parameters of the SPICE model cause an increase in the cost of IP?
    Wawrzyniak: There are two cost elements people often confuse when talking about IP. One is the license cost of the IP. The other is the cost to integrate that IP into the device, into silicon. What we are talking about is the licensing cost of the IP, not the integration cost. I would suspect integration costs to continue to rise. The only thing that might stabilize or even decrease the integration costs would be moving toward IP subsystems. The designer will then be using larger pieces of IP as opposed to lots of small discrete blocks.

    SLD: You’re the expert on IP subsystems. Is it a growing market? What are the latest trends?
    Wawrzyniak: More people are using subsystem IP, whether they have created it internally or licensed it from an IP provider like Cadence, Synopsys or others. Overall, I see a rise in that activity.

    SLD: Are verification hooks bundled into the subsystem IP?
    Wawrzyniak: That’s where it gets a little hazy. With subsystem IP, designers license a system-level function such as a communication subsystem. For example, an SoC designer might need several different types of communication protocols, including HDMI, MIPI, etc., for a consumer device. The designer could get all the functions as discrete blocks and throw them together, or he/she could license a complete communication IP subsystem from a vendor as one contiguous block. This subsystem IP block could then be tested in parallel with IP that the designers must create in-house. The verification suites also could be run in parallel on all discrete and system IP blocks. Theoretically, the designer could cut down on his/her total verification effort. If you reduce this effort, then theoretically, you reduce the total cost of integration.

    Unfortunately, if you give a designer more headroom, they often use it all up plus a little extra. So theoretically you may not reduce the cost of the effort at all. Instead, it might end up being more expensive. But in exchange for that incremental increase in cost of integration, you end up with a device that has much more functionality. That is a main driver behind the subsystem concept.

    SLD: The growth of IP continues to outpace the overall semiconductor market growth rate. This refers to blocks of discrete IP. If designers are increasing their use of subsystem IP, would you expect the resulting bundling of IP to cause a decrease in the IP growth rate?
    Wawrzyniak: That might happen, but farther down the road. We are just beginning to see actual commercial subsystem products and licenses. So that effect, if it happens at all, will not happen for quite some time.

    SLD: Sensors are being incorporated into every imaginable device. Are you seeing any growth in the sensor IP market?
    Wawrzyniak: The problem is that most sensors are based on a MEMS process. For sensors to be a viable market where you can license the function, you have to have access to a MEMS process technology. That part of it hasn’t evolved yet. Instead, most designers that use sensors in cell phones and the like buy a MEMS chip that contains all the sensors. These companies buy the chip from a vendor that has access to the MEMS process and puts all of the sensors into silicon. That’s not the same thing as today’s traditional IP market. I don’t think we are quite at the point where you can actually go out and license sensor IP as IP that can be included into a SoC design—but the time is coming.

    SLD: From your research, what are the major IP growth categories?
    Wawrzyniak: I break the IP market into 10 buckets or categories: memory, CPU, DSP, graphics, analog, interface, logic, chip enhancement, interconnect and security. Each of these IP categories is further broken into licensing, royalty and service revenues. Since people haven’t yet reported for Q4 2012, these numbers are just a forecast for on-chip IP revenues:

    > CPU: $1B
    > Interface: $600M
    > Memory: $400M
    > Other: $1.4B
    > Total IP market = $3.4B in 2012

    An interesting footnote concerning on-chip interface IP is the ongoing and increasing importance of Serializer/Deserializer (SerDes) communication channels. Designers are moving away from parallel connectivity and toward the higher performance of SerDes channels. Most people think of SerDes as a real heavy lifting analog mixed signal (AMS) technology, which it is. But SerDes also has a digital side, which has a MAC and a PHY. Most designers would not contemplate licensing the SerDes PHY from one vendor and the MAC from another. They are optimized to work together. That’s why I include SerDes in the interface and not the analog category.

    SLD: Are the number of cores continuing to increase in mobile devices?
    Wawrzyniak: There is a growing dichotomy between cores that are embedded in devices and cores that are programmable by the user. For example, a smartphone might have a number of well-known cores from ARM, Qualcomm, etc. But behind those publically stated cores are many other embedded cores that the user is unaware of because they cannot get to them—cores from Tensilica, CEVA, Imagination Technologies, and so forth. That trend is only going to increase.

    SLD: Are the major core providers using these embedded cores as part of their subsystem IP?
    Wawrzyniak: That could be. My point is that there is more activity than just the major IP providers. They are the largest players and thus the most well known, the most visible. That’s great. But they are never alone in a device. There are always other embedded cores in the same device doing different functions. That trend will increase.

    In the long term, this means that the number of IP cores being used in devices will go way up. It is already going up but it will go even farther, which again makes the argument for subsystem IP. Why deal with 200 separate IP blocks spread around the device instead of dealing with 10 equivalent subsystem blocks? In terms of functionality, there would be no difference. But from an expenditure of effort, there is a world of difference.