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Behold the Intrinsic Value of IP

Monday, March 13th, 2017

By Grant Pierce, CEO

Sonics, Inc.

Editor’s Note [this article was written in response to questions about IP licensing practices.  A follow-up article will be published in the next 24 hours with the title :” Determining a Fair Royalty Value for IP”].

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Understanding the intrinsic value of Intellectual Property is like beauty, it is in the eye of the beholder.  The beholder of IP Value is ultimately the user/consumer of that IP – the buyers. Buyers tend to value IP based upon their ability to utilize that IP to create competitive advantage, and therefore higher value for their end product. The IP Value figure above was created to capture this concept.

To be clear, this view is NOT about relative bargaining power between buyer and the supplier of IP – the seller –  that is built on the basis of patents. Mounds of court cases and text books exist that explore the question of patent strength. What I am positing is that viewing IP value as a matter of a buyer’s perception is a useful way to think of the intrinsic value of IP.

Position A on the value chart is a classification of IP that allows little differentiation by the buyer, but is addressing a more elastic market opportunity. This would likely be a Standard IP type that would implement an open standard. IP in this category would likely have multiple sources and therefore competitive pricing.  Although compliance with the standard would be valued by the buyer, the price of the IP itself would be likely lower reflecting its commodity nature. Here, the value might be equated to the cost of internally creating equivalent IP. Since few, if any, buyers in this category would see advantage for making this IP themselves and because there are likely many sellers, the intrinsic value of this IP is determined on a “buy vs buy” basis.  Buyers are going to buy this IP regardless, so they’ll look for the seller with the proposition most favorable to the buyer – which often is just about price.

Position B on the value chart is a classification of IP that allows for differentiation by the buyer, but addresses a more elastic market. IP in this category might be less constrained by standards requirements. It is likely that buyers would implement unique instantiations of this IP type and as a result command some end competitive advantage. Buyers in this category could make this IP themselves, but because there are commercial alternatives, the intrinsic value is determined by applying a “make vs buy” analysis. The value proposition of the sellers of this type of IP often include some important, but soft value propositions (e.g., ease of re-use, time-to-market, esoteric features), the make vs buy determination is highly variable and often buyer-specific. This in part explains the variability of pricing for this type of IP.

Position C on the value chart is a classification of IP that serves a less elastic market and empowers buyers to differentiate through their unique implementations of that IP. This classification of IP supports license fees and larger, more consistent, royalty rates. IP in this category becomes the competitive differentiation that sways large market share to the winning products incorporating that IP. This category supports some of the larger IP companies in the marketplace today. Buyers in this category are not going to make the IP themselves because the cost of development of the product and its ecosystem is too prohibitive and risky. The intrinsic value really comes down to what the seller charges.

This is a “buy vs not make” decision – meaning one either buys the IP or it doesn’t bother to make the product. A unique hallmark of IP in this position is that so long as the seller applies pricing consistently, then all buyers know at the very least that they are not disadvantaged relative to the competition and will continue to buy. Sellers will often give some technology away to encourage long-term lock in. For these reasons, pricing of IP in this space tends to be quite stable. That pricing level must subjectively be below the level that customers begin to perform unnatural acts and explore unusual alternatives.  So long as it does, the price charged probably represents accurately the intrinsic value.

Position D on the value chart is a classification of IP that requires adherence to a standard. Like category A, adherence to the standard does not necessarily allow differentiation to the buyer. The buyer of this category of IP might be required to use this IP in order to gain access to the market itself. Though the lack of end-product differentiation available to the buyer might suggest a lower license fee and/or lower to zero royalty rate, we see a significantly less elastic market for this IP type.

This IP category tends to comprise products adhering to closed and/or proprietary standards. IP products built on such closed and/or proprietary standards have given rise to several significant IP business franchises in the marketplace today. The IP in position D is in part characterized by the need to spend significant time and money to develop, market and maintain (defend) their position, in addition to spending on IP development. For this reason, teasing out the intrinsic value of this IP is not as straightforward as “make vs buy.” Pricing is really viewed more as a tax. So the intrinsic value determination is based on a “Fair Tax” basis. If buyers think the tax is no longer “fair,” for any reason, they will make the move to a different technology.

Examples:

Position A:  USB, PCI, memory interfaces (Synopsys)

Position B:  Configurable Processors, Analog IP cores (Synopsys, Cadence)

Position C:  General Purpose Processors, Graphics, DSP, NoC, EPU (ARM, Imagination, CEVA, Sonics)

Position D: CDMA, Noise Reduction, DDR (Qualcomm, Dolby, Rambus)

Why Customer Success is Paramount

Sonics is an IP supplier whose products tend to reside in the Type C category. Sonics sets its semiconductor IP pricing as a function of the value of the SoC design/chip that uses the IP. There is a spectrum of value functions for the Sonics IP depending upon the type of chip, complexity of design, target power/performance, expected volume, and other factors. Defining the upper and lower bounds of the value spectrum depends upon an approximation of these factors for each particular chip design and customer.

Royalties are one component of the price of IP and are a way of risk sharing to allow customers to bring their products to market without having to pay the full value of the incorporated IP up front. The benefit being that the creator and supplier of the IP is essentially investing in the overall success of the user’s product by accepting the deferred royalty payment. Sonics views the royalty component of its IP pricing as “customer success fees.”

With its recently introduced EPU technology, Sonics has adopted an IP business model based upon an annual technology access fee and a per power grain usage fee due at chip tapeout. Under this model, customers have unlimited use of the technology to explore power control for as many designs as they want, but only pay for their actual IP usage in a completed design. The tape out fee is calculated based on the number of power grains used in the design on a sliding scale. The more power grains customers use, the more energy saved, and the lower the cost per grain. Using more power grains drives lower energy consumption by the chip – buyers increase the market value of their chips using Sonics’ EPU technology. The bottom line is that Sonics’ IP business model depends on customers successfully completing their designs using Sonics IP.

Blog Review – Monday, February 13, 2017

Monday, February 13th, 2017

Among this week’s topics: two important announcements: the OpenFog Consortium and IEEE Standard for the Functional Verification Language e; a panel discusses the Internet and beyond; Mentor Graphics applies IoT to PCB design; FASTR accelerates the connected car and why USB is not as easy as 123

The importance of IP blocks is a given, but Rocke Acree, ON Semiconductor, explains how selection also has to consider technology and support tools. The company has collaborated with Hexius Semiconductor to qualify analog IP blocks to reduce design cycles and development time.

There are specific constraints, challenges and design requirements for PCBs designed for the burgeoning IoT market. John McMillan, Mentor Graphics has created a two-part blog focused on this topic.

Doing a quickstep around the topic of USB, Eric Huang, Synopsys, explores verification and FPGA prototyping for best results. He recommends some design rules, a test site, then curiously, throws in some political comment, a film review and dance-related jokes to end the blog.

It may not be an understatement by Rhonda Dirvin, ARM, to say that the day the OpenFog Consortium announced its reference architecture is the day we have all been waiting for. Hyperbole? Possibly not, as it defines how secure, interoperable products should be built – just what the connected world needs. She helpfully includes a link to the architecture, and a heads-up on a presentation at Mobile World Congress in Barcelona, Spain (Feb 27 to March 3).

If there is an award for Most Apt Acronym, the Future of Automotive Security Technology Research (FASTR) consortium, must be a contender. The uncredited Rambus blog reviews the brief history of the consortium, and discusses its recent manifesto, looking at why it is need for a secure, connected vehicle industry.

2017 begins with the publication of IEEE Std 1647 2016, the IEEE Standard for the Functional Verification Language e. of 2017. Efrat Shneydor, Cadence Design, looks at the enhancements which have been made and proficiently summarizes the highlights.

Generic connectivity is not enough – NASA has been designing, building and launching satellite systems with the goal of providing connectivity throughout the world. The concept and realities of the Internet of Space is the panel discussion topic, reported by John Blyler, Chip Design Magazine.

Caroline Hayes, Senior Editor

Blog Review – Monday 07 November 2016

Monday, November 7th, 2016

Browsing the MIT Library; AI and HPC for cancer breakthroughs; FPGAs on Mars; Romancing ISO 26262; It’s IoT conference season; Who’s going to pay?

For smart and connected IoT devices, Intel has introduced the Intel Atom processor E3900 and Ken Caviasca, Intel explains how the series brings computing power nearer to the role of the sensor.

Crash scenes from Mars, as taken by the Mars Reconnaissance Orbiter’s High Resolution Imaging Science Experiment (HiRISE) reveal features previously unseen on the planet. Steve Leibson, Xilinx, explains how we have FPGAs to thank. (For the images, not the crash!)

Ahead of GE’s Minds & Machines Conference (November 15-16, San Francisco) Lane Lewis, Ansys, celebrates the marriage of the Simulation Platform and Predix Platform to create a profitable asset health monitoring and the industrial IoT.

As mobile payment matures, Martin Cox, Rambus Bell ID, identifies that tokenization is becoming a hot topic. His blog explains the role of the company’s Token Gateway as a means to integrate multiple mobile payment schemes. No excuse not to get a round of drinks in now.

Moving automotive and safety into the realm of Dungeons and Dragons, Paul McLellan, Cadence, reviews the recent DVCon Europe and how ISO 26262 – the critical safety standard – became a theme, but not necessarily one to dread and fear or avoid. Like St George, you just have to grit your teeth and tackle it head-on, to find the pot of gold that is critical safety design success.

Fresh from IoT Planet in Grenoble, France, Andrew Patterson, Mentor Graphics, is occupied by two topics – connectivity and security. He shares some interesting thoughts and statistics around these gleaned from the event.

Fascinating insights into the world of bio-medicine and computational bio-medicine are provided by Dr Michael J McManus, Intel. He explains how Artificial Intelligence (AI) and High Performance Computing (HPC) are used by researchers to analyze data and predicts an era of revolutionary cancer breakthroughs, of both drug development structures and genome analytics running on a single Intel cluster using Intel Xeon, Intel Xeon Phi processors and Intel Omni-Path architecture.

There is a fascinating collection of rare books at MIT, exhibited to mark Ada Lovelace Day. For those can’t walk the aisles of the MIT Libraries, Stephen Skuce, MIT Libraries, shows us through some of the collection relating to women who have contributed to science, math and engineering with its annual celebration of the history of women in the STEM (Science Technology, Engineering and Mathematics) subjects.

Caroline Hayes, Senior Editor

Blog Review Monday April 11 2016

Monday, April 11th, 2016

Mbed development board seeks therapy; in praise of HPC; IoT security – can it be improved?; EDAC name change; acquisition fever runs high

Checking and testing safety critical systems can be performed using the Zynq-7000 All Programmable SoC (AP SoC) with dual ARM Cortex-A9 processors, and dual Neon FPUs. Austin, Xilinx, explains the routine.

Therapy from an mbed development board may not threat therapists just yet, but ELIZA, the computer program that simulates a psychotherapist, is now available for the mbed platform. The obvious question to ask Wilfred Nilsen, ARM, is “How do you feel about that?”

Who needs High Performance Computing (HPC), asks Wim Slagter, Ansys. He addresses computing as a strategic asset, scalability benefits and what to do with a server cluster.

The Internet of Things (IoT) security market will be worth $28.90 billion by 2020, yet it is flawed, argues an unattributed blog from Rambus. Interviews with Simon Blake-Wilson and Ted Harrington, Rambus, assess how much ground needs to be made up.

Still with security, Robert Vamosi, Synopsys reports on the Synopsys and Underwriter’s Laboratory (UL) collaboration to create the UL Cybersecurity Assurance Program (UL CAP). The aim is to increase transparency and confidence in the security of network-connectable devices using expertise from both camps.

Looking ahead to the connected car, Andrew Macleod, Mentor Graphics, considers what will be coming together for a centralized processing system, handling communications and autonomous driving functions. The vehicle’s systems will be consolidated, but how best to achieve that is up for debate.

It may take some people a while to adjust, but the EDA Consortium has changed its name to the Electronic System Design Alliance. Gabe Moretti, Chip Design Magazine, looks at the whys and wherefores behind the change and the expertly analyses the Alliance’s expanded charter.

Intel has bought Yogitech, the functional safety company and Ken Caviasca, Intel, looks at what this means for the company and, in particular, its IoT offering.

Still with acquisitions, it is all getting a bit too much for Chris Ciufo, eecatalog, who traces some recent ‘musical chairs’ before focusing on what the Mercury Computer purchase of three Microsemi businesses will meet for the military market.

Caroline Hayes, Senior Editor

Blog Review – Monday, March 21 2016

Monday, March 21st, 2016

Coffee breaks and C layers; Ideas for IoT security; Weather protection technology; Productivity boost; Shining a light on dark silicon

Empathizing with his audience, Jacek Majkowski, sees the need for coffee but not necessarily a C layer in Standard Co-Emulation Modelling Interface (SCE-MI).

At last week’s Bluetooth World, in Santa Clara, CA, there was a panel discussion – Is the IoT hype or hope? Brian Fuller, ARM, reports on the to-and-fro of ideas from experts from ARM, Google, and moderated by Mark Powell, executive director of the Bluetooth SIG.

Of all the things to do on a sabbatical, Matt Du Puy, ARM, chose to climb Dhaulagiri (26,795feet /8161m), described as one of the most dangerous 8,000m mountains. Brian Fuller, ARM, reports that he is armed a GPS watch with cached terrain data and some questionable film choices on a portable WiDi disk station.

Still with extremes of weather, the Atmel team, enthuses about a KickStarter project for the Oombrella, a smart umbrella that uses sensors to analyse temperature, pressure, humidity and light, to let you know if you will need it because rain is coming your way. Very clever as long as you remember to bring it with you. Not so appealing is the capacity to share via social media the type of weather you are experiencing – and they say the Brits are obsessed with the weather!

IoT protection is occupying an unidentified blogger at Rambus, who longs for a Faraday cage to shield it. The blog has some interesting comments about the make up of, and security measures for the IoT, while promoting the company’s CryptoManager.

Still with IoT security, Richard Anguiano, Mentor Graphics examines a gateway using ARM TrustZone, and heterogeneous operating system configurations and running Nucleus RTOS and Mentor Embedded Linux. There is a link provided to the Secure Converged IoT Gateway and the complete end-to-end IoT solution.

Europe is credited as the birthplace for the Workplace Transformation, but Thomas Garrison, Intel. Ahead of CEBIT he writes about the role of Intel’s 6 th Generation Core vPro processor and what it could mean for a PC’s battery life, compute performance and the user’s productivity.

The prospects for MIPI and future uses in wearables, machine learning, virtual reality and automotive ADAS are uppermost in the mind of Hezi Saar, Synopsys, following MIPI Alliance meetings. He was particularly taken with a Movidius vision processor unit, and includes a video in the blog.

Examining dark silicon, Paul McLellan, Cadence Design Systems, wonders what will supercede Dennard Scaling to overcome the limitations on power on large SoCs.

Caroline Hayes, Senior Editor

Blog Review – Monday, February 29, 2016

Monday, February 29th, 2016

ARM and Xilinx Embedded World highlights; Mobile World Congress news; Sensors are on a roll; What makes MIPI?

Ahead of the ARM Cortex-A32 processor announcement at Embedded World and Mobile World Congress, ARM announced its latest real-time processor IP, the ARM Cortex-R8, designed for LTE-Advanced and 5G designs. Neil Wermuller, ARM goes into detail about the Cortex-R8 quad-core, real-time processor, building on the ARMv7-R architecture.

Also at Embedded World, Mentor Embedded teamed up with Xilinx which used demonstrated the Xilinx ZYNQ 7000 platform, hosting a Nucleus RTOS. Andrew Patterson, Mentor, describes how this can be used in advanced driver assistance systems (ADAS)

More power for less dollars is driving demand in the consumer market. Alexandru Voica, Imagination Technologies, explains how the latest additions to the PowerVR series, PowerVR Series8XE meets efficiency and performance requirements.

When someone says “pass the masking tape” do check that it’s not a sensor network. The Atmel team blogs about SensorTape, the MIT Media Lab’s Responsive Environments group project for a sensor network that is on a roll.

Ahead of the MIPI Alliance event (March 7), Hezi Saar, Synopsys looks at what makes up the specification as it moves from the mobile marketplace.

Using a real-life crime to illustrate hazards, ARM’s Simon Segars focused on security at Mobile World Congress in Barcelona, Spain last week, reports Paul McLellan, Cadence. Other areas of interest was virtual reality, and an appearance by F1 racing driver, Lewis Hamilton, under the guise of discussing CAN in vehicles and what street cars could learn from F1.

Still with Mobile World Congress, Gary Bronner, Rambus, is quoted in report of the demonstration there of thermal-enabled lensless smart sensor (LSS) technology, by Rambus Labs. With the capability to replace traditional thermal lenses for IoT in medical equipment, manufacturing as well as the less obvious smart cities and transportation, this is a new approach to imaging, driven by computing rather than optics.

Striving to reduce debug effort and increase productivity is a noble cause, championed by Aditya Mittal, Arrow Devices. He looks at the AX13 system bus and its virtues as well as the company’s PDA tool.

Caroline Hayes, Senior Editor

Blog Review – Monday, February 15, 2016

Monday, February 15th, 2016

Research converts contact lens to computer screens; What to see at Embedded World 2016; Remembering Professor Marvin Minsky; How fast is fast and will the IoT protect us?

The possibilities for wearable technology, where a polymer film coating can turn a contact lens into a computer screen are covered by Andrew Spence Nanontechnology University of South Australia’s Future Industries Institute. The lens can be used as a sensor to measure blood glucose levels to a pair of glasses acting as a computer screen.

If you are preparing your Embedded World 2016, Nuremberg, schedule, Philippe Bressy, ARM offers an overview of what will be at his favourite event. He covers the company’s offerings for IoT and connectivity, single board computing, software productivity, automotive and from ARM’s partners to be seen on the ARM booth (Hall 5, stand 338), as well as some of the technical conference’s sessions and classes.

Other temptations can be found at the Xilinx booth at Embedded World (Hall 1, stand 205). Steve Leibson, Xilinx explains how visitors can win a Digilent ARTY Dev Kit based on an Artix-7 A35T -1LI FPGA, with Xilinx Vivado HLx Design Edition.

Showing more of what can be done with the mbed IoT Device Platform, Liam Dillon, ARM, writes about the reference system for SoC design for IoT endpoints, and its latest proof-of-concept platform, Beetle.

How fast is fast, muses Richard Mitchell, Ansys. He focuses on the Ansys 17.0 and its increased speeds for structural analysis simulations and flags up a webinar about Ansys Mechanical using HPC on March 3.

If the IoT is going to be omnipresent, proposes Valerie C, Dassault, can we be sure that it can protect us and asks, what lies ahead.

A pioneer of artificial intelligence, Professor Marvin Minsky as died at the age of 88. Rambus fellow, Dr David G Stork, remembers the man, his career and his legacy on this field of technology.

I do enjoy Whiteboard Wednesdays, and Corrie Callenback, Cadence, has picked a great topic for this one – Sachin Dhingra’s look at automotive Ethernet.

Another thing I particularly enjoy is a party, and Hélène Thibiéroz, Synopsys reminds us that it is 35 years since HSPICE was introduced. (Note to other party-goers: fireworks to celebrate are nice, but cake is better!)

Caroline Hayes, European Editor

Blog Review – Monday, August 31, 2015

Monday, August 31st, 2015

HPC for cancer analysis; body power: game on for animation; DDR challenges; aviation fascination; packaging checks; Arrow explains USB3.1; IDF meets IoT

It would take 5.6Exabytes to synchronize the data of the 14million cancer patients worldwide, just once, points out Kristina Kermanshahche, Intel. She explains how Intel’s HPC is a helping scientist access and share data, with relationships such as Pan-Cancer Analysis of Whole Genomes, and at the German Cancer Research Centre (DKFZ) and the European Molecular Biology Laboratory (EMBL).

Distasteful things like a body’s sweat could charge phones, speculates Catherine Blogar, Dassault Sytemes. She speaks to some experts in wearable and implantable engineering for some futuristic power advice.

Some helpful tips on creating animation is offered by Laura Mengot, ARM, in her blog. Although the software used is Autodesk Maya and Unity, Mengot says that the detailed, illustrated theories are applicable to any 3D engine and game engine.

Ely Tsern, Rambus, identifies five trends in server memory and speculates on DDR4 capability in particular, and even beyond to DDR5.

Welcoming the RTCA/DO-254 (Design Assurance Guidance For Airborne Electronic Hardware) standard, Graham Bell, Real Intent, delves into what it means for verification tools.

Reminiscing about a European design classic, Nazita Save, Mentor Graphics, remembers Concorde. Pre-CAD modification and with no CFD software, how did they do it?

While end users may love smaller package sizes, they are a headache for manufacturers. IC Packaging Pros, Cadence, discuss layout tools for validating and verifying, with some easy-to-follow advice.

Four bloggers contribute to the latest update to USB3.0. Anand Shirahatti, Thejus Shanbhogue, Kanak Singh, Deepak Nagaria, Arrow, discuss the implementation and verification challenges – with a link to a USB3.0 vs USB3.1 USB cheat sheet thrown in.

Richard Solomon appears confused as to what day it is, but makes up for it with a round up of what’s what at this year’s IDF, from characters encountered, travel tips to his own takeaways from this month’s event in San Francisco.

Blog Review – Monday, May 04 2015

Monday, May 4th, 2015

Steve Leibson, Xilinx, reports on an interesting academic program to ‘look at, poke, modify, and experiment with’ the MIPS RISC processor RTL using a simplified Imagination Technologies microAptiv processor core. The MIPSfpga program provides university CS and EECS departments access to a fully-validated, current generation MIPS CPU. There are also plans for the Imagination University Programme to expand this university program to the PowerVR graphics processors and FlowCloud IoT technology.

Two ARM server hardware platform used in cloud-based set-top box systems are explained in detail by Karthik Ranjan, ARM. The blog looks back at early cable TV systems and looks ahead to the IoT and cloud use in virtual network functionality (VNF) ahead of the VNF world Congress in San Jose this week.

In praise of an overlooked object-oriented language, Ruby, Michael Cizl, IP Extreme, presents a strong case and urges readers to rethink their choices.

Excitement is growing for the advent of Windows 10. Rambus speculates on the inclusion of a universal sensor driver set for environmental, biometric, proximity and motion sensing. Adam Shah, IDG, speculates on what this will mean for functionality for devices running the OS.

Wrestling with power, the panel of experts at the Electronic Design Processes Symposium, discussed if the industry needs to rethink tackling power for IoT devices in particular. Brian Fuller, Cadence, reports from the Monterey event.

Distilling a report from IHS Automotive, John Day, Mentor Graphics, identifies apps and trends that smartphones will bring to the in-car experience, from Apple to Android, with a graph of consumers’ preferences from Bluetooth for hand-free use, touchscreen to an auxillary hook to add an MP3 player or phone.

Returning to a familiar blog-topic, Michael Posner, Synopsys, compares hybrid prototyping vs prototyping bridges, using the company’s latest DesignWare Hybrid IP Prototyping Kits as a starting point for the IP prototyping discussion.

Caroline Hayes, Senior Editor.

Blog Review – Monday April 20, 2015

Monday, April 20th, 2015

Half a century and still quoted as relevant is more than most of us could hope to achieve, so the 50 anniversary of Gordon Moore’s pronouncement which we call Moore’s Law is celebrated by Gaurav Jalan, as he reviews the observation first pronounced on April 19, 1965, which he credits with the birth of the EDA industry, and the fabless ecosystem amongst other things.

Another celebrant is Axel Scherer, Cadence, who reflects on not just shrinking silicon size but the speed of the passing of time.

On the same theme of what Moore’s Law means today for FinFets and nano-wire logic libraries, Navraj Nandra, Synopsys, also commemorates the anniversary, with an example of what the CAD team has been doing with quantum effects at lower nodes.

At NAB (National Broadcasters Association) 2015, in Las Vegas, Steve Leibson, Xilinx, had an ‘eye-opening’ experience at the CoreEL Technologies booth, where the company’s FPGA evaluation kits were the subject of some large screen demos.

Reminiscing about the introduction of the HSA Foundation, Alexandru Voica, Imagination Technologies, provides an update on why heterogeneous computing is one step closer now.

Dr. Martin Scott, the senior VP and GM of Rambus’ Cryptography Research Division, recently participated in a Silicon Summit Internet of Things (IoT) panel hosted by the Global Semiconductor Alliance (GSA). In this blog he discusses the security of the IoT and opportunities for good and its vulnerabilities.

An informative blog by Paul Black, ARM examines the ARM architecture and DS-5 v5.21 DSTREAM support for debug, discussing power in the core domain and how to manage it for effective debug and design.

Caroline Hayes, Senior Editor

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