Analog and mixed signal IP began closing the gap with digital core IP in design explorations in the first two months of this year, a clear sign that multicore systems on chip have emerged as the dominant semiconductor model and that the architecture requires both types of IP.

While it’s too early to tell this year what effect that will have on overall design activity—the economy is the real determining factor there—the convergence is pronounced. In January, when chip design exploration typically is at its lowest even in a good year, there were 894 digital IP core explorations vs. 427 for analog and mixed signal. Last month, the number for digital had grown to 2,729 while those for analog/mixed signal had increased to 2350.

Off-chip interface IP also is becoming important, although to a far lesser extent. Much of that work is still being done by hand, but many industry insiders believe that approach will change over the next couple of process nodes as design engineers are called upon to add more context to their designs, including software applications and application interfaces, as well as connections at the board level. The exploration with off-chip interfaces was 211 in February, up from 75 in January.

On chip bus IP activity, meanwhile, was 173 in January vs. 327 in February, and verification IP—still in emerging market mode—showed 9 investigations in January and 28 in February.

January (blue) vs. February design investigations.

–Ed Sperling

One of the subtle differences hidden in global design data is exactly when design starts peak in various regions around the globe. While the total number of designs remains relatively consistent, the activity in each area does not.

In Asia, for example, the biggest months are at the beginning of the year and between May and July. In Europe, the numbers are highest at the beginning of the year, with moderate activity in April, May and June. And in North America, design activity typically starts strong at the beginning of the year and peaks in May, July and September, just in time for fourth-quarter delivery of products.

While this is likely to become skewed in 2009 because of the downturn, there are a couple of interesting trends at work here that persist from year to year in normal growth years. First of all, much of the design work in North America and Europe is done at similar times and is of similar types, except that European workers typically take their vacations during the summer months. In North America, design continues even if some of the team is on vacation.

In Asia, many of the designs are tied into local markets, which run on a different schedule. The biggest retail months in China are in November, during the national holiday, and during the Lunar New Year. Those designs aimed at export markets typically have been less technologically advanced or narrower in focus than many designs out of Europe, North America and Japan.

–Ed Sperling

By John Blyler

Total chip power trends in architectural designs are murky, while economic numbers are crystal clear.

That makes it far more difficult to find meaningful technology trends in these times of economic instability, even though economic numbers can greatly influence chip power trends. Engineers would say that the signal-to-noise ratio (S/N) is just too low, meaning that the signal (useful information) is still there but it’s barely discernible from the noise.

For example, consider the latest total chip power trends that result from pre-silicon, architectural-level investigations. These investigations or trade-off studies will eventually lead to an actual IC project.  Figure 1 below shows which ranges of power (in watts) have been of critical interest to chip architects over the last three years. Up until mid-2008, there was clear interest in chips that had a total power budget of less than 0.11 watts and those between 1 and 4 watts. This latter range coincides with the total power usage of handheld wireless devices, such as mobile phones.

Figure 1

Since the middle of last year, however, it is not as clear which power ranges are of the most interest to the designers of future chip products. For one thing, the number of overall chip investigations – a precursor to actual chip starts – is down considerably. This coincides with the ongoing downturn in the semiconductor industry and overall global economy. This decrease in numbers contributes to the difficulting in reading future trends in total chip power design – at least for the near term.

Economic trends may be somewhat easier to discern, especially if you follow the right metrics. For example, analysts at e-forecasting.com recently said the leading indicators for both chips and chip making equipment fell in November in North America. These indicators are a composite of components that included interest rate spread, productivity measures, changing profit margins and more.

The North American chip sales indicator declined by 2.7 percent in November. (See Figure 2) Not surprisingly, the chip equipment sales indicator declined by 3.5 percent in the same month.

Figure 2

The “murkiness” of lower numerical values for all data types – e.g, all architectural power ranges – means that it is difficult to discern which trends are about to rise about the noise floor. Using sensitivity models designed to clear up this murkiness are one way to see trends more clearly. This will be my strategy going forward.

AI used to be the stuff of science fiction, but cheap processing power and storage has made it a reality. To find out what’s being developed, System-Level Design (www.chipdesignmag.com/sld) tracked down Rachel Goshorn, assistant professor of System Engineering at the Graduate School of Engineering and Applied Science in the Naval Postgraduate School in Monterey, Calif. Check out what she has to say.

By Ed Sperling

In the chip world it’s beginning to look like the erosion of the middle class, or at least the middle tier.

The bulk of companies working in the semiconductor industry—from design to development—have annual revenues of either less than $10 million (26.2%) or more than $500 million (25.4%). The number between $10 million and $100 million is only 12.8%, while the number between $100 million and $500 million is only 8.8 percent.

These numbers reflect several important trends in the chip design world. First, there are far fewer IPOs than in the past, making the exit strategy for investors less clear cut. That, in turn, limits the number of new companies being started, particularly in the United States, Europe and Japan.

Second, companies that do achieve enough mass to hit the radar screen—usually with successful products and unique technologies—often become acquisition targets for larger companies. These acquisitions are not always amicable, though, which has made integration and assimilation much more problematic than simply acquiring a technology or a technology team and developing technology in-house.

Third, the table stakes for getting into the system-level design world are much higher than in the past. Technology is more complex, and often it is the integration of more than one piece that makes it attractive to potential customers. While chip chip design and development always seems complex compared with what came before—everything from lithography to substrate materials, packaging, gate design and tradeoffs between power and performance—solving these issues can no longer be done serially. Architects can no longer just pass the concept to the designers, who in turn pass it along to the developers and verification engineers, and then pass it along to the software coders.

Finally, despite the perpetual development of new technology, the chip design world is maturing. That is marked by relatively stable single-digit growth by companies in good times, and fewer entrants into a market. While the industry is still viable, with enormous opportunities for players in the industry, the number of companies entering the field will be limited until there is a radical shift in technology, which usually happens when something is broken or there is a huge demand for new technology.

The data also shows that the bulk of the pre-design activity was done by the design engineers, who accounted for 44.6% of all work. Engineering and executive management entered into 20.1% of all decisions, a reflection of how much money it now costs to develop a new chip.