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Posts Tagged ‘S2C’

S2C SPEEDS FPGA PROTOTYPING AND INCREASES SCALABILITY

Tuesday, October 25th, 2016

Gabe Moretti, Senior Editor

ARM has always done an outstanding job in providing support for its processors.  In the specific case of the ARMv8-A processor its Prodigy interface has been used by S2C to create a development environment that allows engineers to configure FPGAs in the system.

The Prodigy Interface Module for ARM Juno works with the ARM Juno Development Platform and Prodigy Logic Modules to speed up and increase scalability of FPGA prototyping for designs based on ARMv8-A. The Prodigy Interface Module for Juno effectively bridges the software development environment to the S2C’s Prodigy Logic Modules for prototyping custom logic blocks alongside the ARM processor.

The ARM Juno Development Platform includes the Juno Versatile Express board and an ARMv8-A reference software port available through Linaro Linux. The Prodigy Interface Module for Juno works seamlessly with the Prodigy Complete Prototyping Platform that includes advanced capabilities for design partitioning, prototype configuration, multi-FPGA debug, and the ability to scale beyond 1.5B gates utilizing the Prodigy Cloud Cube architecture.

Prodigy Interface Module Kit for ARM Juno includes the following:

  • One Prodigy Interface Module for Juno
  • One I/O loopback test module for ARM Juno
  • One 8GB DDR4 Pre-tested SO-DIMM Memory Module
  • One 400mm Prodigy Cable
  • One reference design for Juno, tutorial guide and application note

The kit also includes a complete easy set up reference design that shows:

  • Comprehensive self-testing between the Prodigy Logic Modules and the Juno ARM Development Platform
  • Expanded FPGA capacity
  • Early porting of OS kernel or driver code for ARMv8-A processors
  • High-speed DDR4 memory access between the Logic Module(s) and Juno ARM Development Platform

S2C Additional capabilities

S2C Inc. has announced the availability of its Prodigy Juno ARM Interface Module. The module works with the Juno ARM Development Platform, speeding up and increasing the scalability of FPGA prototyping for designs based on ARMv8-A architecture. The Prodigy Juno ARM Interface Module effectively bridges the software development environment to S2C’s Prodigy Logic Modules, for prototyping custom logic blocks alongside the ARM-based processor.

The Juno ARM Development Platform includes the Juno Versatile Express board and an ARMv8-A reference software port available through Linaro Linux. The new system includes advanced capabilities for design partitioning, prototype configuration, multi-FPGA debug, and the ability to scale beyond 1.5B gates utilizing the Prodigy Cloud Cube architecture.

S2C provides a complete easy set up reference design as part of the Prodigy Juno ARM Interface Module package. It connects S2C Prodigy Virtex UltraScale and Kintex UltraScale Logic Modules with the Juno ARM Development Platform. The reference design shows:

1)      Comprehensive self-testing between the two environments

2)      Expanded FPGA capacity

3)      Early porting of OS kernel or driver code for ARMv8-A processors

4)      High-speed DDR4 memory access between the Logic Module(s) and Juno ARM Development Platform

Figure 1: The integrate system showing both ARM and S2C subsystems

“Within the ARM ecosystem our partners are developing larger and more complex designs that require advanced prototyping tools,” said Vincent Korstanje, vice president of marketing, systems and software group, ARM. “Our collaboration with S2C will help partners to verify these designs and accelerate software development using the Juno ARM Development Platform.”

The Prodigy Juno Interface Module is available now for the Prodigy Virtex UltraScale Logic Module series.

Choosing the Best Pin Multiplexing Method

Tuesday, September 13th, 2016

Gabe Moretti, Senior Editor

S2C has recently published a white paper “Choosing the best pin multiplexing method for your multiple-FPGA partition”.  You can read the entire paper at www.s2cinc.com/resource-library/white-papers.  I think that a portion of the paper is interesting enough on its own merit to be published separately.

Using multiple FPGAs to prototype a large design requires solving a classic problem: the number of signals that must pass between devices is greater than the number of I/Os pins on an FPGA. The classic solution is to use a TDM (Time Domain Multiplexing) scheme that muxes two or more signals over a single wire or pin (Figure 1).

Figure 1   Signals Multiplexed with a Fast Clock

This solution is still widely employed, and coupled with the advances in FPGAs, the obstacles to constructing a multi-device prototype are greatly reduced. The latest FPGAs offer advantages such as a very high number of industry-standard I/O, integrated high-speed transceivers, and LVDS (Low Voltage Differential Signaling) signaling.

Single-ended Signals vs. LVDS

Single-ended TDM uses a single-ended signal which can transmit physical signals at a speed up to 290 MHz (Virtex UltraScale). This is determined by dividing the TDM ratio (or signal multiplexing ratio) and taking into account setup, synchronization and board delays.

With a TDM ratio of 4:1, the system clock speed will be around 17.8 MHz. If the TDM ratio is increased to 16:1, the system clock speed will drop to less than 10 MHz. From this we can see that as the TDM ratio increases, the performance drop linearly.

However, using the LVDS I/O standard supported by Xilinx FPGAs, the physical transmission data rate between FPGAs can achieve up to 1.6 Gbps. This offers tremendous advantages over single-ended transmission, even when considering that a single LVDS signal requires a pair of single-ended pins.

Figure 2    Single-Ended TDM and LVDS TDM performance with Asynchronous mode

Figure 2 shows a comparison between Single-Ended TDM and LVDS TDM using Xilinx UltraScale devices. (Note: performance for different FPGA families vary.) Performance of TDM implemented with LVDS is better than Single-Ended TDM, especially for higher TDM ratios.

Figure 3 shows another comparison of Single-ended TDM and LVDS TDM. It shows the number of physical I/O needed to accommodate a given number of virtual I/O, assuming a system speed of 11 MHz:

Figure 3 Number of physical interconnections needed for a system running at 11MHz

This shows that for a system with a clock speed of 11 MHz, if 12800 virtual connections are needed, single-ended TDM consumes 1600 physical I/O. With LVDS TDM, this number is cut in half to 800.

Given the physical I/O limitation of FPGAs, partitioning becomes easier if less physical interconnections are needed. LVDS TDM has clear advantages over traditional Single-Ended TDM.

Partitioning and Automatic TDM Insertion

Combining the technique of using asynchronous LVDS TDM with a single clock cycle design, it’s possible to create a tool that can partition a design and perform automatic TDM insertion. Ideally, such a tool would be able to:

  • Optimizes buses and match the LVDS resources in each bank considering such factors as trace lengths, matching impedances, and impedance continuity.
  • Avoid consuming FPGA design resources for the TDM circuity by taking advantage of built-in reference clocks (e.g.: IODELAY) to drive TDM clocks and resets

S2C’s Prodigy Play Pro is a tool that provides design partitioning across multiple FPGAs, and offers automatic TDM insertion based on an asynchronous TDM using LVDS.

FPGAs for ASIC Prototyping Bridge Global Development

Wednesday, July 20th, 2016
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