By Ed Sperling
Apache Design uncorked the next release of its RedHawk power signoff environment, this one geared for sub-20nm and stacked die for designs with more than 3GHz performance and billions of gates. The fact that tools are starting to roll out for 3D ICs is key for moving this design, packaging and re-use scheme forward.

Cadence introduced TripleCheck IP Validator, the latest addition to its verification IP catalog for compliance testing of interface IP. The company also announced availability of its OrCAD Capture Marketplace for its OrCAD and Allegro PCB community through a desktop browser.

Samsung rolled the industry’s first hardened ARM Cortex A-15 SoC utilizing Synopsys’ IC compiler for place and route of the 32nm chip. The chip is based on Samsung’s LP process using high-k/metal gate technology. ARM’s A-15 is its most power processor core yet, and one that it has positioned squarely against Intel.

By Ed Sperling
Synopsys issued a barrage of announcements, including new products, new relationships, and a new win. The company unveiled its next-generation verification IP based on its new VIPER architecture, with native support for OVM, UVM and VMM. Synopsys claims up to 4x performance over other commercial VIP. This is an interesting number, and likely will spark a volley of announcements from the other Big Three EDA vendors, all of which have been gearing up for what they see as a big opportunity in the VIP space. Synopsys also rolled out 28nm M-PHY IP that supports six different standards for mobile applications.

On the relationship side, Synopsys struck a deal with Arteris to jointly develop an IP solution based on the Low Latency Interface, which cuts the cost of the bill of materials by eliminating a memory chip and reducing the area of a PCB. In a related move, Arteris introduced its low-latency interface digital controller IP, which it says is already silicon-proven in TI’s OMAP platform.

Synopsys also is working to link Springsoft’s debug technology with its own Protocol Analyzer. It also won a deal with BiTMICRO for a slew of EDA tools.

Samsung teamed up with Mentor Graphics to create a DFM sign-off reference solution for Samsung’s foundry. This opens the door to a couple of other big deals for Mentor, as well, considering Samsung is one of the three main companies in the Common Platform. The others are GlobalFoundries and IBM.

Mentor also announced its Q4 financial results, which set a new record. Revenues for the quarter were $320.4 million, up from $307.3 million in the same period in 2011. For the 12 months ended Jan. 31, revenue was $1.015 billion—also a record—up from $914.8 million in fiscal 2010. Net income for Q4 was $57.8 million, up from $50.6 million in Q4 2011, and for the year it was $83.9 million, compared with $28.6 million the previous year. Mentor expects revenue to increase to about $1.1 billion this year.

Cadence unveiled the production release of a virtual platform for Xilinx’s Zynq-7000, which is based on the ARM Cortex-A9 MPCore. After years of EDA companies trying to gain a strong entry into the FPGA world, this is an interesting doorway.

Docea Power rolled out a new tool for architectural-level power and thermal analysis. Given the fact that the biggest savings in power and heat can be obtained at the earliest stages of a design, this is an important step forward. The next challenge is to implement this kind of capability into existing flows so that power and heat models can be integrated easily with other models. Functionality and performance are no longer enough.

Tensilica introduced its second-generation multimode baseband chip, which includes multiple dataplane processors. The chip was co-developed with NTT DOCOMO, Fujitsu, Panasonic and NEC.  Tensilica also rolled out Dolby Digital Plus for surround sound on its HiFi Audio DSPs, and it struck a deal with ClariPhy, which will license Tensilica’s dataplane processors for optical networking mixed signal processing.

By Ed Sperling
It was a good week for emulation. Mentor Graphics joined forces with MoreThanIP to create emulation solutions for multi-gigabit Ethernet SoCs.  Mentor also won a deal from ZTE for its Veloce emulator, and it added emulation solutions for USB 3.0 products.

Cadence and Samsung have developed a 32nm HD digital camera SoC for Ambarella, which has been creating digital still cameras with high-definition video capabilities. Translation: lots and lots of pixels. Cadence also teamed up with Xilinx for system design, software development and testing of Xilinx’s Zynq platform. And Cadence announced its quarterly numbers, showing net income of $28.1 million for the quarter ended Oct. 1 ($37.3 million non-GAAP) vs. $126.8 million in the same period in 2010 ($11.2 million non-GAAP). Revenue for the quarter was $292 million vs. $238 million in 2010.

eSilicon inked a deal to use Synopsys’ Custom IC design solution for 28nm SoCs. And Synopsys’ DesignWare Audio IP achieved first-pass silicon for 65nm and 55nm process technologies from multiple foundries.

Open-Silicon launched an ARM Center of Excellence to provide complete SoC development solutions for low-power chip development for the networking, telecommunications storage and computing markets. This is becoming a very cozy relationship. Open-Silicon already has a multi-year licensing agreement in place with ARM.

Atrenta introduced early PPA analysis for ARM’s AMBA designer using its SpyGlass and GenSys products.  Atrenta also joined Cadence’s System Realization Alliance, which is no surprise considering it was one of the first to adopt Cadence’s EDA360 terminology.

Arteris won a deal from VIA Telecom for its high-speed inter-chip communications IP between mobile phone baseband chips and application processors.

Tensilica won a deal from EnVerv, which licensed Tensilica’s ConnX DSP cores for its smart grid power line communications SoCs.

By Ed Sperling
A series of recent announcements by the Big Three EDA vendors and their well-known partners from across the disaggregated SoC ecosystem is lending new credence to the impact of collaboration.

While IDMs such as Apple, Intel, Samsung and IBM continue to blaze their own trail, developing in-house tools, methodologies, processes and chips, fabless companies working with foundries and tools developers are beginning to show some of the same benefits for a much lower cost.

One such effort involves Cadence, ARM and TSMC, which together unveiled a 20nm Cortex A-15 chip. Mike Inglis, executive vice president and general manager of ARM’s processor division, said teams from each company worked closely together to find out what was broken on the process side, then fed that information back into performance optimization and packaging and worked it into the design flow.

“This is how you more easily get to a more optimized solution more quickly,” Inglis said. “It also enables the leading edge and the trailing edge to get to market more quickly.”

This is what IDMs have always done, taking information back and forth between the design teams and the fab and adding tweaks all along the way. But what’s changing is that fabless companies appear to be catching up more quickly than most industry observers believed was possible.

“We’re seeing collaboration that is both horizontal and vertical,” said Lip-Bu Tan, president and CEO of Cadence. “Horizontal involves industry standards among peers and does not differentiate end products. With vertical collaboration, the goal is an end product that is differentiated, whether that involves IP, EDA, the foundry or software.”

Mentor Graphics, meanwhile, rolled out the next version of its Nucleus real-time operating environment that was developed with partners such as Texas Instruments, GCT and Stonestreet One. In a move aimed at conserving power, Mentor has moved some of the power management capabilities such as dynamic voltage and frequency scaling into the kernel of the RTOS, according to Jan Klube, director of the Nucleus product line.

“The software design was built into the application from the beginning versus folding complexity onto the application,” said Klube. “So developers get a simple power management API and a power-aware RTOS.”

One of those developers is TI, which has been working with Mentor as well as ARM for its Stellaris microcontrollers. Miguel Morales, worldwide marketing manager for the MCUs, said the microcontrollers are sold with pre-written software wrapped up in kits.

“Collaboration will have to accelerate,” said Wally Rhines, Mentor’s chairman and CEO, who noted that Mentor is also working with TSMC on “reliability” kits. He added that it will be critical to respond together to new and emerging problems, particularly with stacked die where stress, thermal and parasitic effects will create as-yet unknown issues.

Synopsys, meanwhile, has been working closely with TSMC and ARM to improve yield and deal with process variations.

“As we look ahead, there is the notion that an upstream tool can know what a downstream tool must do,” said Aart de Geus, chairman and CEO of Synopsys. “We need to be able to move forward to place and route before we finish synthesis, and we need to be able to question why we should do all the work if an issue is not resolvable.”

De Geus noted that collaboration is the answer to systemic complexity. “We must be committed, and we will need to collaborate with partners that have competence.” He added that there also is a need for quick compromise, balancing a “great enough” solution against a better one that will take longer to develop.

By Ed Sperling
Mentor Graphics rolled out its Pyxis custom IC design platform, signaling that it has fully digested and integrated its acquisition last year of Pyxis, which made AMS routing tools. What’s particularly interesting is that Mentor says the new platform is tightly integrated with 2.5D interconnect parasitic extraction, taking yet another step alongside its role in test to position itself in the stacked die world.  Mentor also unveiled a new program for embedded software development that includes both professional services and a suite of tools for Linux, Android, open-source toochains and user interface product and design services.

Synopsys uncorked the next version of its LightTools for illumination analysis for the lighting industry. The focus will be on lighting and solar designs, which are both rapidly growing markets. Being able to apply advanced CAD tools to these sectors should produce some interesting results.

A standard for sharing memory between two chips, which was jointly developed by Arteris and Texas Instruments, has been licensed by 10 SoC vendors in the mobile and wireless markets. You might recognize some of these names: Intel, Samsung, LG, ST-Ericsson, HiSilicon and VIA Telecom.

Ansys’ proposed acquisition of Apache Design Solutions got a boost when the U.S. Justice Department and the Federal Trade Commission reduced the waiting period for the deal. The acquisition is expected to close next quarter.

TSMC issued its Q2 earnings report. Revenue was up 6.5% from Q1 and 16% year over year (in U.S. dollars). Net income was down 0.9% from last quarter. What’s most interesting in the earnings report, though, is the outlook. The company says the “global economic condition has weakened in the last few months,” adding volatility into the supply chain and impacting the demand for wafers next quarter. Consumer and computer sements are expected to decline while the industrial/standard segment will increase.

By Ed Sperling
Cadence acquired Azuro, which develops tools for clock concurrent optimization, aka coopt. Azuro claims it can reduce clock-tree power by up to 30% and overall system power by 10%. Given the increasing number of clocks in SoC designs, this can only be a good thing. Terms of the deal were not disclosed, meaning it wasn’t significant enough as a percentage of Cadence’s revenue to actually report.

For anyone who’s been contemplating the future of double patterning, strain engineering and eventually stacking of die, this stuff is no longer just theoretical. Samsung used Cadence’s Encounter-based flow to tape out a 20nm test chip. Samsung also used Synopsys’ IC Compiler and IC validator for in-design physical verification to get that test chip out.

Synopsys also is working with GlobalFoundries to deliver interoperable process design kits later this year at advanced nodes. 65nm G and enhanced low power (LPe) kits are available now.

Cavium licensed Arteris’ FleNoC interconnect IP for its processors. Given the complex interconnect tradeoffs in an SoC, this is a recognition by a mainstream processor company of how to deal with trouble spots in the future, namely plan for them.

Germany’s Dream Chip Technology inked a deal to become a Tensilica design center, supporting Tensilica’s processor core IP. Dream Chip makes SoC, FPGA and embedded software designs.

TSMC’s net sales shrank 0.9% between May and June, but they were up 1.5% year over year for that period.

By Pallab Chatterjee
Mobile devices today are optimized for low- to mid-bandwidth data transmission, which is sufficient for e-mail, batch downloads of applications and music, and playback of encoded/compressed streaming video. But in coming months they will add another feature—image capture and processing and advanced graphics processing.

This adds a whole new wrinkle to mobile devices, which have focused more on simply downloading and displaying data—particularly at low power—than on the quality of the display and user experience—both of which require significantly higher performance.

The semiconductor industry from its inception was driven by increasing performance and increasing device density. In the past decade, the realization that power was not unlimited and needed to be part of the design constraint, has changed the direction for processors and memory structures. This swing to ultra low power is now swinging back to a combination of performance and low power.

Mobile devices are now falling into the following bins: single-processor smartphones for email/Web surfing/music/simple apps, and dual-core processors for the new high-res business class smart phones and the current line of tablets. These dual-core systems also are being used to run new gaming software with higher-resolution graphics, more movement and action in the games (not just side scrolling) and more advanced sound or motion control. This advanced software, just like on the PCs and console platforms, is required to meet user demand for even more advanced experiences, but that requires even more processing power.

That explains why the next-generation tablet processors are quad-core systems. Nvidia is currently ramping a quad-core Tegra chip, which is both performance and power optimized. The quad core allows not only for multitasking with the Android operating system, but also for high performance graphics for single tasks. The new processor is power optimized to provide the same net battery operation life as the dual core, while displaying both streaming video and high-resolution gaming.

Mobile devices have added image capture (cameras) in the past. The new generation has both outward and user (inward) facing cameras, and some have three cameras so the outward facing supports Stereo3D images. To address this level of image capture, both still and video, suppliers like Samsung are providing local image processing control circuits. These circuits handle the image stabilization, focus, zoom, white balance, among other image cleanup functions.

A new function of these mobile systems is to not only capture the image, but also edit the data. This involves intense graphics processing to provide color changing, cropping and overlay for still images. For video it requires rudimentary title insertion, NLE functions, cut and paste, and most important, encoding the edited file to a playable format.

For the gaming environment, the mobile platforms have to write code specifically for the video cores. This direct control is to be able to minimize latency and control the power management options of the graphics chip. The current methods for 2D and dimensional 3D games involve creating Open GL and Stereoscopic 3D with Open CL.

Finally, for storage in the mobile devices, the method of choice is solid state disk (SSD) technology. These devices dominate with the SATA II interface at this time. The high speed SATAIII (6Gb/s interface) is not really used in mobile devices due to power consumption issues. The SATA format gives the developer the ability to use a known timing model for the disk interface, and the SSD provides a minimum systematic latency for the disk access. The SSD has far superior power over a traditional rotating media HDD and is fairly independent on performance from single through quad core processors.

By David Lammers
Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied.

Now that Intel has come out of the closet with its tri-gate technology, “the foundry customers are all going to ask, ‘When am I going to get a FinFET? What does it look like?’” said one source, who asked not to be identified.

What they may find is a transistor that is rather difficult to build, at least for the companies that lack the resources to make the jump from planar to vertical structures. “Intel’s competitors will all be taking that thing (the tri-gate device) apart. They will learn from it. They will catch up, but it is not automatic and takes time. Intel has shown its technology leadership, but of course they have to invest an enormous amount of money to stay ahead and the competitors have to spend a much smaller amount to copy,” the source said.

Opinions differ on how quickly finFETs will enter the SoC space. At the Intel tri-gate rollout, Intel architecture general manager Dadi Perlmutter said Intel’s goal is to achieve “parity,” rolling out MPUs and SoC products on the latest technology at the same time. The lag is declining node by node, he said.

Planar vs. FinFET

Analyst Nathan Brookwood, sees Intel introducing tri-gate-based, 22nm, Atom-based SoCs for smartphones and tablets in the fourth quarter of 2012. Those “Silvermont” SoCs would be supplanted in 2014 by the 14nm-based “Airmont” SoCs. If that scenario proves accurate, Intel will be on the market with Atom-based and MPU products at the same time in 2014.

If Intel meets its target, and if TSMC rolls its finFET technology in 2015 at the 14nm node, at least two companies would be on vertical transistors for SoCs. There is speculation that TSMC might pursue a planar transistor for low-cost applications at the 14nm generation, using finFETs for the high-performance graphics MPUs, FPGAs, and others. And some believe that Intel will be more active in the foundry space, partly as a way to monetize the estimated $2 billion it took to develop the 22nm tri-gate technology.

Dean Freeman, a manufacturing technology analyst at Gartner Inc., said Intel’s tri-gate technology is impressive. “However, the SOI group won’t give up any ground.” The SOI consortium is working closely with ARM to demonstrate lower power consumption, at 1 to 2 GHz performance, for smart phones. But Freeman said most of those smartphone chips are produced on bulk wafers today, and they will be reluctant to spend much on the additional wafer cost represented by UTB-SOI wafers. Even AMD has switched to bulk (non-SOI) technology for its low-cost Fusion products, he noted.

On the other hand, Freeman said the vertical devices require a big change in the design tools, and a complete redesign of a company’s proprietary intellectual property. “Not all devices need 3D. Tri-gate will be used for Intel’s X86 products, and IBM will go 3D for its high-performance devices. Some high-performance ASSPs might need 3D as well. I am not certain about the ARM devices,” he said.

Gary Patton, an IBM vice president who manages the Fishkill Alliance including Samsung, Toshiba, STMicro, and GlobalFoundries, said the alliance is developing several different transistors for the 14nm node. IBM will continue to develop an SOI technology with finFET transistors, adding its on-chip SOI-based embedded DRAM technology. Other members of the alliance need a bulk FinFET, and others, including STMicroelectronics, are pursuing a planar UTB-SOI approach (which IBM refers to as Extremely Thin (ET)-SOI) using back-gate biasing underneath the planar channel to boost performance or reduce power consumption.

“ET-SOI with a back-bias operation is pretty comparable with finFETs for certain applications. FinFETs are pretty complex, and ST Micro is pretty confident in ET-SOI,” Patton said during a brief interview at the Advanced Semiconductor Manufacturing Conference, held in Saratoga Springs, N.Y., this month. Patton said members of the Fishkill Alliance and IBM Albany will give three papers at the upcoming VLSI Symposium, planned for early June, on SOI finFETs, bulk finFETs and ET-SOI.

“FinFETs have some performance advantages, but Intel and others will have to show that they can control the tolerances, including at the source and drain regions. On the other hand, ET-SOI appears to have some resistance problems, so we’ll have to see how it plays out,” Patton said.

Freeman said the Fishkill Alliance has been a huge success, but warned that the shift to a tri-gate transistor “does give Intel a crack at the mobile device market, as the power consumption is very good.”

The Gartner analyst added, “What IBM needs to look out for is an Intel alliance forming. You already have Toshiba and Samsung working with Intel on some transistor technology, so there could be some cracks forming. There is the possibility of two camps, but Intel is so protective of its IP it will be interesting to see how this plays out.”

Chenming Hu, who led a UC Berkeley team that did much of the early work on both finFETs and UTB-SOI a dozen years ago, said he believes for finFETs and UTB-SOI technology will be deployed. Manufacturing finFETs, with the need for a very thin fin at close tolerances, is challenging for all but the largest companies such as Intel and TSMC.

“If the interface with the design team is close, and the resources are large enough, the lure of finFETs is that they can be scaled. But it does take investments. UTB-SOI does not take as much technology development investment,” Hu said.

UC Berkeley's Hu

“I remain steadfast in my belief that both FinFETs and UTB-SOI will be going to manufacturing,” Hu said. “I expect both to go into production. The very large companies, such as Intel and TSMC, will have the resources to go to FinFETs. Some other companies may go to UTB-SOI. ST Microelectronics is probably the closest to using UTB-SOI. FinFETs may be more versatile in performance and power. On the other hand, FinFETs take a lot more development resources, in terms of the manufacturing control, the layouts, and the libraries. In FinFETs, the gate widths are discrete, rather than continuous. And the thickness of the fin needs to be scaled, along with the gate length.”

Scott Thompson, a professor at the University of Florida, said the manufacturing challenges of finFETs may provide Intel with a five-year lead, or longer.

“Developing a complex technology like tri-gate requires significant investment in silicon resources and manpower—development teams of perhaps more than 1,000 people. The complexities for development mean that hundreds of thousands of wafers have to be run to solve the issues. The tri-gate development is at least an order of magnitude more complex than strained silicon at 90nm, or HKMG at 45nm. That is why it took Intel eight years to implement, and why I don’t think anyone else will have in market for more than five years,” said Thompson, who spent two decades in technology development at Intel’s technology and manufacturing group at Hillsboro, Ore.

Manufacturing perfect fins over billions or trillions transistors is quite a challenge, Thompson said, adding that “it can be done in a fab that runs a single process, with equipment and settings that are kept constant. The manufacturing flow has unique advantages for high-end processors but does have problems supporting several key features needed for SOCs: multiple threshold voltages, and thin and thick oxides in support of analog.”

By Pallab Chatterjee
Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics.

The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are still somewhat fuzzy.

In the area of uses, the discussion focused on three areas–memories, SoCs and computing systems (processor cores and memory). Memories have been using stacked die approaches for many years. These stacks use traditional wirebond technology, feature either standard or thinned die, and have a known cost model.

The advantage of memories is that there is common pin-out and stacked devices can utilize existing memory test methodologies by adjusting the address range for the design. The die in this application are stacked from the top of one die to the bottom of the next die. These products have shipped literally billions of parts in this technology at a very similar price point to standard wire bond. This methodology supports using known good die for the design, has compatibility with current design tools and has known thermal performance.

Computing systems have a different target for stacked die. These systems, however, require a different architecture. There is local 3D memory for each core that is connected, where the core is placed in the die by way of a vertical interconnect. These applications have very high I/O counts that cannot be run to peripheral I/O, so they cannot use memory-style connections. The die are stacked in a top-to-top format. These are the designs targeted for TSVs.

There are questions, however, about whether the TSVs should be part of the IP blocks and whether the models for the IP should include the timing for vertically stacked memory. The challenge with including them in the IP is related to the large variability in post-processing options for TSV creation by the fabs. The tools needed to model the TSVs and verify the IP is being used properly are still lacking, according to the panelists. Moreover, the thermal models, changes in strain after thinning, and multi-layer capacitive coupling for the die being stacked face-to-face are issues that need to be dealt with for generalized IP use.

These problems are not unsolvable. Xilinx has released products using multi-die technology, and for fixed topology applications there is an understanding of how to solve these problems. The generalized use of TSVs randomly distributed over a custom processor die leads to the creation of custom memory configurations and pin-outs, as well.

It is unlikely that a standards group will drive the memory compilers and designers to a standard pin-out for the blocks. Because the processor cores are soft IP and have different optimization tradeoffs, there is no standardized application target that would allow for the performance tradeoffs of the cores to hit a standard pin-out. In general. these will be custom designs and custom applications. The stacked die setup is targeted for very high volume or high ASP products that can justify the high cost of test.

With respect to SoCs, this platform will likely be one of the last to address TSVs because of the impact on the design and release cycle. Packaging, thermal, timing and power issues for multi-die SoCs is very complicated and is beyond the capacity of most EDA tools, especially in the context of billion-device ICs that already are pushing the limits of the tools. Advances are being made for this area, and tool vendors have discussed options for system verification that are being targeted at this use. These are still in development, and the current releases of the tools address some but not all of the use models for TSVs and stacked die, or silicon interposer and stacked die, but are not to the design tradeoff stage as yet.

In addition, this whole area is still bracketed by cost. Traditional system-in-package and wirebond-based stacked die are still the most cost-effective for consumer commodity chips. The key is to identify a device, market and performance metric that can justify the high production cost of this technology now.

By Ed Sperling
Just because a smart phone is sold by Verizon or AT&T mobile no longer means that it will be used primarily as a phone.

That distinction may sound trivial, but it has deep implications for the components that are used inside of these devices, how they’re used, and who wins the designs. Shifts such as this can also lead to broad changes in who buys the tools to develop the components, which tools they buy, and what sorts of flows they create with those tools.

There are several fundamental reasons why this shift is occurring, and all of them intersect and support the others.

Generation, geography and culture
First, there is a huge generational and geographical gap between what’s important in phones. For older users, voice conversations are the most important feature. For younger users, texting and games are key. And for business people on the go, the most useful features are a combination of voice and e-mail.

“This trend began in China, where a phone is not considered a voice device,” said Charlie Cheng, CEO of Kilopass. “It’s very textual and graphical. You use it for text, Facebook and browsing. Young people all use it that way, too. My kids think it’s a novelty when I call them on the phone.”

The tablet has blurred the lines even further. While most of the comparisons have been between tablets and personal computers, the real volume market overlap will be between smart phones and tablets. Both are capable of texting, videoconferencing and e-mail, and each can go places and do things that the other cannot. A tablet has huge possibilities in the business world and in places such as hospitals, where a touchscreen is preferable to a keyboard because it can be wiped clean. It’s also better for making presentations. But while it fits in a briefcase, it doesn’t fit in a pocket—something that may change as flexible screens begin production.

“A phone is no longer a phone,” said Vishal Kapoor, vice president of product management for SoC realization at Cadence. “The three most important issues are security, management of data—including how much of that is local information—and the video or graphics. Even bandwidth is no longer a problem technologically, although not all of the phones can take advantage of 4G yet.”

Power and performance
The second major change is in performance and power. While the two typically are tradeoffs on the same SoC, they’re not necessarily tradeoffs in the same package.

For the past couple of generations, smart phones have been able to hold their own as full-fledged number-crunching and computing devices. They can be used to surf the Web, do e-mail, download documents and photos, and even update those documents. While the form factor is limiting, the tradeoff in portability may suffice for executives or salespeople on the road.

But the real opportunity is less in conventional desktop or notebook computing than a raft of new applications. Apple reportedly is working with Visa, for example, on “swipe and go” technology, where a smart phone is used as a checkout device that can replace credit cards using near-field communication technology. Phones already are being used as boarding passes on many airlines, particularly in Europe.

These features are a sign of just how far performance has increased on these devices. Apple, MIPS, Freescale, ARM and Synopsys (through its ARC acquisition) all have developed very powerful multicore processors that draw very low power when used in conjunction with such approaches as power islands and power gating.

“What’s changing is that you’re starting to put a lot of personal information into these devices,” said Cheng. “There’s a lot of money involved in this and there’s a lot at stake.”

The Android effect
A third factor that is contributing to this shift is Android. The operating system developed by Google is spawning a revolution in how devices such as smart phones are used—and who wins the designs.

MIPS, which was one of the first adherents of the Android platform, is experiencing huge growth—much of it because of Android. The company’s revenues grew 44% in Q2 of 2010 vs.Q2 of 2009.

“The playing field is wide open,” said Art Swift, vice president of marketing and business development at MIPS. “What’s changed is those companies that were the leaders in the past in mobile will not necessarily be the leaders in the future. That’s especially true with tablets. Part of the market driver here was Android, and it’s wide open. There’s a whole cast of new players.”

Not all of it is happening in the usual places, either. John Koeter, vice president of marketing for IP and systems at Synopsys, says Android is opening up other markets that didn’t exist in the past.

“We’re not going to play in the shootout between MIPS and ARM,” said Koeter. “But we are seeing new markets for things like picture frames that can be interconnected and run applications. There are all sorts of new and interesting applications.”

Samsung's new Android-based Galaxy tablet.

Design challenges and opportunities
The challenge for chip companies working in these transitional technology markets is figuring out where the volume adoption will be, how to best utilize the technology to serve multiple markets, and how to add in enough flexibility so that certain features can be given priority where necessary.

In some cases this may utilize a system-in-package approach with an interposer technology or a network-on-chip architecture for improving signal traffic flow. In some cases it may be multiple cores within a complex SoC that serve the same purpose. And in the future, it will likely be multiple chips on a 3D stack, where different functions can be developed and then manufactured as needed for different markets.

What will have to change, however, will be the pace of tool adoption and development. One of the big complaints among system-level tools vendors is that not everything can be integrated into a flow because high-level tools don’t necessarily work perfectly with older tools that utilize lower levels of abstraction. That has stymied the growth of high-level synthesis and software prototyping, for example.

But these kind of changes may bring new players into the market, raising the competitive stakes to develop chips more quickly, more efficiently and with more flexibility. That means newer tools will be required, and it can quickly force a competitive upgrade among existing companies and spur growth in areas that have been slow to develop, particularly in the ESL space.

Conclusions
So what will be the most important features on a phone in the future? That will depend to a large extent on the applications and what’s important to users and companies that buy these devices. A phone will still have to be able to make phone calls, but that may be just a lesser feature on these increasingly complex devices.

“A phone will have to be reliable and clear,” said Koeter. “But once it meets that standard, then it’s all about a whole new experience.”