It was a big week for the Common Platform. Mentor Graphics completed a test chip using its netlist-to-GDSII flow for the Common Platform’s 32/28nm technology. And Synopsys introduced production ready Ly-nx for the Common Platform’s 28nm technology.

But the biggest news came from the Common Platform itself. At 20nm, the triumvirate of Common Platform members—Samsung, IBM and GlobalFoundries, will shift from “gate first” to “gate last” high-k metal gate technology. That’s the same approach used by TSMC. Common Platform companies say they’ve allowed customers to extend their technology one more node with minimal disruption. They may have a point.

Shanghai-based Spreadtrum Communications, which makes baseband and RF solutions for wireless communications, has standardized on Cadence’s design flow and taped out its first 40nm low-power chip using Cadence tools on its first pass.

Realtek Semi, meanwhile, licensed a bunch of processors from MIPS for everything from networking technology to digital home applications.

By Ed Sperling
Mentor’s Nazita Saye does what all good engineers do on vacation: They think about how to improve something. In this case, it’s the wireless access during a ski vacation in France. There may be a reason, of course. Just imagine what would happen if people were texting while skiing.

What would the holiday season be without great electronic toys? Or, to rephrase that, how did engineers ever pass the time before the mass adoption of electronic gismos? Synopsys’ Eric Huang looks at everything from USB drives to the Xbox Kinect.

ARM’s Cara Forsythe has her own list of things you can’t live without, including an ARM-based remote control helicopter. This invites all sorts of holiday innovation, like airlifting the cat.

Speaking of ARM, Cadence’s Richard Goering looks at why SoC designers should care about Linaro, the open-source initiative aimed at optimizing code for ARM cores. With chip developers now required to produce more of the software stack than ever before, this is an interesting twist.

Daniel Nenni views the Common Platform’s approach of a consistent process and the ability to add capacity as needed through GlobalFoundries, IBM and Samsung as a huge advantage. That’s the theory, at least.

Synopsys’ Karen Bartleson has begun looking for real world examples to illustrate the 10 Commandments for Effective Standards. Check out the Microsoft-Motorola lawsuit. There’s no place like court for instilling holiday cheer.

Deepchip’s John Cooley reviews Mentor’s Blue Book for C-to-RTL synthesis and gives it positive reviews. What’s particularly interesting is how much deep technical reading he gets done at fast-food restaurants.
Also in Deepchip, ST’s Ravin Sachdeva reviews Synopsys’ Synphony C compiler. The results are quite encouraging.  And in yet another blog, Cadence’s Akshat Shah responds to Jim Hogan’s evaluation of Cadence’s Analog Design Environment.

Mentor’s Harry Foster promotes up-front planning in verification. It’s a great idea, and there are lots of stats from a survey by the Verification Academy that should be required reading for all engineering managers.

Speaking of verification, Verilab’s Jonathan Bromley—writing in Synopsys’ VMM Central—digs into how to configure VMM testbenches. This is technical stuff, but it’s good advice from the experts.

Cadence’s Arthur Schaldenbrand digs deep into measuring f max in transistors. This is particularly noteworthy at advanced nodes, where proximity effects such as noise and distortion can kill a chip. It’s going to be required study for everyone in 3D stacking in a couple years, as well.

Mentor’s Colin Walls finds even more uses for memory management units, such as protecting memory buffers. Think about 3D stacking and you’ll find this one quite relevant.

Cadence’s Team Verify looks at assertion-based verification for complete blocks. For verification teams—software engineers, included—this is very good information.

Mentor’s Andras Poppe believes the Christmas lighting industry has reached a milestone: cool, LED lights. And to think that at one point people used to do this all with candles.

And finally, Cadence’s Jim Newton takes a deeper look into the SKILL language and how to translate code into English—and when not to.

By Ed Sperling
It was a good week for test, self-test and repair.

Synopsys rolled out its DesignWare self-test and repair error correcting codes compiler. This is a big deal in the IP world, and most of this comes from the Virage Logic side of Synopsys. Being able to self-correct memory can mean the difference between a wafer with good yield and one with poor yield. It’s also a way of building some margin into the design without eating up performance. And it helps prevent design problems deep in the embedded world where they’re hard to find and fix.

Mentor teamed up with ARM in a similar move, providing automated memory test and repair for ARM’s embedded memories and processor cores. Mentor is supporting ARM’s memory compilers.

Synopsys also plans to expand its RTL synthesis-based test technology over the next 12 months for better defect coverage of embedded memories.

Arteris scored a major deal with Samsung, which will use Arteris interconnect IP to link together multiple chips on its mobile platforms. Samsung plans to use it to connect its SoC and external modem chip. Considering Samsung’s prowess in this market, the volume should be huge.

By Ann Steffora Mutschler
With the typical cost of software accounting for 40% to 60% of an SoC, semiconductor OEMs are under more pressure than ever to meet margins. As a result, they are drawing on their ecosystem partners to provide a more complete foundation including hardware, software, FPGA prototypes, verification IP and virtual models, as well as an increasing demand for open source software support for their SoCs.

To be sure, software acquired through an open source model can allow faster time to market by leveraging publicly available technology. But the biggest limitation is lack of support, unless the software comes from a commercial provider.

How does this play outside in the hardware world? “Software is something you can change relatively easily, whereas hardware IP, once it’s in silicon you’re stuck with it,” said Simon Davidmann, president and CEO of Imperas and founding director of Open Virtual Platforms (OVP). “Another big difference between hardware and software is that there are very few people designing hardware compared to people writing software. If there are 100,000 apps for an iPhone then there must be 300,000 or 400,000 people trying to write them. In the hardware world, there are only about 100,000 hardware engineers globally, and yet there are many times that just developing software for the iPhone.”

Clearly, then, the software scale is completely different from the hardware scale, and this has an important effect on open-source ideas.

“With the GNU tools they can apply to tens of thousands of people easily, but in the EDA world that’s not really the case,” said Davidmann. “The closer you get to the hardware, the less appropriate an open source community is. Open source is good from a, ‘Let’s have a compiler that you can use for free,’ but no user fiddles with the open source bits of GCC (GNU Compiler Collection) or GDB (GNU Project Debugger) that doesn’t fiddle with Linux. It’s very useful for the hardware guy to make use of, but then they tend to have to pay people to do it.”

Where it works best
One of the biggest challenges companies face in implementing a design is in the verification phase, which is why it consumes the largest chunk of the non-recurring engineering expenses in any design. Prasad Subramaniam, vice president of eSilicon’s design technology, said this is exactly where open source can help.

First, open source software could be of help in the actual verification of the IP that is being stitched together as part of the SoC, especially for IP that is standards-based like a USB interface or a PCI Express interfac. “Because it is in the public domain, you can develop verification IP in an open source manner. That’s one of the advantages. People who do verification today license this kind of IP from various IP providers, and it will be significantly helpful for them if such verification IP is available in the open-source model as it will make it easier to access, allow them to do what-if analysis, experiments and so on before they go on and purchase something that is industrial class,” Subramaniam said.

Second, open source software support can be helpful in system-level verification. “Once you have designed your SoC, you want to try and run system-level testbenches, for example. If you build an ARM-based subsystem, you want to try and emulate it in an FPGA type of environment. You can get a board that contains an ARM chip with an FPGA and you can implement your logic, and this has an interface to your PC and you can control the software from your PC but the actual software will be running on the ARM test board and the FPGA,” Subramaniam said.

Similarly, John Koeter, vice president of marketing for Synopsys’ IP and Systems Division, said the use of virtual prototyping at the system level has allowed a fair share of the top 10 global semiconductor companies to pull the time to ramp into production by as much as six months earlier than with older approaches.

“Today many companies still use what I call a waterfall model where they develop the hardware, they get to the golden RTL or even the chip and then that’s when they’ll start developing the software on the physical prototype itself or maybe on an FPGA-based prototype of the chip,” he said. “That process is done in a serial or waterfall manner, and obviously that pushes out the entire development schedule significantly. We are really working with the semiconductor companies to pull in the start of the software design much earlier using virtual prototyping. In a fast moving market, ramping to silicon six months or even three months your competition easily yields 10% to 15% revenue through additional early wins.”

Models Are Key
The key to virtual prototyping involves the models, and while not disclosing any plans, Koeter noted that Synopsys intends to enable a significant effort within the open source community for creating models. He said plans are in development. Also, with its recent acquisition of Virage Logic, Synopsys gained the ARC cores, and is fully supporting the various software stacks that run on an ARC core, including variants of Linux, etc.

On the surface, it appears that Synopsys may be finding out what Imperas did, namely that people want control over the simulation models. They didn’t want to get into the insides of the simulator. But they do want a commercial company to professionally service and support the tools, and they want control over the IP and the models, Davidmann said. “The great thing about open source is that it allows you to see what’s going on, modify it and use it, and then that way it gives you freedom and can take things further.”

Imperas has a closed-source commercial simulator and open-source models (developed from published documentation and in such a way that the user can extend them). “This is very different from the SystemC approach of an open-source simulator—developed and funded by the big EDA companies, but which isn’t really open because you have to be part of their club and paying to be able to enhance it and redistribute it,” he said. “What this means is that it is about three or four years old. It’s a commercial ploy in that Cadence, Mentor, Synopsys have their own tools and simulators that use SystemC as proprietary professional solutions and the OSCI simulator is the poor cousin so it is several versions of a standard behind.”

Imperas also uses an Apache License, which Davidmann noted is good for commercial organizations and does not have the same requirements as the GNU license.

“For a silicon vendor that makes them very nervous. If [they] download a bit of IP and put it in [their] chip, the rules aren’t very clear yet because open source is all about software, it’s not really about hardware. Hardware tends to be covered by patents and software by copyright. In software if you use a GNU public license, if you link it to any other pieces of software, all of that software has to be covered by it so it really promotes the spirit of ‘free to use.’ You are allowed to access the source, and if you use it you’ve got to make your source available so it furthers the usage of it. Whereas in a commercial organization, there’s no way you would want to include a piece of hardware on your chip if you had to give away your hardware design. You want to protect that and hide it because it’s all your tricks and magic. In the hardware world people are much more nervous about the licensing of open source.” Davidmann said.

A new approach to open source for ARM-based SoCs
There is another approach that ARM, IBM, TI, Samsung, ST-Ericsson and Freescale have come together on to address OEMs that demand the best open source support. “They want the latest kernels, they want the latest tools, they’ve got to be stable. It’s more than just throwing them a BSP and hoping it is good enough. They want more than that, and that’s what Linaro was born to do,” to make it easier for ARM partners to deploy the latest, optimized technology into Linux based products, explained Rob Combs, head of global alliances at Linaro, a not-for-profit open-source software engineering company that launched in June.

Linaro stemmed from conversations with OEMs about the difficulties of developing open source—the need for great tools, the latest kernel, not having to rewrite BSPs from silicon partners, he said. “They want more of that support in the upstream trunk rather than less and they want more investment so we can fix any problems that crop up. That’s more than any one company can deliver individually. There needed to be a collaboration vehicle to deliver this for the ARM partnership. Linaro was born to make it easier and quicker to develop complex open source products based on these new whizzy SoCs that are coming out.”

Linaro does essential engineering relevant to multiple verticals markets and to multiple distributions. At the application framework level, the organization aims to helps distribution creators get a better base to start from, which is enabled on multiple ARM platforms for more commonality, and less fragmentation. In terms of development tools, Linaro believes it can provide better tools to build optimal software, which is are used at all levels of the OS, and which is crucial to achieving the best PPA. All of this is part of the move toward a common kernel and is enabled on multiple silicon platforms, Linaro said.

In the process of ramping from 20 to 80 engineers, the organization will deliver every six months a harvest of all of the latest, freshest code, Combs said. Linaro’s next step is to show proof points at upcoming Linux conferences.

By David Lammers
Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations.

“This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech. “Many companies are assessing the ETSOI path as a way to build on their history of planar devices. But other companies are considering non-planar devices, perhaps because they see a longer scaling path. The next year will be a period of intense evaluation and development.”

Thomas Hoffmann, the front end of the line program manager at Imec, said many of the fabless companies that belong to Imec’s Insite program—which allows the large fabless IC vendors to gain early understanding about technology trends—are now asking for information about finFETs. During the first year of the Insite program, the main topic of interest was high-k/metal gate technology.

“Today, there are a lot of questions about finFETs, and not so many about high-k, which they may have already tackled,” Hoffmann said. “Many of them expect one of the major foundries to adopt finFETs.”

At the Imec technology forum, TSMC senior vice president of technology S.Y. Chiang confirmed that finFETs were on the foundry’s roadmap. “We evaluated the device physics and decided that we cannot extend planar devices that far. So we will use finFETs at the 14nm node.”

Before then, Intel may lead the way into vertical transistors, using its tri-gate design as early as the 22nm node. With its history of pushing bulk silicon technology, Intel may adopt vertical devices on bulk silicon wafers rather than switching to the more-expensive SOI wafers. University of Florida Professor Scott Thompson, who earlier worked at Intel, is among those predicting an early switch by Intel to the vertical dimension at the 22 nm generation. Others believe Intel will figure out how to extend planar bulk technology at the 22nm node.

Though it is still evaluating finFETs, analysts including Gartner Inc.’s Dean Freeman expect the Fishkill Alliance to switch to ETSOI at the 22nm node, taking advantage of the ability to fully deplete carriers from the thin channel. IBM has worked closely with its primary SOI wafer supplier, Soitec (Bernin, France), to create a volume supply of extra-thin SOI wafers with a top silicon thickness of 12nm, plus or minus .5 nm. Maintaining uniformity of the top silicon layer is critical to controlling the threshold voltage in ETSOI technology.

Imec’s Hoffman said at the 22nm generation, about 75% of the process steps used to create planar transistors are also common to a finFET process flow. “When it comes down to the 22nm node, I wouldn’t be surprised if IBM goes to a fully depleted SOI technology. In the first order, companies have to figure out how to scale the gate length, but ultimately they will do it in order to scale the supply voltage.”

Yannick Le Tiec, a researcher at Leti (Grenoble, France) now working at the Fishkill Alliance, said the undoped channel in ETSOI technology removes the problem of dopants moving around during the high-temperature steps. Also, ETSOI improves control of the gate. “We can use the buried oxide layer of SOI and create a back bias at the ground plane. That is an option that bulk technologies don’t have,” Le Tiec said.

Fig. 1:Fully depleted SOI devices with a gate length of 40 nm and a thin (10 nm) buried oxide. (Source: STMicroelectronics, Leti, and Soitec presentation at 2010 Symposium on VLSI Technology)

With strain techniques and high-k/metal gates pushed close to their limits, leading-edge IC vendors have to do something new to keep power consumption under control, said Jan Rabaey, head of the Gigascale Systems Research Center at the University of California at Berkeley. The undoped channel in ETSOI “gets around the key problem for leading-edge devices, which is the random variability of the dopants.” Also, by putting a fourth terminal beneath the oxide, Rabaey said ETSOI transistors can improve the ability to fully turn off the transistors.

“Intel is very committed to finFETs, and TSMC also is talking about finFETs at the 15nm node. But ETSOI is a technology that may be more amenable to rapid deployment,” Rabaey said. FinFETs would require a “total redesign of any company’s hard IP,” he said. With vertical transistors, the design rules governing spacing, proximity, and density all will change. And vertical transistors require innovations in manufacturing as well, including lithography and CMP.

Fig. 2: At the 2010 Symposium on VLSI Technology, IBM Research and other members of the Fishkill Alliance presented a finFET SRAM cell measuring 0.094 μm2

At 22nm and beyond, the design community is likely to see the major foundries go in different directions. TSMC may support a bulk 22nm flow, while GlobalFoundries, Samsung, IBM, and other members of the Fishkill Alliance may commit to a planar ETSOI process. If TSMC follows through on its commitment to finFETs at the 15nm generation, the EDA, IP, and fabless semiconductor companies may confront another divide, with TSMC adopting vertical transistors while GlobalFoundries and others remain planar. At that point, Rabaey said foundries will need to get much more involved with design, and fabless companies will “have to know a lot more about the process.”

Gap-fill challenges
The shift to vertical transistors will require new manufacturing techniques, said Randhir Thakur, general manager of the Silicon Systems Group at Applied Materials. Applied unveiled a flowable CVD (FCVD) tool on Aug. 24 that is aimed at finFETs and vertical memory devices where conventional CVD dielectrics and spin-on dielectrics (SOD) both run out of gas. Electrical isolation of the vertical transistors requires filling the isolation trenches with dielectrics from the bottom up, rather than from the sides.

“FinFETs raise the complexity beyond what spin-on dielectrics can handle. Those chemistries also have a lot of carbon, which creates fixed charges,” Thakur said in announcing Applied’s “Producer Eterna” flowable CVD tool.

The Eterna system includes a proprietary precursor, a carbon-free chemistry that can fill 10nm openings with very high (30:1) aspect ratios. “If carbon is introduced, that causes the threshold voltage to shift and creates leakage,” said Bill McClintock, general manager of Applied’s dielectric systems and chemical mechanical planarization products. Also, finFET manufacturing requires relatively low processing temperatures. “Going forward, these new device architectures involve filling gaps which are not doable with the current systems on the market,” he said.

By David Lammers
Through-silicon vias (TSVs) are in various stages of late development, but design and manufacturing challenges remain before companies can gain the full benefits of the third dimension.

Two camps are pushing hard to introduce TSVs—the design community and the manufacturing equipment companies. The initial goal is to connect graphics memories to graphics processors in mobile systems. Integrated device manufacturers (IDMs) such as Samsung Electronics are racing to use TSVs to couple high-bandwidth DRAMs with processors. Samsung counts Apple as a major customer. Qualcomm and foundry partner TSMC are creating their own design and manufacturing ecosystem for TSV-enhanced mobile IC solutions.

Sesh Ramaswami, senior director of strategy for the TSV program at Applied Materials said Applied has had about 50 people working on TSV-related technologies since 2008, and now has a complete toolset ready. “We are extending all of the knowledge gained from Damascene processing (for copper chip interconnects) to TSVs,” he said.

The equipment and materials companies have gained valuable learning from the early adoption of TSVs in CMOS image sensors, said Didier Louis, a project leader at the Leti R&D consortium in Grenoble, France. Leti worked closely with STMicroelectronics and Nokia to develop a TSV process flow, used to create image sensors in which the TSVs connect the CMOS image sensor and memory. Leti is not yet working on a logic-to-memory TSV solution, but Louis said, “We have in our toolbox all the knowledge. To manage a logic-memory TSV integration it helps if the dice are the same size, and if the manufacturer knows where to drill the vias.”

Fig. 1: Signal and ground TSV architectures may be needed for video applications. (Source: Robert Geer, CSNSE)

Getting the bandwidth increases promised by TSVs will require careful interconnect design optimization, said Robert Geer, a professor at the College of Nanoscale Science and Engineering in Albany, N.Y.. “Every time a designer uses a TSV, you are losing device area,” Geer said, noting that about 10% of the typical die area is consumed by the vertical interconnects. While performance gains are there to be had, Geer reminded an audience at Semicon West that “as nice as TSVs are, they are still copper, which has a frequency limit of about 1GHz” for a 5µm-diameter TSV. For memory access, bandwidth of 2 terabits per second (Tb/s) is sufficient, but logic-to-logic computation requires 5 to 6 Tb/s, and RF signals need much more bandwidth, 50 to 100 Tb/s.

Fig. 2: Video and RF will require up to 100 Tb/s of bandwidth. (Source: Robert Geer, CNSE)

Power is a critical issue. “You want the signals to go through (from logic to memory) at a femtoJoule rate,” Geer said.

For power-conscious mobile systems, TSVs are the only realistic way to connect a graphics/video processor to several layers of graphics memory, where 12.8 GB/s of bandwidth is needed between the processor and DRAM memory for high-definition video. A conventional (non-TSV) HD video solution would require high-frequency operation over 2,000 I/O pins, a non-starter for any battery-operated system, said Pol Marchal, director of IMEC’s TSV development effort.

Geer and CNSE colleague Wei Wang have studied the interconnect architectures needed for “many-core” SoCs with the processor blocks running at relatively low frequencies. Network-on-chip (NoC) architectures for these TSV-enhanced many-core solutions will be required. For video processing and other high-bandwidth requirements, Geer said a coaxial interconnect design, with each signal TSV surrounded by four ground/buffer TSVs, may be required.

While the design community develops the expertise and EDA tools required for TSV-enhanced interconnect architectures, the equipment and materials vendors are ironing out their own challenges. Fusen Chen, executive vice president at Novellus Systems, said TSVs of 5 to 6µm are difficult to fill without voids. Because of the CTE mismatch between copper and silicon, “the copper wants to pump out” from the via, Chen said, adding that for Novellus “the key is our ability to pre-wet in a unique way.”

Keeping the cost of electroplating down, particularly for high-aspect ratio (20:1) vias, is another challenge, Chen said. Novellus introduced its Sabre 3D electroplating system, optimized for TSVs, redistribution layers (RDLs), and other wafer-level packaging applications at Semicon West this month. That sets the stage for an intense electroplating competition between Novellus and Applied Materials, which last year bought electoplating vendor Semitool Inc. (Kalispell, Mont.).

Also at Semicon West, Applied introduced the Avila CVD system for the vias-last TSV process flow, where temperature control is critical. In the vias-last flow, TSVs are formed from the backside after the wafer is thinned. In the vias-middle approach, the TSVs are created in the wafer fab after formation of the contacts.

By David Lammers
Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanical stress had relaxed over time and the top die had delaminated.

3D researchers around the world are paying much closer attention to thermal and mechanical stress, particularly as ever-thinner die are stacked and connected. At last week’s 2010 Symposium on VLSI Technology in Honolulu, IMEC researchers described the mismatch in the coefficient of thermal expansion between copper through-silicon vias (TSVs) and the surrounding silicon. Using a 45nm digital analog converter test chip, the IMEC team measured transistor drive currents with TSVs located at various distances from the active circuits. Tensile stress near the TSVs was in the range of mega Pascals (MPa), declining to zero stress at a distance of about 10 microns from the TSV edge – a distressingly long distance for today’s leading-edge devices.

That kind of fundamental information (IMEC will deliver a more-complete paper at IEDM in December), Marchal said, is allowing EDA vendors and chip manufacturers to begin creating stress models. “Thermal and mechanical stresses induced by TSVs is a big worry for the community, but I believe there are different ways to mitigate them. A lot depends on what type of devices you use. Stress is not uniform for different types of devices; for example, long channel devices see more impact.”

At its Leuven facility, IMEC is fabricating a series of test chips, named after volcanos, which have sensors positioned at various places on the die to measure thermo-mechanical stress. “We position the smart sensors at the most critical places inside the stack, with the DRAM on top, to study the thermal and mechanical impacts. Then we provide the information to our supply chain partners, including the DRAM makers and packaging houses. Our partners, such as Qualcomm and STMicro, want to gain a head start. When they start RTL-level design they want to know what is feasible and what is not.”

Fig. 1: IMEC is working with several EDA partners to create a pathfinding flow for 3D prototype creation. (Source: IMEC)

While the EDA community is making progress, Marchal worries about is the relative absence of the packaging design community. Co-design of the die and package is particularly important as top die are thinned to 50 microns or less, positioned on top of a much thicker die.

“The die are becoming as thin as aluminum foil, and if you have the wrong glue, or different heat cycles, the die do not remain flat. That builds up stress across the die. The EDA and packaging communities need to be more active in how to analyze this,” Marchal said.

These challenges will be solved, particularly as increasingly large investments are being made in 3D TSV technology. At the DAC conference last week, Myung-Soo Jang, a design infrastructure manager at Samsung Electronics, described Samsung’s plan to use TSVs to link a mobile logic device with a 400 MHz DDR3 memory. “Because we are the world’s largest memory maker, which also has systems expertise from our cell phone business, we believe we have an advantage in this area,” Jang said.

Memory manufacturers such as Samsung and Toshiba, bring certain advantages, but fabless and foundry vendors are forming their own alliances, including EDA vendors and packaging houses. At DAC, L.C. Lu, director of the design methodology division at TSMC, called 3D TSV “the next killer application” and outlined a 3D design flow that TSMC is developing.

The mobile systems vendors need TSV interconnects to support the bandwidth needed for new data services, which include point-to-point video, a market set to accelerate over the next five years. High-definition video encoding requires about 12.8 GB/s of bandwidth between the processor and DRAM memory. The only way to do that in a mobile system is with TSV-connected logic-memory solution, using three or four tiers of die thinned to 30 to 40 microns. To achieve the same bandwidth, conventional DRAMs would require the power-hungry GDR5 DRAM standard, some 2,000 I/O pins, and a frequency that would kill any cell phone battery quickly.

Sitaram Arkalgud, director of Sematech’s 3D interconnect initiative in Albany, N.Y., said Sematech is focused now on a copper-copper bonding, vias-middle manufacturing flow that will come into use in several years. To tackle the stress challenge better standards are needed for how to measure and report thermal and mechanical stress levels. At next month’s Semicon West in San Francisco, Sematech and Germany’s Fraunhofer IZFP research center will hold a workshop on 3D stress management, including DFM-like approaches for managing stress, material properties, and measurement techniques.

Arkalgud said Sematech and SEMI are working on a data exchange format for TSV applications, and will hold a meeting on the subject at Semicon West and again at Semicon Europa in the fall.
“Especially as we go to thinner die the TCE and stress issues will be something we need to watch. To do that, we have to agree on how to measure it, so a data exchange specification needs to be there,” Arkalgud said.

By David Lammers
GlobalFoundries and TSMC had major presences at last week’s Design Automation Conference, with TSMC announcing support for system-level design techniques and GlobalFoundries explaining its reference design platform. Samsung Electronics also generated a fair amount of foundry buzz at the 2010 DAC in Anaheim, detailing its 32nm high-k/metal gate process and the planned $3.6 billion investment in a logic fab in Austin, Texas.

Both TSMC and GlobalFoundries are emphasizing 28nm design rules for their low-power customers, with 28nm low-power (28 LP) manufacturing beginning later this year. GlobalFoundries is busy in Dresden, Germany, ramping up its 32nm high-performance high-k/metal gate (HKMG) SoI process for Advanced Micro Devices. AMD’s Llano processor will provide GlobalFoundries with a valuable learning curve for its 28nm LP process with HKMG technology. While TSMC will offer an oxynitride (SiON) 28nm LP process first for low-cost applications, the HKMG process will serve much of the mobile space.

TSMC has dominated leading-edge foundry manufacturing for so long that its customers have built up a rich library of intellectual property tuned to the TSMC processes. Playing catch-up in the IP space, GlobalFoundries, IBM, and Samsung—the trio of companies in the Common Platform—share a common process as well as shared EDA and IP partners.

The Common Platform’s biggest edge is that at the 32/28nm generation, Samsung and Global Foundries will provide customers with second-source capabilities. A Freescale Semiconductor manager said that because TSMC and the Common Platform partners have implemented different approaches to HKMG deposition, fabbing designs at both TSMC and GlobalFoundries will require “a totally different set of libraries and IP.”

The incompatible IP stems in part from the different approach to high k, he said. “TSMC will tell you that their gate-last approach has performance advantages, and GlobalFoundries says their gate-first approach has die-size and design-migration advantages,” the Freescale manager said. “But with Samsung in there, it allows us to move a design to both GlobalFoundries and Samsung with the same GDS II tape.”

The Common Platform process features process “knobs,” including implant steps and others, which can be used to tune the threshold voltage (Vt ) to meet product requirements. The Freescale manufacturing manager said the Common Platform process involves five additional implant masks, compared with the TSMC 28nm flow, adding that the implant masks are “pretty cheap masks.”

Ana Hunter, Samsung’s vice president of foundry operations, said that Samsung created a test SoC with an ARM 11 core and other IP. A direct comparison of the Samsung 32nm HKMG test chip with the 45nm SiON version at the same frequency showed a 33% improvement in dynamic power and a 55% reduction in leakage power. Some customers might prefer to emphasize performance, Hunter said, taking a 26% increase in speed while keeping power consumption relatively stable.

Hunter said despite published doubts about the threshold voltage stability of the gate-first HKMG flow, Samsung’s qualification process has shown the gate-first flow to be stable. “There is a lot of FUD (fear, uncertainty, and doubt) out there,” Hunter said, “but we have fully qualified this 32nm process and it is stable, with intrinsic reliability. The Vmin is very stable and robust.”

Suresh Venkatesan, vice president of alliance technology at GlobalFoundries, said the gate-first HKMG process supports an overdrive capability that proves the robustness of the gate-first approach. “The first AMD Fusion product is a quad-core-plus-graphics-processing design that runs at operating voltages ranging from 0.8V to 1.3V. That shows that our high-k metal gate process supports an overdrive capability that could only happen if the process has a high degree of reliability.”

Another point of debate between TSMC and the Common Platform partners revolves around die size. TSMC insists that the gate-last approach does not result in a die size penalty, as long as the design teams follow a TSMC-approved place and route style tuned to the gate-last HKMG flow. GlobalFoundries “provides a 10-20% advantage in die size, versus the extensive restrictive design rules” required by the other leading foundry,” Venkatesan said.

The two camps are engaged in a marketing war over whether the gate-last approach restricts the use of a local interconnect layer or not, and the possible impact of that on the portability of the designs from 40nm to 28nm HKMG. “If you just look at the ground rules, there is no getting around a die size difference,” said Gary Patton, vice president at IBM’s Semiconductor Research and Development Center in Fishkill, N.Y.

At DAC, Samsung representatives said the $3.6 billion expansion of the Samsung Austin fab is aimed at logic. “Samsung has identified foundry as the next big opportunity going forward. The Austin expansion shows Samsung’s commitment to the foundry business,” said William Chang.

While GlobalFoundries is expanding in Dresden, Singapore, and Malta, N.Y., and Samsung is building up logic and foundry wafer starts in Giheung, Korea and Austin, foundry leader TSMC continues to concentrate its massive expansion at its home base of Taiwan. TSMC senior vice president S. Y. Chiang said construction is underway on two 300mm gigafabs in Hsinchu and Tainan. What is less well known is that TSMC has broken ground on a third site in Taichung, in central Taiwan. Plans call to construct the shell in Taichung over the next year and then quickly equip the fab when foundry market demand requires it.

By Ed Sperling
Cadence completed its acquisition of Denali, moving the company squarely into the IP business for what amounts to an all-out IP arms race. Several sources have confirmed Cadence bid for Virage Logic first, but was outbid by Synopsys. Cadence subsequently made the $315 million offer for Denali. The selling price has lots of companies hanging out a “for sale” sign. The big question is who’s next?

ARM, the Common Platform companies (IBM, Samsung and GlobalFoundries) and Synopsys introduced a 32/28nm high k/metal gate that is “vertically optimized.” Exactly what “vertically optimized” means is something of a mystery, however. You won’t find any additional information about this in the release or in any of the links.

Mentor Graphics and Synopsys both updated some of their top tool suites at DAC, not to mention their relationships with foundries. Mentor is collaborating with GlobalFoundries on an advanced design and manufacturing flow using Calibre.  It also added verification, extraction and DFM support for TSMC’s AMS 1.0 flow, as well as ESL, integrated design, and manufacturing closure for TSMC’s Reference Flow 11.  In addition, Mentor’s Olympus SoC place and route is now supported by X-FAB.

Synopsys improved its PrimeTime performance for static timing analysis, migrated its Ly-nx pre-validated design environment for the Common Platform’s 32/28nm nodes. It also introduced a Galaxy characterization solution for standard cells, complex macros and memories, and it added StarRC custom 3D extraction for sub-45nm designs.

Cadence also provided its contribution to the Universal Verification Methodology, aka UVM—an open-source reference flow for SoC verification.

Atrenta introduced SpyGlass-Physical for physical implementation modeling. There was a lot of talk about tradeoff analysis and what-if approaches at DAC this year.

http://www.atrenta.com/atrenta-news/96.news

AMD inked a deal for Apache Design Systems’ power supply noise and reliability sign-off tools. Considering the close relationship between AMD and GlobalFoundries, this becomes particularly interesting.

By Ed Sperling

Actel’s ProASIC FPGAs are all over the new Boeing 787, which is supposed to be significantly more fuel-efficient than previous Boeing jets. Actel has been developing chips that use flash instead of SRAM to make them more resistant to single-event upsets caused by stray neutrons, which are about 150 times more prevalent at 35,000 feet than at sea level.

Synopsys began laying the groundwork for the next big market, namely India. The company’s VLSI design curriculum was adopted by five regional centers of excellence. This is similar to what many of the EDA players did in China at the beginning of the last decade.

AMD raked in $1.65 billion in sales in Q4, up 18% from the previous quarter and up 42% from the same period in 2008. The company also reported a profit of $1.18 billion. But dig a little further into the numbers and you find that Intel paid AMD $1.25 billion to settle its longstanding dispute. How long can AMD live on the Intel settlement and can it reach profitability on its own before the money runs out?

Rambus settled its longstanding patent infringement case against Samsung, taking home $900 million. But the bigger win may be a joint development deal between the companies to work together on a variety of new memory technologies.