By Pallab Chatterjee
Stacking die has progressed from what is technologically possible to what will be realistically feasible in a fabless or fab-lite world. The big challenges may be less about how to deal with stress caused by a TSV or thermal density and more about companies working together in a disaggregated supply chain.

This was quite evident at a recent DesignCon panel dicussion on 3D die and assembly standards. The panelists—Riko Radojcic of Qualcomm, Sumit DasGupta of Si2, Liam Madden of Xilinx, Raj Jammy of SEMATECH and Jim Hogan of Vista Ventures—had widely different views about what needs to be done.

Both Qualcomm and Xilinx are in production with products that use TSVs and other stacked die technologies. Sematech and Si2 are focused on future directions for being able to implement what these companies have accomplished, seeking commonality in process and design across dissimilar businesses and markets.

Hogan zeroed in on the realities of production and getting parts into the marketplace, downplaying standards that result in everyone working together happily. The challenge, he said, is the rules for these stacked die are based on what you do with them.

The Xilinx product has a fixed pattern logic array (FPGA core) and fixed memory blocks connected together in a pattern that conforms to both its design architecture as well as its design software base. These pin placements, pad locations on the die, and stacking methodology are not necessarily applicable to other vendors or custom designers that could benefit from standardization of Xilinx’s tooling. As a result, moving forward without a standard is not a big deal for this application.

Qualcomm has a similar situation for its stacked die, which is targeted at cell phones. The company’s RF and logic cores and second chip memories, which are driving the use of stacked die, have different I/O issues. Compared with Xilinx’s application, Qualcomm’s has different pin counts, different performance for these connections and a much different reach. This is a custom processor that can be laid out over the local RAM, creating a clock-optimized design that minimizes the delay path for the system design.

Based on the unit being created—whether it’s a smart phone, feature phone, tablet, TV or set-top box—there are different assembly guidelines and goals for the 3D stacking. These designs heavily utilize traditional edge-based pin connections. Qualcomm already has a history of stacked die production. It has used this knowledge base to make more aggressive chipsets and product solutions, so at this time sharing that marketplace information has a limited value.

Hogan noted there is a need for commonality in processes, so every like microprocessor can contact a standard product memory, but custom processors and custom memories need not conform. It’s the same with standard logic functions being available as both MPW samples and DFW that are implemented as a high-level standard function IP. The challenge becomes when is it IP and when is it package assembly? While the technical model may want to have standards in the loop to address a TTM reduction, the business model for incorporating those standards is behind the pace of implementation that is dictated by the product rollout schedules. The market cannot wait, and products have to be shipped.

Hogan also brought up the concept of IP for the 3D interconnect and its encompassing system. If there are standard locations (similar to the JEDEC ones that are already in progress), will these include electrical specs, thermal and materials models, abstracted simulation models, reliability information, and test for both sides of the interconnect point as well as the interconnect point itself? Creating a specification of location and order without these aspects does not help the time-to-market challenge facing the semiconductor industry.

Unlike the power supply debates, which were fostered as two standards from competing EDA companies with differing politics of design—the 3D market is not a single problem with different approaches. It includes different design applications in different manufacturing chains that require some pin commonality.

By Ed Sperling
System-Level Design sat down to discuss the future of stacked die with Riko Radojcic, director of engineering at Qualcomm; Prasad Subramaniam, vice president of design technology at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that conversation.

SLD: Where are we with 2.5D and 3D?
Radojcic: I think 2.5D was a misnomer, because that implies they are sequential. It’s clear that what we call 2.5D and 3D are going to co-exist for a long time. Some things make sense with an interposer and some make sense to be 3D.
Reiter: I agree—2.5D is a parallel effort to 3D. Lots of things will not use 3D because it’s too expensive. In 2.5D we will see production this year. With 3D it will take until next year for the first ones. I would guess computing or networking would be the first.
Radojcic: I would think those guys will pursue 2.5D.
Subramaniam: Memory makers are already offering 3D solutions today. If you look at just the memory chip, to increase the size of the memory rather than the die they’re stacking it vertically. That kind of 3D is already in production. It’s the question of co-mingling logic and memory that will take time. The advantage of 2.5D is that it allows afterthought. It allows you to take an existing design and to create a new set of I/Os and put in a 3D type of application.
Radojcic: I see no value in doing that. You’re creating an expensive solution to something you can do more cheaply. If you add the 3D interposer you’re adding another wafer. That’s cost. We can solve that problem with a flip chip. It’s cheaper.
Subramaniam: I disagree. We’ve done the analysis. It allows us to take an existing design, like an ARM subsystem in 28nm, even though surrounding logic doesn’t have to be at that 28nm process node. It can be 40nm or 65nm. Rather than building a new chip at 28nm, I can take my existing design, use it as one component of my 3D IC, and build a second chip in a cheaper, older technology.
Radojcic: Yes, as long as you’ve architected your chip like that, such that you can partition it.
Subramaniam: You can’t take any design, no. There has to be some partitioning in the architecture and some forethought. It’s not 100% an afterthought, but there is still some afterthought there.
Radojcic: You have to architect for it. If you haven’t done that, taking an existing chip will just cost you more. If you have done that, of course there is an avenue to doing things better and more flexibly.
Subramaniam: There is enough flexibility in designs that allow you to partition it in some manner.
Radojcic: True, but before 3D came along most of us wouldn’t have partitioned. We wouldn’t have architected it that way. To be able to leverage that value proposition, you must have 3D in mind.
Gianfagna: That’s true. It’s a premeditated act. If you don’t think it through way up front it doesn’t work.
Subramaniam: Because the SoC has a well-defined architecture, it lends itself to this type of application.
Radojcic: But only if you plan for it ahead of time.

SLD: Is this true in all cases?
Reiter: That’s the view of a high-volume supplier. I see low-volume solutions where they use an existing die, put it face down on an interposer, and connect memory to it. So for low to medium volume, 2.5D works. You call it an afterthought. I call it a customized solution.
Radojcic: Why wouldn’t you do that in a traditional multichip package?
Subramaniam: Because you don’t get the interconnectivity. The advantage of a silicon interposer is that you get thousands of interconnects.
Radojcic: But you have to design it sufficiently so you can leverage the interconnects from die to die. If you had designed for a traditional design, though, you would say, ‘I can’t have thousands of interconnects so I’m going to make a serial interface with 100 pins.’ If you take that design for a 100-pin interconnect and stick in an interposer it’s an expensive way of doing things.
Subramaniam: You may be able to take some internal signals out, which you are not able to do with a traditional MCM (multi-chip module) approach.

SLD: Let’s do a reality check. How far along are we toward stacking?
Gianfagna: Last year we had a hot-wired 3D system that was 2D with a bunch of scripts and manual effort. The customer base had strange, contrived designs and they were trying to see what they could and couldn’t do, and the foundries didn’t know what they wanted to do. A year later we have native 3D planning capability, the customer base has specific designs for implementation this year and next, and the foundries have a laser-sharp focus on process learning, mostly around 2.5D initially. If that’s a metric, things are clearer this year than last year. From an EDA perspective, I still think the market is two years away. But we still think this is big.
Reiter: If you look at the Atom chip with the FPGA from Altera, that’s basically a 2.5D solution. The FPGA is for customizing things. The Atom chip was not designed for this application.
Radojcic: But why use an interposer? Why not use a substrate and a multichip package?
Reiter: You could do that.

SLD: What’s missing from the tools side to make all this work?
Reiter: The ability to demonstrate what this technology can do is the most important capability. If you look at big corporations, top management is still hesitant to invest in this technology. If we could demonstrate in a credible way what it can do, people will be more successful in getting money to start programs using this technology.
Gianfagna: The way that happens is the early adopters blaze the trail, everyone tries to follow and the market heats up. What’s needed are commercial drivers. The tools aren’t there, but they’re close enough.
Subramaniam: The tools are not the issue. The development needed to support 3D is incremental. It can be done with the existing infrastructure. It’s really the end application.
Radojcic: Other than path-finding, which is hard to do with traditional tools. And the analysis.
Gianfagna: The complexity is higher. We’ve discovered that, too. RTL prototyping for a single chip has a certain set of challenges. When you go to 3D the modeling requirements are much greater, the constraint generation is more complicated. And we need standards. We can generate all the constraints, but we don’t know where to put them and how to express them because there is no agreed upon way to do that.

SLD: Do the standards organizations know where to start with all of this?
Radojcic: Standards are on a good track. We’ve worked with Si2 and Sematech to propose initials blasts for standards so we can feed them into Si2 and the EDA community and accelerate the process. The bits and pieces are moving, and we are on track to have a set of design exchange format standards by early next year.
Reiter: And Wide I/O.
Radojcic: Yes. The standards are channeled and the engine is revving.
Reiter: We have a bunch of players in a 3D enablement center participating. There are 15 companies listed, including Intel, IBM, TSMC, GlobalFoundries, and so on.
Radojcic: The way this was set up was Sematech said we are going to start a 3D enablement center initiative driven by the SIA. All the members of Sematech were mapped into this. Then a number of companies like Qualcomm, LSI and ASE joined.

By David Lammers
Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations.

“This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech. “Many companies are assessing the ETSOI path as a way to build on their history of planar devices. But other companies are considering non-planar devices, perhaps because they see a longer scaling path. The next year will be a period of intense evaluation and development.”

Thomas Hoffmann, the front end of the line program manager at Imec, said many of the fabless companies that belong to Imec’s Insite program—which allows the large fabless IC vendors to gain early understanding about technology trends—are now asking for information about finFETs. During the first year of the Insite program, the main topic of interest was high-k/metal gate technology.

“Today, there are a lot of questions about finFETs, and not so many about high-k, which they may have already tackled,” Hoffmann said. “Many of them expect one of the major foundries to adopt finFETs.”

At the Imec technology forum, TSMC senior vice president of technology S.Y. Chiang confirmed that finFETs were on the foundry’s roadmap. “We evaluated the device physics and decided that we cannot extend planar devices that far. So we will use finFETs at the 14nm node.”

Before then, Intel may lead the way into vertical transistors, using its tri-gate design as early as the 22nm node. With its history of pushing bulk silicon technology, Intel may adopt vertical devices on bulk silicon wafers rather than switching to the more-expensive SOI wafers. University of Florida Professor Scott Thompson, who earlier worked at Intel, is among those predicting an early switch by Intel to the vertical dimension at the 22 nm generation. Others believe Intel will figure out how to extend planar bulk technology at the 22nm node.

Though it is still evaluating finFETs, analysts including Gartner Inc.’s Dean Freeman expect the Fishkill Alliance to switch to ETSOI at the 22nm node, taking advantage of the ability to fully deplete carriers from the thin channel. IBM has worked closely with its primary SOI wafer supplier, Soitec (Bernin, France), to create a volume supply of extra-thin SOI wafers with a top silicon thickness of 12nm, plus or minus .5 nm. Maintaining uniformity of the top silicon layer is critical to controlling the threshold voltage in ETSOI technology.

Imec’s Hoffman said at the 22nm generation, about 75% of the process steps used to create planar transistors are also common to a finFET process flow. “When it comes down to the 22nm node, I wouldn’t be surprised if IBM goes to a fully depleted SOI technology. In the first order, companies have to figure out how to scale the gate length, but ultimately they will do it in order to scale the supply voltage.”

Yannick Le Tiec, a researcher at Leti (Grenoble, France) now working at the Fishkill Alliance, said the undoped channel in ETSOI technology removes the problem of dopants moving around during the high-temperature steps. Also, ETSOI improves control of the gate. “We can use the buried oxide layer of SOI and create a back bias at the ground plane. That is an option that bulk technologies don’t have,” Le Tiec said.

Fig. 1:Fully depleted SOI devices with a gate length of 40 nm and a thin (10 nm) buried oxide. (Source: STMicroelectronics, Leti, and Soitec presentation at 2010 Symposium on VLSI Technology)

With strain techniques and high-k/metal gates pushed close to their limits, leading-edge IC vendors have to do something new to keep power consumption under control, said Jan Rabaey, head of the Gigascale Systems Research Center at the University of California at Berkeley. The undoped channel in ETSOI “gets around the key problem for leading-edge devices, which is the random variability of the dopants.” Also, by putting a fourth terminal beneath the oxide, Rabaey said ETSOI transistors can improve the ability to fully turn off the transistors.

“Intel is very committed to finFETs, and TSMC also is talking about finFETs at the 15nm node. But ETSOI is a technology that may be more amenable to rapid deployment,” Rabaey said. FinFETs would require a “total redesign of any company’s hard IP,” he said. With vertical transistors, the design rules governing spacing, proximity, and density all will change. And vertical transistors require innovations in manufacturing as well, including lithography and CMP.

Fig. 2: At the 2010 Symposium on VLSI Technology, IBM Research and other members of the Fishkill Alliance presented a finFET SRAM cell measuring 0.094 μm2

At 22nm and beyond, the design community is likely to see the major foundries go in different directions. TSMC may support a bulk 22nm flow, while GlobalFoundries, Samsung, IBM, and other members of the Fishkill Alliance may commit to a planar ETSOI process. If TSMC follows through on its commitment to finFETs at the 15nm generation, the EDA, IP, and fabless semiconductor companies may confront another divide, with TSMC adopting vertical transistors while GlobalFoundries and others remain planar. At that point, Rabaey said foundries will need to get much more involved with design, and fabless companies will “have to know a lot more about the process.”

Gap-fill challenges
The shift to vertical transistors will require new manufacturing techniques, said Randhir Thakur, general manager of the Silicon Systems Group at Applied Materials. Applied unveiled a flowable CVD (FCVD) tool on Aug. 24 that is aimed at finFETs and vertical memory devices where conventional CVD dielectrics and spin-on dielectrics (SOD) both run out of gas. Electrical isolation of the vertical transistors requires filling the isolation trenches with dielectrics from the bottom up, rather than from the sides.

“FinFETs raise the complexity beyond what spin-on dielectrics can handle. Those chemistries also have a lot of carbon, which creates fixed charges,” Thakur said in announcing Applied’s “Producer Eterna” flowable CVD tool.

The Eterna system includes a proprietary precursor, a carbon-free chemistry that can fill 10nm openings with very high (30:1) aspect ratios. “If carbon is introduced, that causes the threshold voltage to shift and creates leakage,” said Bill McClintock, general manager of Applied’s dielectric systems and chemical mechanical planarization products. Also, finFET manufacturing requires relatively low processing temperatures. “Going forward, these new device architectures involve filling gaps which are not doable with the current systems on the market,” he said.

By David Lammers
Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanical stress had relaxed over time and the top die had delaminated.

3D researchers around the world are paying much closer attention to thermal and mechanical stress, particularly as ever-thinner die are stacked and connected. At last week’s 2010 Symposium on VLSI Technology in Honolulu, IMEC researchers described the mismatch in the coefficient of thermal expansion between copper through-silicon vias (TSVs) and the surrounding silicon. Using a 45nm digital analog converter test chip, the IMEC team measured transistor drive currents with TSVs located at various distances from the active circuits. Tensile stress near the TSVs was in the range of mega Pascals (MPa), declining to zero stress at a distance of about 10 microns from the TSV edge – a distressingly long distance for today’s leading-edge devices.

That kind of fundamental information (IMEC will deliver a more-complete paper at IEDM in December), Marchal said, is allowing EDA vendors and chip manufacturers to begin creating stress models. “Thermal and mechanical stresses induced by TSVs is a big worry for the community, but I believe there are different ways to mitigate them. A lot depends on what type of devices you use. Stress is not uniform for different types of devices; for example, long channel devices see more impact.”

At its Leuven facility, IMEC is fabricating a series of test chips, named after volcanos, which have sensors positioned at various places on the die to measure thermo-mechanical stress. “We position the smart sensors at the most critical places inside the stack, with the DRAM on top, to study the thermal and mechanical impacts. Then we provide the information to our supply chain partners, including the DRAM makers and packaging houses. Our partners, such as Qualcomm and STMicro, want to gain a head start. When they start RTL-level design they want to know what is feasible and what is not.”

Fig. 1: IMEC is working with several EDA partners to create a pathfinding flow for 3D prototype creation. (Source: IMEC)

While the EDA community is making progress, Marchal worries about is the relative absence of the packaging design community. Co-design of the die and package is particularly important as top die are thinned to 50 microns or less, positioned on top of a much thicker die.

“The die are becoming as thin as aluminum foil, and if you have the wrong glue, or different heat cycles, the die do not remain flat. That builds up stress across the die. The EDA and packaging communities need to be more active in how to analyze this,” Marchal said.

These challenges will be solved, particularly as increasingly large investments are being made in 3D TSV technology. At the DAC conference last week, Myung-Soo Jang, a design infrastructure manager at Samsung Electronics, described Samsung’s plan to use TSVs to link a mobile logic device with a 400 MHz DDR3 memory. “Because we are the world’s largest memory maker, which also has systems expertise from our cell phone business, we believe we have an advantage in this area,” Jang said.

Memory manufacturers such as Samsung and Toshiba, bring certain advantages, but fabless and foundry vendors are forming their own alliances, including EDA vendors and packaging houses. At DAC, L.C. Lu, director of the design methodology division at TSMC, called 3D TSV “the next killer application” and outlined a 3D design flow that TSMC is developing.

The mobile systems vendors need TSV interconnects to support the bandwidth needed for new data services, which include point-to-point video, a market set to accelerate over the next five years. High-definition video encoding requires about 12.8 GB/s of bandwidth between the processor and DRAM memory. The only way to do that in a mobile system is with TSV-connected logic-memory solution, using three or four tiers of die thinned to 30 to 40 microns. To achieve the same bandwidth, conventional DRAMs would require the power-hungry GDR5 DRAM standard, some 2,000 I/O pins, and a frequency that would kill any cell phone battery quickly.

Sitaram Arkalgud, director of Sematech’s 3D interconnect initiative in Albany, N.Y., said Sematech is focused now on a copper-copper bonding, vias-middle manufacturing flow that will come into use in several years. To tackle the stress challenge better standards are needed for how to measure and report thermal and mechanical stress levels. At next month’s Semicon West in San Francisco, Sematech and Germany’s Fraunhofer IZFP research center will hold a workshop on 3D stress management, including DFM-like approaches for managing stress, material properties, and measurement techniques.

Arkalgud said Sematech and SEMI are working on a data exchange format for TSV applications, and will hold a meeting on the subject at Semicon West and again at Semicon Europa in the fall.
“Especially as we go to thinner die the TCE and stress issues will be something we need to watch. To do that, we have to agree on how to measure it, so a data exchange specification needs to be there,” Arkalgud said.

By Cheryl Ajluni

At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs).

The concept of 3D stacking or integration technology is not new. In fact, 3D stacking of dies has been successfully demonstrated and is currently being commercially employed in some embedded domains (e.g., stacking DRAM memory on CPU cores). A recent 3D IC report from Yole Développement suggests that by 2012, the number of 3D IC-processed wafers could surpass 10 million units, driven in part by handset, wireless and computing applications. Given the intense interest and work going into developing 3D integration technology, this prediction seems just about right—assuming, of course, that a few challenges can first be met.

Exploring the third dimension

Very simply put, 3D integration consists of stacking integrated circuits and connecting them vertically so that they behave as a single device. A 3D chip is therefore just a stack of multiple device layers with direct vertical interconnects tunneling through them. So what’s the big deal about 3D integration?

Today’s semiconductor chips face extreme pressure to achieve increased performance, while reducing their size and accommodating lots of new functionality. When these factors coalesce in traditional 2D chips, longer interconnects result. In SoCs, longer interconnects translate into reduced speed and increased power consumption.

A key benefit of 3D integration is that it can reduce the length of interconnects. Additionally, it provides higher transistor density, faster interconnects and heterogeneous technology integration, with potentially lower power, cost and faster time-to-market. As Matt Nowak, director of engineering in the VLSI technology group of Qualcomm’s CDMA technology division, pointed out in a DAC 2008 presentation, the 3D approach “achieves extremely high densities, allowing us to use heterogeneous technologies and reduce form factor. The key is that it enables the use of new differentiating technologies to build new architectures that cannot be built in existing technologies.”

Eyeing recent developments

Up to this point, most efforts in 3D integration have focused on developing different fabrication techniques for stacking multiple device layers and forming the vertical interconnects. Much of the work has been done through collaborations with academia, industry organizations and government-sponsored laboratories around the world. One of the key technologies to come out of this research is a next-generation interconnect technology known as Through-Silicon Via (TSV). The TSV is a vertical electrical connection that passes completely through a silicon wafer or die to produce multilevel chips with an optimum combination of cost, functionality, performance, and power consumption. By using TSV technology, 3D ICs can pack greater functionality into a smaller footprint and realize shorter critical electrical paths, resulting in faster operation.

Some of the other developments to come out of ongoing 3D integration research were recently recognized at the Electronic Components and Technology Conference. Sandia National Laboratories presented details of its W TSV process, which is said to provide a suitably low-resistance metal with a coefficient of thermal expansion close to Si, a via fill that is conformal, and can be readily integrated into IC fabrication. IMEC introduced a novel process for die-to-wafer bonding (using Cu-Cu bonds) of its 3D SIC technology and a scalable TSV technology for 3D wafer-level packaging. Its TSV technology is designed for 3D structures where interconnects are fabricated after standard CMOS processing.

SEMATECH also is focusing its 3D research on TSV technology, particularly for implementation. The industry organization is actively working to bring together partners from across industry—chipmakers, equipment and materials suppliers, assembly and packaging service companies—to make 3D TSV suitable for high-volume manufacturing (Figure 1).

Figure 1. In contrast to the 2D-SoC or 3D System-in-Package, 3D TSVs offer a cost-effective way to achieve high density and performance, while also being able to integrate non-CMOS products with CMOS. The SEMATECH 3D project is based on cost modeling to assure products will be both manufacturable and affordable.

Help: tool support needed!

While ongoing research and development is absolutely critical to the success of 3D integration, perhaps one of the greatest challenges it faces is tool support in terms of design techniques and methodologies. Without it, engineers have virtually no efficient way to exploit the technology’s benefits. Tool support is especially critical when it comes to 3D integration because vertical stacking tends to increase thermal resistances, further exacerbating temperature-induced problems that can negatively affect system reliability, performance and leakage power. The use of 3D also will significantly complicate the typical design flow.

The key, of course, lies in creating a standardized design environment and methodology for physical design of 3D chips that could support a range of different tools. Having the tools integrated in one place would make it easier for designers to explore and make architectural decisions and then, to hand those decisions off to next stages in the design process.

3D IC integration is still in its infancy and, as a result, tools developed today for one specific application (e.g., stacked memory) may not be suitable for heterogeneous integration tomorrow. Nevertheless, there are some tools available now, with more in development. Some of these tools include:

3D PathFinding

Javelin Design Automation. 3D PathFinding provides a detailed 3D flow for accurate performance/power/cost estimates that can be used for rapid design exploration and optimization of 3D stacked ICs. Developed in collaboration with IMEC and Qualcomm, the solution extends Javelin’s existing PathFinding methodology and j360 Silicon PathFinder physical design prototype platform to support virtual chip design (Figure 2).

Figure 2. Javelin’s 3D PathFinding solution allows the designer to assess the impact of various 3D interconnect strategies throughout the IC design and fabrication process, in a matter of just a few hours or days. Silicon process engineers can use it to fine-tune their technology to the system architecture specifications.

MAX-3D, R3Integrator, R3CAD, and R3Artist; R3Logic

These tools, developed through work conducted as part of research programs sponsored by the Defense Advanced Research Projects Agency (DARPA), enable 3D IC design and analysis (Figure 3). MAX-3D is a 3D mask layout tool whose technology file includes all properties of stacking process, wafer orientations, bond materials, via electrical/material properties, and also incorporates 2D foundry design kits. R3Integrator is used for die/interposer/package co-design with TSVs. R3CAD is a java-based, multi-platform tool for 3D design research and prototype study and R3Artist is an embedded 3D layout editor (Figure 3).

R3Logic is currently collaborating with STMicroelectronics and CEA-LETI to develop a full 3D design flow for 3D heterogeneous system and system-in-package design.

Figure 3. R3Artist features single and multiple wafer technologies, integrated material properties database and solid model extraction, including dielectric layers.

3DCACTI

3DCACTI estimates the optimum access times and power dissipation of a cache using 3D IC technology for a given number of active device layers and by partitioning device layers for various technology nodes. Based on the estimation, it searches for the optimized configuration that provides the best delay, power and area efficiency trade-off according to the cost function for a given number of different 3D partitions.

3D Magic and PR3D, Massachusetts Institute of Technology

3D Magic is a comprehensive layout methodology for 3D circuit-layout editing and extraction with MAGIC, an open source layout editor developed by UC Berkeley. PR3D is a placement and routing tool for standard cell design in 3D. Both tools were developed through MIT’s Interconnect Focus Center Research Program. MIT also developed SysRel (System-Level IC Reliability) for assessing the interconnect reliability of 3D ICs from a thermal-aware perspective at the circuit-layout level.

Conclusion

With the pressure on traditional 2D chips mounting, 3D integration has begun to establish itself as a viable means of breathing more life into Moore’s Law. It certainly touches on all the hot buttons in the industry today, namely low power, cost and time-to-market. The challenge will be in ensuring that these benefits are realized in a timely and efficient manner. 3D-specific design tools and methodologies are coming to meet this challenge head on. In the meantime, the tools available now and the groundwork for future tools and methodologies being laid by industry organizations, academia and commercial companies alike, will go along way in ensuring 3D integration plays a critical role in the future of the semiconductor industry.