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Manufacturing Challenges 3D NAND Deployment

Thursday, August 31st, 2017

Jim Feldhan, president of Semico Research and veteran semiconductor analyst, shares his views on the challenges of moving from 2D planar to 3D NAND flash.

By John Blyler, Editor-in-Chief, Electronic Systems Design

3D NAND flash is touted as the eventual replacement for bit density limited 2D planar NAND flash. Its arrival into the mainstream memory market has been delayed by several years but should commence toward the end of 2017.  The delay has been caused by a steeper than expected learning curve in the manufacturing process. To understand why, Electronic Systems Design spoke with Jim Feldhan, founder and president of Semico Research Corp. What follows is a portion of that interview. – JB

Blyler: What are the general trends in NAND flash technology?

Jim Feldhan

Feldhan: 3D NAND is an evolutionary, architectural change that was needed to deal with the scaling limitations faced by planar 2D NAND memory. One major benefit of 3D NAND is that it will be manufactured on slightly older and less expensive process nodes.

Blyler: What unique costs are incurred for the manufacturing of 3D NAND Flash?

Feldhan: Depending upon the architecture, manufacturing at higher process nodes like 40nm can save money in terms of lithography requirements. However, since a common practice is to make 32 to 48 vertical layers or more in the 3D design, a significant increase can occur in etch costs. Holes must be etched between the different stacked layers to serve as inter-connections between the vertical layers.

Even though 3D NAND go back to older, higher process nodes for the lithography, the bit density is still increased via vertical stacking. The trick has been to fine tune the etch processes so that the yields remain good while achieving lower costs. Like any new process technology, it takes a while to get up that learning curve to maximize the yield.

Blyler: Increasing the need for additional etching should be good news to the semiconductor capital equipment companies.

Feldhan: Yes. With 3D NAND, you’ll have an array that is more like a cube or a three dimensional chess board with interconnections and wires going horizontally and vertically through the matrix. That is why companies like Applied Materials and Lam Research are thrilled since memory manufacturers will have to buy 5 or 10 times the amount of etch tools.

On the technology side, there has been interesting things with the resist, specifically, they can do several etches with the same coating of resist. More specifically, new materials on the resist allows for multiple etches without recoating. This process will save both time and money. [Editor’s Note: A resist is a thin layer used to transfer a circuit pattern to the semiconductor substrate which it is deposited upon.]

Blyler: Is 3D NAND more reliable than planar?

Feldhan: One of the original questions was how reliable is 3D NAND flash. The relaxed lithography node means you are not squeezing everything together so cross-talk is less. Also, 3D NAND has substantially more interconnections with vertical architecture that might provide you with access to more redundant cells. These redundand cells could be used if or when other cells fail. As 3D NAND has only been out for a few years, I haven’t really seen any lifecycle test data. But what I hear from Samsung and Micron is that 3D NAND is getting good acceptance from their customers. That’s impressive as many of the early customers are in data center applications that are really particular about failure rates.

Blyler: How does the Intel-Micron Optane differ from other 3D NAND flash technologies?

Feldhan: The Intel-Micron technology is called 3D Xpoint. They’ve described it as changing the physical properties of the material, which sounds more like a phase-change technology than a 3D NAND architecture. Further, the description made it seem different from the phase-change technology announced by IBM many years ago. Apparently, Intel-Micron have spent quite a bit of time working on a new material that they think solves all the problems faced by the original phase-change memory devices.

Blyler: So the Intel-Micron 3D Xpoint technology seems like it will be competing with 3D NAND flash. Is that correct?

Feldhan: Well, the XPoint platform is a different technology than with what everyone else is doing on 3D NAND. But Intel is doing both approaches, as I understand it. Their fab in China is gearing up for 3D NAND in production. My estimation would be that the Xpoint is a new technology and probably has a much higher bit cost, which would explain why they are focusing on SSDs and more so on the enterprises and server farm apps.

Blyler: Let’s return to 3D NAND manufacturing issues. At some point, won’t that technology need to move to the latest process nodes and/or contain ever-increasing layers to stay competitive with the bit cost?

Feldhan: Yes, they will eventually have to move to finer levels of lithography or be able to continue to go up in vertical layers. Or some type of combination. When the major manufacturers rolled out the first 3D NAND, they were saying it would be scalable, i.e., 24 layers at first, then 32 layers to 48 layers and etc. But I haven’t seen them progress as quickly as they mentioned. So I think they are now more focused on maximizing yield and reliability. [Editor’s Note: At the 2016 IEDM conference, SK Hynix discussed stacking technologies that could potentially enable over 256 memory cell layers.But it wasn’t clear when those levels would be reached.]

Blyler: When will 3D NAND become a mainstream memory technology?

Feldhan: On the plus side, the cost of 3D NAND is reaching equivalence with 2D planar NAND. Over the last year or so, NAND flash memory prices have been driven upward from tight supply and strong demand (see Figure). These aggregate average selling prices (ASP) are average prices for all densities and technologies.  As 3D NAND production comes down the manufacturing learning curve, the cost per bit for 3D NAND will fall and 2D NAND will have to match the price to remain viable in the market. Ultimately, 3D NAND will have the lowest cost per bit and will supplant 2D NAND especially in the large density parts.

NAND Pricing

Figure: With a tightening supply and strong demand, prices for all NAND devices are climbing. Before too long, 3D NAND will be on par with 2D planar memory. (Courtesy of Semico Research).

Blyler: Thanks, Jim.

Accellera Systems Initiative has taken over OCP-IP

Tuesday, October 15th, 2013

By Gabe Moretti

Accellera has been taking over multiple standards organization in the industry for several years and this is only the latest.  The acquisition includes the current OCP 3.0 standard and supporting infrastructure for reuse of IP blocks used in semiconductor design. OCP-IP and Accellera have been working closely together for many years, but OCP-IP lost corporate and member financial support steadily over the past five years and membership virtually flatlined. Combining the organizations may be the best way to continue  to address interoperability of IP design reuse and jumpstart adoption.

“Our acquisition of OCP assets benefits the worldwide electronic design community by leveraging our technical strengths in developing and delivering standards,” said Shishpal Rawat, Accellera Chair. “With its broad and diverse member base, OCP-IP will complement Accellera’s current portfolio and uniquely position us to further develop standards for the system-level design needs of the electronics industry.”

OCP-IP was originally started by Sonics, Inc. in December 2001 as a means to proliferate it’s network-on-chip approach.  Sonics CTO  Drew Wingard has been a primary driver of the organization.  It has long been perceived as the primary marketing tool of the company and it will be interesting to see how the company (which has been on and off the IPO trail several times since its founding) fairs without being the “big dog” in the discussion.

A comprehensive list of FAQs about the asset acquisition is available.

EDA in the Age of the System

Monday, July 31st, 2017

Learn from other industries to gain a system’s perspective was the reoccurring theme of Garysmith EDA analyst Laurie Balch’s pre-DAC address.

By John Blyler, Editor-in-Chief, ESDE

Once again, the system took center stage at the recent Design Automation Conference (DAC), an event focused on the software tools required to developed semiconductor system-on-chip (SOC) devices. These software tools typically fall under the heading of electronic design automation (EDA).

As per tradition, DAC kicked-off with a Sunday night “state of the industry” address by the analysts at GarySmith EDA (GSEDA). This year’s event was presented by Laurie Balch, Chief Analyst at GSEDA (see Figure 1).

Figure 1: Laurie Balch, Chief Analyst at GSEDA, presents EDA trends at DAC 2017 in Austin, TX.

She began by highlighting the positives with the chip design industry, starting with the diversity of both larger established and smaller start-up companies. Further, EDA is a mature market where litigations among the companies has more or less subsided. Finally, the chip industry is still very dynamic with lots of new product development.

The bad news is that there will be no double-digit growth for the traditional EDA space in the near future, at least not without a few changes, explained Balch (see Figure 2). More on that shortly.

EDA Growth Chart

Figure 2: Double-digit growth is not expected anytime soon for the EDA industry. (Courtesy GSEDA)

Broadening the Core

This begs the question as to the meaning of the traditional EDA landscape. In the past, EDA has provided tools in a number of development abstraction areas, including semiconductor chip gate-level and register transfer level (RTL) design-verification, electronic system level (ESL) design, packaging and interfaces to IC Computer-Aided Design (CAD) and Printed-Circuit Board (PCB) design.

“Since EDA is a maturing market, the industry needs to more beyond the traditional definition,” explained Balch. “In addition to the core EDA space, we have to include the embedded, mechanical and IP markets. These peripheral markets are central to understanding the future growth potential of EDA (see Figure 3).”

EDA Peripheral Markets

Figure 3: Expanded view of EDA markets and growth potential. (Courtesy of GSEDA)

Engaging with customers on the intersecting markets means that semiconductor companies must think about high-level systems. This is not a new observation. At last year’s DAC-2016, Balch predicted that EDA will see mechanical CAD vendors coming onto tradition semiconductor turf. This was confirmed with the recent acquisition of long-time EDA giant Mentor Graphics by Siemens PLM, a global systems, software and CAD business.

Mechanical CAD is only one of three markets that will help expand revenues to the traditional EDA market. The growth of semiconductor and embedded intellectual property (IP) over the last several years has already improved the revenue outlook. Adding mechanical design and embedded software will lead to further revenues, noted Balch.

Popular Tools

What were purported to be the hot new EDA market spaces at this year’s DAC? Balch provided the following list:

  • Analog/Mixed-Signal/RF
  • Emulation
  • System-Level Tools
  • Intellectual Property (IP)
  • Simulation & Verification
  • Circling the edges of EDA
  • Automotive

This list has changed little from previous DAC events. Perhaps the only difference now has been from the recent flurry of acquisitions which resulted in market share shifts among the three major EDA vendors.

What Does it Mean?

Today’s EDA is a market in transition, one that faces many challenges. Balch listed four main concerns:

  • Disappearance of double digit growth
  • Disruptive change vs. process improvement
  • Shift in vertical industry influences
  • IoT design impact

The disappearance of double-digit growth in traditional EDA markets has already been covered. Balch didn’t see disruptive changes in the market but rather a move toward more efficient methods in the overall chip development process. This was taken as a good move as process improvement is the right mindset for system development, she noted.

A shift to vertical markets could be a good thing for EDA, e.g., consider the rising growth in the automotive sector.

Perhaps the real challenge to EDA tool vendors is the rise of the Internet-of-Things (IOT). Designing for IOT requires changing some ways that EDA designs and offers their own tools, noted Balch. One big different is that most IOT designs don’t required the lowest and most expensive manufacturing nodes. I’ve noted other differences in the IOT design approach in other articles. (See, “Why is Chip Design for IOT so Hard?”)

Path Forward

One way to gain perspective on today’s EDA market is to look at it from another angle. For example, perhaps the mechanical design market will serve as a template for EDA. Balch pointed out the EDA originally grew out of the mechanical CAD space. Another comparison point is that mechanical CAD tools had a slow growth period similar to the one facing EDA. The latter emerged from its doldrums with new strategies that included reaching out to other markets.

Another change of perspective is afforded by the so-called “tall, thin engineer.” In the chip community (referencing Howard Sachs), a tall-thin engineer was a generalist with broad knowledge in many different fields rather than a specialist deeply involved in only areas, say IC design or layout.

Personally, I find this term misleading. A “tall, thin engineer” seems more indicative of a specialist, i.e., someone who has a deep (or tall) understanding in a very narrow (or thin) area of technology – for example, designing digital Silicon chips. In markets outside of EDA, the “tall, thin engineer” is known simply as a systems or systems-of-systems (SOS) engineer. Even this subtle difference in semantics highlights the difficulty that domain and EDA semiconductor engineers will face when expanding into peripheral markets like embedded software and mechanical systems.

Regardless of the semantics, many technical folks touch upon electronics, meaning that they have to deal with electronic issues for which they are not specialists. EDA can help them navigate the technical challenges but only if EDA itself has more generalists that understand the end-users perspective. Thus, the process by which EDA tools are developed would also need to be different. Balch noted that the tool obstacle was confronted by the mechanical community years ago, specifically in Computer-Aided-Engineering (CAE) tools for simulation. The result was new tools that could be used by engineers who were not experts.

Finally, vertical markets are directly influencing the EDA tool market. In the automotive space, Tier 1 companies are forcing their users to use specifically-qualified tools, e.g., ISO-26262. This influence will only continue. (See, “Fit-for-Purpose Tools Needed for ISO 26262 Certification”)

There are encourage signs that the EDA community is embracing other markets. Many presentations at this DAC focused on the new and rising markets of big data, machine learning and artificial intelligences.

EDA Call to Action

In conclusion, Balch listed three activities that would help rejuvenate the EDA community:

  • Recognition of EDA realities
    • Risks of standing still
  • Learn from parallel markets
    • Model for navigating the future
  • Repurposing EDA expertise
    • Creativity in abundance
  • Be fearless!

Foremost on the list was the theme of her presentation, namely, that future EDA strategies must continue to embrace the larger system world. The systems-view will help the community look and learn from other markets, esp. mechanical design.

“We should look at their history and see how they solved similar problems,” emphasized Balch.

The EDA space is well positioned to re-purpose their expertise into new markets, e.g., mechanical design, IP, embedded software and vertical markets like automotive and

Finally, Balch admonished the attendees to be fearless when seeking expanded markets, perhaps by focusing on design data management as well as high level physics-based technologies.

SoS Meets SoC as Siemens Buys Mentor Graphics

Monday, November 14th, 2016

System-of-Systems (SoS) company Siemens significantly expands with acquisition of Mentor Graphics System-on-Chip (SoC), board-level and automotive technologies.

By John Blyler, Editorial Director, JB Systems

Back in 2010, I wrote about the possible acquisition of Mentor Graphics by a large product lifecycle management (PLM) company with a strong embedded focus. At that time, the concern was which industry might profit from an EDA acquisition:

“In the past, many of us have seen suitors for both Mentor Graphics and Cadence Design Systems come and go. Those interested parties varied from financial/investment firms (such as the Cadence – Blackstone-KKR buyout), supply chain/ERP manufacturing companies, PLM design vendors (see my comments about Dassault Systemes) and even EDA-to-EDA (Cadence’s attempted acquisition of Mentor in the summer of 2008). [see, “What does Carl Icahn really want from Mentor?”]

It now looks like I had the right market but the wrong company. Today, Siemens announced its plans to acquire EDA giant Mentor Graphics. Among other things, this means that Siemens, “now offers mechanical, thermal, electrical, electronic and embedded software design capabilities on a single integrated platform.” In other words, Siemens becomes even more of a Systems company then before. I use the capital “S” to signify a multi-discipline, multi-domain, system-of-systems (SoS) company beyond just software, network, and even system-on-a-chip (SOC) technologies. Mentor Graphic will help elevate Siemens to a new level of Systems.

Unfortunately, it also means that our rather niche world of semiconductor EDA companies just got a whole lot smaller. I wonder who’s looking at the remaining players, namely, Synopsys and Cadence.

Related Articles:

Starting A New EDA Company

Thursday, February 20th, 2014

Gabe Moretti, Contributing Editor

Every once in a while the topic of what the EDA industry should be resurfaces.  In the last few weeks I have read ideas from Rick Carlson, Joe Costello and Chris Rowen.  All three are seasoned, successful EDA personalities who are, mostly due to the lack of new funding in the industry, unhappy with EDA.  Unfortunately all three must bear some of the blame, since they are part of the successful EDA entrepreneurs who made the industry what it is today.

By this I mean the industry is a service industry providing engineering tools to semiconductors and system houses to be used to develop and build semiconductor ICs.  The fact that the end users make much more money selling their products while EDA vendors fight over the Costello proverbial dog food bowl is a fundamental characteristics of a service industry such as EDA.  Yes, our technology is supreme and second to none, but we still just build tools to build ICs and thus the price of a tool is bound by the availability of similar tools fighting for the relatively few customers available.

Where are the new entrepreneurs?

I did not read any suggestions by Rick, Joe or Chris that would change the nature of the industry.  But what is worth nothing is the total lack of new ideas from younger people.  Are the new leaders all too busy finding new ways to gossip on the net?  Are we really all so lonely that we must post a picture of what we just ordered for lunch?  Is it possible that there is no other business plan in EDA than the old one developed when tilting an IC the proper way in the sunlight would show the transistors built on the substrate? (Yes I was there then).

The concept of unbundling the development of CAD tools in order to decrease costs and concentrate leading edge knowledge in a third party vendor is over thirty years old, an eternity in this business.  The problem I fear is complacency.  People like Rick, Joe, and Chris are comfortable with the professional and financial success they have achieved.

The disruption created by a new business approach is as scary as the prospect of a  large earthquake.  Is there any young creative person that can look at today’s reality and propose a new approach?

Given the vacuum I decided an old guy needs to speak up.

A New Model

To come up with a new business model one has, of course, to describe the requirements first.  Semiconductor process technology has progressed so much that the need for a greater number of transistors on a chip is no longer the principal concern for the vast majority of designs.  The majority of semiconductor products today are fabricated with 90 nm or 65 nm processes.  They are at least four generations ago!  Thus the pressure to continue to double the number of transistors every 18 months is practically gone with the exception of less than twenty system houses.  So the emphasis is no longer on transforming a RTL netlist into a network of transistors, but to architect an heterogeneous system that satisfies particular requirements.

A new successful EDA company is one that has the characteristics of Mathworks and ARM put together.  Mathworks focuses on providing solutions for specific application areas, while ARM provides components that are an integral part of the final product and thus benefits form the revenue generated by the end sale.

A new EDA company is one that understands thoroughly the application industry it serves and provides tools and components that enable the creation of leading edge products in that industry.  Providing tools to produce leading edge semiconductors is no longer profitable, since the customers base is so small.  But providing the same collection of tools and components to develop the smart home or the distributed medical industry is not.  I would have also listed automotive as an opportunity if it were not too late.  That train has left the station a few years ago.

The Bottom Line

If you want to start a new successful EDA company look at the system level.  Develop hardware and software components and the tools to assemble them together with third party proprietary components into a leading edge system.  Sell the environment, or give it away for free, and license the components.  Forget the silicon as your primary focus: it is just one way to implement hardware.  A few companies, less than a handful, will profit from enabling foundries, but many more will be profitable by being true business partners in developing end users products.

To read more from Gabe go to

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