By Ed Sperling
Mentor’s Mike Jensen looks at the “Rooster Tail,” the giant fan of water released out of three dams in the Pacific Northwest. Check out the photos and you’ll know why they call it the Rooster Tail. This would certainly be a rude awakening in the morning.

Synopsys’ Navraj Nandra examines whether DDR3L will ever make its way into mobile DRAM. The answer, apparently, is no.

Cadence’s Richard Goering peers into the details of 20nm RTL to GDSII methodology. This is like looking over Niagara Falls where manufacturability, timing variability and design size and complexity are churning at the bottom. Better reinforce the barrel.

DeepChip’s John Cooley focuses in on the changes on Mentor’s board of directors, notably that two of Carl Icahn’s three choices for the board have been replaced. This gives new meaning to hot swapping.

NXP engineer Chris Hill, standing in for Mentor’s Robin Bornoff, looks at diminishing returns in thermal design of PCBs and how extra copper layers don’t always help. Given the price of copper these days, no one will argue.

Independent blogger Gaurav Jalan examines the list of challenges for verification teams, providing some insight into why it takes so long to get a chip out the door. Even more disturbing, though, is that confidence in the final product appears to be on the wane.

Synopsys’ Eric Huang had one of those “ah-hah” moments about the limits of family involvement in technical subjects. You do what for a living? Is that legal?

Cadence’s Jason Andrews looks at simulation performance on a Zynq virtual platform using VirtualBox compared with native Linux.

Si2’s Steve Schulz previews what his group is doing at DAC this year, which will include a rundown of all the standards efforts under way at the moment—or at least the ones they’re talking about in public.

Mentor’s Brooks Moses looks at the embedded software in a control cluster of an unmanned aircraft and how difficult it is to program to get maximum performance. In this case, “maximum performance” may mean different things to different people.

By Ed Sperling
Synopsys’ Navraj Nandra takes note of a shift in set-top boxes. Think about Skype on your TV over HDMI. This adds a new dimension to reality TV.

Cadence’s Richard Goering reports on a presentation by Samta Bamsal about design challenges at 20nm and 14nm, most notably double patterning implementation, thinner gate oxides and widely varying voltages. Take notes.

Mentor’s Chris Hallinan launches a new blog about embedded software, although this one is mostly about boating, flying, Morse code and GNU/Linux Aviation code.

Si2’s Steve Schulz looks back on 10 years of OpenAccess and how it has evolved. This one turned out to be a lot better than anyone initially thought.

Synopsys’ Karen Bartleson talks with Roy Jewell, former president and COO of Magma, on his journey from physicists to engineer to business leader. And given Synopsys’ recent acquisition of Magma, now what?

IHS iSuppli’s Andrew Rassweiler shows off the bill of materials for Apple’s new iPad 3 and why it costs more to produce than the iPad 2 even though the retail price is the same.

Cadence’s Robert Dwyer talks about collaboration, concurrency and convergence, which were top themes running through this year’s Cadence User Group event, aka CDNLive!

Synopsys’ Eric Huang has posted a video record of his recent trip. That’s “trip” as in falling over. Ouch.

By Pallab Chatterjee
Stacking die has progressed from what is technologically possible to what will be realistically feasible in a fabless or fab-lite world. The big challenges may be less about how to deal with stress caused by a TSV or thermal density and more about companies working together in a disaggregated supply chain.

This was quite evident at a recent DesignCon panel dicussion on 3D die and assembly standards. The panelists—Riko Radojcic of Qualcomm, Sumit DasGupta of Si2, Liam Madden of Xilinx, Raj Jammy of SEMATECH and Jim Hogan of Vista Ventures—had widely different views about what needs to be done.

Both Qualcomm and Xilinx are in production with products that use TSVs and other stacked die technologies. Sematech and Si2 are focused on future directions for being able to implement what these companies have accomplished, seeking commonality in process and design across dissimilar businesses and markets.

Hogan zeroed in on the realities of production and getting parts into the marketplace, downplaying standards that result in everyone working together happily. The challenge, he said, is the rules for these stacked die are based on what you do with them.

The Xilinx product has a fixed pattern logic array (FPGA core) and fixed memory blocks connected together in a pattern that conforms to both its design architecture as well as its design software base. These pin placements, pad locations on the die, and stacking methodology are not necessarily applicable to other vendors or custom designers that could benefit from standardization of Xilinx’s tooling. As a result, moving forward without a standard is not a big deal for this application.

Qualcomm has a similar situation for its stacked die, which is targeted at cell phones. The company’s RF and logic cores and second chip memories, which are driving the use of stacked die, have different I/O issues. Compared with Xilinx’s application, Qualcomm’s has different pin counts, different performance for these connections and a much different reach. This is a custom processor that can be laid out over the local RAM, creating a clock-optimized design that minimizes the delay path for the system design.

Based on the unit being created—whether it’s a smart phone, feature phone, tablet, TV or set-top box—there are different assembly guidelines and goals for the 3D stacking. These designs heavily utilize traditional edge-based pin connections. Qualcomm already has a history of stacked die production. It has used this knowledge base to make more aggressive chipsets and product solutions, so at this time sharing that marketplace information has a limited value.

Hogan noted there is a need for commonality in processes, so every like microprocessor can contact a standard product memory, but custom processors and custom memories need not conform. It’s the same with standard logic functions being available as both MPW samples and DFW that are implemented as a high-level standard function IP. The challenge becomes when is it IP and when is it package assembly? While the technical model may want to have standards in the loop to address a TTM reduction, the business model for incorporating those standards is behind the pace of implementation that is dictated by the product rollout schedules. The market cannot wait, and products have to be shipped.

Hogan also brought up the concept of IP for the 3D interconnect and its encompassing system. If there are standard locations (similar to the JEDEC ones that are already in progress), will these include electrical specs, thermal and materials models, abstracted simulation models, reliability information, and test for both sides of the interconnect point as well as the interconnect point itself? Creating a specification of location and order without these aspects does not help the time-to-market challenge facing the semiconductor industry.

Unlike the power supply debates, which were fostered as two standards from competing EDA companies with differing politics of design—the 3D market is not a single problem with different approaches. It includes different design applications in different manufacturing chains that require some pin commonality.

By Ed Sperling
Synopsys’ Michael Thompson uses the local Israeli road navigation technology, which links to other drivers, to sort through the traffic mess. This is like crowd control at its finest.

Mentor’s Dennis Brophy looks at the next steps for UVM—stability, making it easier to use, and a way of bridging System Verilog with SystemC.

Cadence’s Richard Goering examines the need for really high-speed data transfer inside data centers. That would be up to 100 GbE (gigabit Ethernet) SoCs with as many as 10 data pipes. This is what’s really going on in the cloud.

Si2’s Steve Schulz raises an interesting question: How do standards affect mergers? The reverse of that question is interesting, too: How do mergers affect standards? It all depends on how much market share you can afford.

Synopsys’ Hezi Saar compares CMOS to CCD image sensors in digital cameras. CMOS wins on power consumption, cost, performance and integration. Well, that should just about cover it. Anyone still banking on CCD?

Mentor’s Colin Walls examines the user interface on an electric toothbrush. This is what engineers think about before going to bed.

Cadence’s Jason Andrews test drives a Linaro file system on a virtual platform for Xilinx’s Zynq. If you’re working with ARM cores, bookmark this one.

Synopsys’ Eric Huang claims he was forced to do a video under threat of donut sanctions. Considering the average donut has almost no nutritional value, this isn’t all bad.

Mentor’s Jim Martens is seeking information on the job market. Hopefully it’s just intellectual curiosity.

TLMCentral’s Tom De Schutter interviews Arteris’ Kurt Shuler about TLMs and earlier multicore SoC architecture optimization.

IHS iSuppli’s Mike Howard predicts a merger between Micron and Elpida could redraw the competitive landscape of the memory market.

Synopsys’ Helene Thibieroz provides 10 performance tips for CustomSim. If your simulator is too slow—and everyone’s is these days, which is why emulation sales are way, way up—this can only help.

By Ed Sperling
Mentor’s Harry Foster digs into formal verification for non-experts. It’s not exactly push-button verification, but at least this is a step in the right direction.

Speaking of verification, Synopsys’ Alex Seibulescu sheds some light on convergence-driven coverage modeling. The premise is that for multiple different models, you should always choose the “easiest.” Note the quote marks. In verification, nothing is easy.

Cadence’s Richard Goering looks at the Open NAND Flash Interface, which should help eliminate a performance bottleneck in nonvolatile memory. These kinds of standards are very good for the IC design world.

Si2’s Steve Schulz writes about measuring performance in standards development, breaking it down into four categories. This is a big step in the right direction.

Semico’s Tony Massimini examines the effect of the Kindle Fire on the iPad. Hint: Don’t short Apple stock based on this one.

Mentor’s Robin Bornoff talks about the heat generated by e-mail and links this to Jeff Bridges, the actor. Well, sort of. Bridges, routers and switches are key components of the Internet. The pictures in his blog are not.

Synopsys’ Tom DeSchutter, writing in TLMCentral, looks at the open-source component in the model portal. The rating system is particularly interesting.

Cadence’s Jason Andrews found a gap between the virtual model and the Linux OS. Here’s how to get around it.

Mentor’s Colin Walls has begun inspecting his wireless world. Not all of it can be identified, however. He’s looking for volunteers.

By Ed Sperling
System-Level Design sat down to discuss the future of stacked die with Riko Radojcic, director of engineering at Qualcomm; Prasad Subramaniam, vice president of design technology at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that conversation.

SLD: Where are we with 2.5D and 3D?
Radojcic: I think 2.5D was a misnomer, because that implies they are sequential. It’s clear that what we call 2.5D and 3D are going to co-exist for a long time. Some things make sense with an interposer and some make sense to be 3D.
Reiter: I agree—2.5D is a parallel effort to 3D. Lots of things will not use 3D because it’s too expensive. In 2.5D we will see production this year. With 3D it will take until next year for the first ones. I would guess computing or networking would be the first.
Radojcic: I would think those guys will pursue 2.5D.
Subramaniam: Memory makers are already offering 3D solutions today. If you look at just the memory chip, to increase the size of the memory rather than the die they’re stacking it vertically. That kind of 3D is already in production. It’s the question of co-mingling logic and memory that will take time. The advantage of 2.5D is that it allows afterthought. It allows you to take an existing design and to create a new set of I/Os and put in a 3D type of application.
Radojcic: I see no value in doing that. You’re creating an expensive solution to something you can do more cheaply. If you add the 3D interposer you’re adding another wafer. That’s cost. We can solve that problem with a flip chip. It’s cheaper.
Subramaniam: I disagree. We’ve done the analysis. It allows us to take an existing design, like an ARM subsystem in 28nm, even though surrounding logic doesn’t have to be at that 28nm process node. It can be 40nm or 65nm. Rather than building a new chip at 28nm, I can take my existing design, use it as one component of my 3D IC, and build a second chip in a cheaper, older technology.
Radojcic: Yes, as long as you’ve architected your chip like that, such that you can partition it.
Subramaniam: You can’t take any design, no. There has to be some partitioning in the architecture and some forethought. It’s not 100% an afterthought, but there is still some afterthought there.
Radojcic: You have to architect for it. If you haven’t done that, taking an existing chip will just cost you more. If you have done that, of course there is an avenue to doing things better and more flexibly.
Subramaniam: There is enough flexibility in designs that allow you to partition it in some manner.
Radojcic: True, but before 3D came along most of us wouldn’t have partitioned. We wouldn’t have architected it that way. To be able to leverage that value proposition, you must have 3D in mind.
Gianfagna: That’s true. It’s a premeditated act. If you don’t think it through way up front it doesn’t work.
Subramaniam: Because the SoC has a well-defined architecture, it lends itself to this type of application.
Radojcic: But only if you plan for it ahead of time.

SLD: Is this true in all cases?
Reiter: That’s the view of a high-volume supplier. I see low-volume solutions where they use an existing die, put it face down on an interposer, and connect memory to it. So for low to medium volume, 2.5D works. You call it an afterthought. I call it a customized solution.
Radojcic: Why wouldn’t you do that in a traditional multichip package?
Subramaniam: Because you don’t get the interconnectivity. The advantage of a silicon interposer is that you get thousands of interconnects.
Radojcic: But you have to design it sufficiently so you can leverage the interconnects from die to die. If you had designed for a traditional design, though, you would say, ‘I can’t have thousands of interconnects so I’m going to make a serial interface with 100 pins.’ If you take that design for a 100-pin interconnect and stick in an interposer it’s an expensive way of doing things.
Subramaniam: You may be able to take some internal signals out, which you are not able to do with a traditional MCM (multi-chip module) approach.

SLD: Let’s do a reality check. How far along are we toward stacking?
Gianfagna: Last year we had a hot-wired 3D system that was 2D with a bunch of scripts and manual effort. The customer base had strange, contrived designs and they were trying to see what they could and couldn’t do, and the foundries didn’t know what they wanted to do. A year later we have native 3D planning capability, the customer base has specific designs for implementation this year and next, and the foundries have a laser-sharp focus on process learning, mostly around 2.5D initially. If that’s a metric, things are clearer this year than last year. From an EDA perspective, I still think the market is two years away. But we still think this is big.
Reiter: If you look at the Atom chip with the FPGA from Altera, that’s basically a 2.5D solution. The FPGA is for customizing things. The Atom chip was not designed for this application.
Radojcic: But why use an interposer? Why not use a substrate and a multichip package?
Reiter: You could do that.

SLD: What’s missing from the tools side to make all this work?
Reiter: The ability to demonstrate what this technology can do is the most important capability. If you look at big corporations, top management is still hesitant to invest in this technology. If we could demonstrate in a credible way what it can do, people will be more successful in getting money to start programs using this technology.
Gianfagna: The way that happens is the early adopters blaze the trail, everyone tries to follow and the market heats up. What’s needed are commercial drivers. The tools aren’t there, but they’re close enough.
Subramaniam: The tools are not the issue. The development needed to support 3D is incremental. It can be done with the existing infrastructure. It’s really the end application.
Radojcic: Other than path-finding, which is hard to do with traditional tools. And the analysis.
Gianfagna: The complexity is higher. We’ve discovered that, too. RTL prototyping for a single chip has a certain set of challenges. When you go to 3D the modeling requirements are much greater, the constraint generation is more complicated. And we need standards. We can generate all the constraints, but we don’t know where to put them and how to express them because there is no agreed upon way to do that.

SLD: Do the standards organizations know where to start with all of this?
Radojcic: Standards are on a good track. We’ve worked with Si2 and Sematech to propose initials blasts for standards so we can feed them into Si2 and the EDA community and accelerate the process. The bits and pieces are moving, and we are on track to have a set of design exchange format standards by early next year.
Reiter: And Wide I/O.
Radojcic: Yes. The standards are channeled and the engine is revving.
Reiter: We have a bunch of players in a 3D enablement center participating. There are 15 companies listed, including Intel, IBM, TSMC, GlobalFoundries, and so on.
Radojcic: The way this was set up was Sematech said we are going to start a 3D enablement center initiative driven by the SIA. All the members of Sematech were mapped into this. Then a number of companies like Qualcomm, LSI and ASE joined.

By Ed Sperling
The semiconductor industry has been one of the most prolific sectors in history when it comes to generating standards. Talk to any design engineer facing time-to-market pressures, new packaging approaches, and a mindboggling number of merchant IP, subsystems and interface requirements, and you’ll hear a compelling pitch for new standards. Talk to his or her boss and you’ll probably get an earful about how there are too many standards that need to be supported.

The truth is they’re both right. There are too many old standards and not enough new ones. Where technology converges and uncertainty adds risk, standards are considered essential. They improve time to market, help get multiple companies speaking the same language and moving in the same direction, and they can bring enormous cost savings.

But when standards are no longer needed, they tend to stick around forever—like space junk. Standards need to be maintained and updated. But the work of updating standards, which includes reassessing them regularly and combining them with other standards when it makes sense, is even less glamorous than developing the standards in the first place, and certainly more tedious. Moreover, there is even less direct economic benefit to developing those updates.

The result is that the industry is littered with old standards while the din rises for even more. Scott McGregor, president and CEO of Broadcom, said his company is involved in about 100 standards efforts at any one time.

“Standards need to evolve, and new standards drive innovation in larger markets. “But standards also need to go away when it makes sense.”

He’s not alone in that viewpoint. John Goodenough, vice president of design technology and automation at ARM, said the industry needs to “keep collapsing standards down.”

Standards to ease pain
Wherever there is a pain point—particularly one where multiple vendors are involved—there is discussion about standards. Sometimes it’s a way of slowing down a market leader. Sometimes it’s a way of slowing down everyone else who follows the market leader. But in all cases, it requires an almost superhuman commitment to negotiate an outcome because each company has its own agenda, and standards in many ways are a compromise.

“That’s why standards happen at the edges of the network,” said Charlie Janac, president and CEO of Arteris. “We’ve got standards like AXI (Advanced eXtensible Interface) and OCP (Open Core Protocol). And there will be new standards as we move from 2D to 3D, but those are just being established. The goal is that customers shouldn’t have to care about what they use. It should all just work.”

But getting things to work also requires a lot of translation, which is the really hard stuff in developing standards. Drew Wingard, CTO of Sonics, said the most effective standards are ones that allow engineers to work with their own terminology and still provide useful information to other groups using different terminology and data.

“The folks worrying about video use a different number than the people who are worrying about graphics processor performance,” said Wingard. “The best thing we can do is keep it at that level. But asking one group, like the architects of a subsystem, to adopt my vocabulary, is counterproductive. A better way is to come up with a simple language.”

That’s easier said than done, of course. Ask anyone about power formats these days and you’re likely to evoke a sour look. UPF 1.0, IEEE 1801 and CPF are all standards, but they don’t work together. There has been a big improvement in cross-standard functionality, thanks largely to the efforts of Cadence, Mentor Graphics and Synopsys, and there are now cheat sheets about how to read one versus the other. But the hard work now under way is to bridge those two with a Rosetta Stone type of translation.

While the existence of multiple power format standards still rankles customers—many of whom are quite vocal about it because they use multiple vendors’ tools and IP, which favor one format over the other. But at least the problem is being addressed, and it has served as a warning against developing standards prematurely—or without all the essential players involved in the planning process.

Works in progress
This hesitancy to put a stake in the ground for standards is particularly evident in the 3D stacking arena. Si2 and Accellera have spent the past couple years just watching the process, trying to figure out where standards will be best served.

So far, these efforts are more general than specific, as companies attempt to narrow down what will be effective. Dennis Brophy, vice chairman of Accellera, said the real drivers of these efforts are time-to-market pressures and more complicated, larger systems.

“You clearly can’t start from scratch, so you need to re-use IP,” Brophy said. “That should lead to a more reliable design and quicker verification. But you also have to catalog and store these IP blocks.”

Accellera has puts a stake in the ground for system-level IP integration—work is underway to significantly improve IP XACT. Sonics’ Wingard said what’s really needed is a way of describing the IP that companies are being asked to integrate.
“The days when you spent more money integrating IP than in buying it are over. We expect it to be a black box.”

Accellera also is is pushing for UVM to be part of the system-level verification flow. This is easier said than done, because companies are still investing heavily in VMM and OVM, the verification methodologies that UVM is supposed to supersede. Accellera also is examining what standards will be necessary in software so there is some sort of bridge between SystemC, analog/mixed signal, and system Verilog.

Analog/mixed signal and 3D
Analog is a particularly thorny subject when it comes to standards. The sheer complexity of the problems being solved has surpassed the ability of analog designers to do everything manually, requiring far more automation than in the past. In addition, with stacked die looming in the future, a consistent way of writing analog is now required because the analog will probably reside in a separate subsystem or on a separate die that must be integrated with other die.

“This has to be a black box so it can be sold and integrated,” said Simon Butler, CEO of Methodics. “But how do you prove that it works when you get that block? You need a standard way to test it.”

He said that IP-XACT will address some of those concerns with digital IP for a consistent way of creating testbenches and defining what’s in an IP block. Analog is another story entirely.

“In 3D, there will be dependencies created,” he noted. “We need to add context into all of this.”

The road ahead
Si2 has plotted a number of standards it plans to work on in 2012. Topping the list are the following:

1. OAC: New release of OpenAccess to include scratch designs and other functionality and performance enhancements.
2. DFMC: OpenDFM 2.x will include DRC+ and other enhancements, while OPEX 2.x will include open parasitic extraction parameters and OpenLVS
3. LPC: Updated power modeling standards to support handling power intent and verification for large IP blocks
4. OpenPDK: New OPS 1.0, the Open Process Specification, will include a symbol standard, a design parameter standard, and a callback standard, and all other design parameters. In addition, all work started in 2011 will be completed.
5. Open3D: Standards are expected to be released to address definition of the power distribution network across the die of a 3D stack; thermal design and analysis of an entire 3D stack, including thermal constraints between neighboring dies; and expression of design constraints into and out of the path-finding and floor-planning stages of the overall design process. All work started in 2011 will be completed.

The road behind
Getting rid of the old standards, or at least collapsing them and making them more useful, is a subject no one wants to talk about. But venture capitalist Jim Hogan did have an interesting observation about just how long standards stick around.

At a recent Synopsys interoperability forum, Hogan noted that Roman roads were constructed exactly 47 inches wide to accommodate two horses used to pull a chariot. He said the distance between rails is the same distance, and the seat in his car is exactly 23.5 inches wide.

So far, no one has seen a need to adjust that number.

By Ed Sperling
Cadence’s Richard Goering reports on a three-die stack tapeout with TSVs from CEA-LETI and ST-Ericsson. Consider this proof of concept.

Synopsys’ Hezi Saar examines the Chinese mobile electronics market, where Nokia is still the market leader. Be sure to check out the photo. This must be a blind date. “I’ll be the one wearing the green feathers.”

Mentor’s Colin Walls looks at the divide-and-conquer approach to testing multi-threaded applications. It’s not so much the individual threads that cause problems. It’s when you tie them all back together that the problems really begin.

Si2’s Steve Schulz peels back the covers on the upcoming Open Parameters for Extraction (OPEX) standard that will be introduced by the DFM coalition early next year. This is important stuff. Anything that can more tightly couple front-end design to manufacturing is very important, particularly at advanced nodes and in stacked configurations.

Also on the subject of standards, Synopsys’ Karen Bartleson rolls out part three of her epic on why we need standards. Take her word for it. We really do.

Gaurav Jalan, a verification engineer writing in his Siddhakarana blog, looks at constrained random verification and how it played out in core designed for intensive performance.

Cadence’s Joe Hupcey reports the highlights from ARM’s TechCon 2011. The sub-20nm stuff is particularly noteworthy. But wasn’t the Rubicon Caesar’s point of no return? Or maybe that’s the point.

Mentor’s Mike Jensen looks at the challenges of using yesterday’s tools plus experience to design current technology. Chances are you could do it, but not quickly enough to stay employed. This should create some interesting turmoil in the workplace.

Synopsys’ Eric Huang notes that Intel has achieved USB certification for its 7 Series chipsets. Add in FinFETs and things will get even more interesting.

By Ed Sperling
Hitting market windows with IC designs has always been a struggle, but the race to the finish line is becoming more critical—and much more difficult. The reason: Market windows themselves are shrinking.

Products that used to stick around for years may now only last for months, replaced by newer versions that offer either better performance or lower power. In many cases, particularly for the hottest consumer markets that drive the highest volumes, there isn’t even time for competing on cost with derivative chips. The so-called long tail of design now looks significantly shorter, overtaken by a quick ramp up to the next SoC.

This raises a slew of new concerns among chip designers about which market opportunities are worth the risk, at which process node, and how to get there quickest with the least amount of risk. It also raises issues among tools developers about how many customers there will be for tools if the largest customers skip process nodes. And it raises the stakes across the board for making bad decisions, because they can no longer be amortized across dozens of derivative designs.

Changing market dynamics
What’s behind much of this is a shift in consumer buying habits. It’s not that consumers necessarily buy more devices, but they buy them much more quickly after the release date. The iPhone 4S was a classic example. Within four days of its introduction sales had topped 1 million units, something that took years for previous product lines.

“We used to be able to use a shotgun approach,” said Mike Gianfagna, vice president of marketing at Atrenta. “Now it’s more like a precision rifle shot. And if you don’t hit it just right, the market is gone.”

Time-to-market has escalated from important to critical. But for most companies that also involves a disaggegrated supply chain, which tends to slow down the design process more compared with IDMs such as Intel and Samsung, which have regular communications between fab, design teams and debug operations.

“What we’re heading toward is virtual re-aggregation,” said Gianfagna. “But that’s going to require speed and perfection, a lot of standards, and changes throughout design.”

It also changes the rules about how companies go to market with new ideas and technology.

“Traditionally, people went into market to test the waters,” said Neil Hand, group marketing director for Cadence’s SoC Realization Group. “The way things are now, you have to get it right. And if you’re successful, you have to quickly turn out new products. Product planning is important, but you also have to build in flexibility.”

Multi-patterning, packaging, and physics
It also requires some techniques and approaches that were not even considered in the design process until very recently. Sequential flows are now concurrent, with manufacturing now an important element of the early design phase. One area that is a particular trouble spot involves lithography, where EUV has been considered the best hope for etching extremely thin lines. EUV was expected to be commercially viable years ago. It’s still in the development stage, which is why the industry is heading to double patterning at 22/20nm. And that slows down the whole process significantly.

“Double patterning means you’re splitting a single mask up into two masks,” said Wally Rhines, chairman and CEO of Mentor Graphics. “And at 14nm we’re still uncertain whether the solution will be EUV or triple patterning. It could be either one. It depends on the development schedule of EUV. We may have a node that starts out without EUV and ends up with EUV. From the perspective of power and throughput it’s still a long way from production-worthy. The backup is triple patterning. It’s undesirable from a cost point of view.”

For an industry that has banked heavily on proven techniques and processes, this is a remarkably untested future with a very uncertain throughput and cost structure, filled with a variety of other risk factors.

Stacking of die will complicate that further, because understanding the stress impact of TSVs remains fuzzy, at best. Interposers are slightly better tested, particularly more advanced versions that potentially use new materials. In addition, wide I/O standards are still being developed, and so are ways of connecting all the pieces together, testing and debugging them, and figuring out how to deal with heat dissipation.

There’s also a question about what will get valued most in this new approach—and where the development dollars will go for tools. That also can affect time to market, because if the tools aren’t updated or integrated companies will have to do that work themselves—something they’ve done in areas such as rapid prototyping until recently, when commercially integrated solutions became available.

“It’s a little like the automotive or aircraft industry,” said Rhines. “The people who put the pieces together are system integrators. They deal with multiple die. They deal with software. They deal with interconnects. They are system designers. Then the individual die, an the individual IP, are component suppliers to each other. Today that IP serves as a barrier, but it will commoditize. System integrators get paid more than component suppliers, and components become commodities.”

Unbundling and future changes
One way to facilitate these kinds of changes is by unbundling the individual pieces in an SoC.

“There are really relatively few new hardware blocks being added to new designs,” said Drew Wingard, chief technology officer at Sonics. “The exception is the continued improvement in processor cores from ARM or graphics engines. Mostly it’s continued pressure on integration, and we believe strongly the only way to deal with this effectively is to isolate the components.”

He noted that interdependencies make it difficult to advance one component in a package without also making changes to another component. That has proven particularly problematic for mixed signal blocks, where shrinkage of digital features has forced similar but extremely painful shrinkage of analog processes. By separating those worlds, progress can be made in both portions of the block when it makes sense.

“If you can decouple the verification you can divide and conquer,” said Wingard. “That allows you to do verification at the subsystem level and re-use testbench code. A lot more companies also are thinking about designs in a platform-based way. A platform is a set of decisions you’ve made, and then you abstract up and down.”

Platforms have been talked about for years as a future direction. Intel, which used to churn out dozens of different chips for various PC markets, adopted a platform approach with the introduction of its Core architecture. ARM has done the same with its Cortex line. And while SoC developers have had a much more difficult time with this approach, many of components within those chips are developed using a platform approach.

But every decision has ramifications in an SoC. While it’s okay to unbundle the components, everything is tied to everything else in ways that extend well beyond the chip.

“When you develop a chip in the wireless space you have to make sure you’re in sync with the carriers, the handset makers, and the whole value chain,” said Kurt Shuler, director of marketing at Arteris. “This becomes a problem when you start shrinking the design time. It used to take 18 to 24 months to gather requirements to put a chip out there. Now the best designs take 9 to 12 months, and the most advanced companies are pushing to get that down to 6 to 9 months. The only way to do that is with a platform approach where you have one hardware and software platform and you can re-use the hardware and software investment.”

Re-use is driving a significant portion of Synopsys’ business these days. It’s no longer just IP blocks that are being sold. It’s IP plus software, and often in conjunction with services.

“We absolutely believe the next major evolution is subsystems of larger integrated blocks,” said John Koeter, vice president of marketing for Synopsys’ Solutions Group. Those subsystems increasingly are customized for very specific markets, as well, to both reduce risk and decrease the time it takes to get an SoC out the door. “These are very market-specific, he said. In the audio area an MP3 will have codecs that are different from a home entertainment system. We’re also seeing an increased willingness among companies to outsource. It’s not just small companies, either. It’s also the big tier-one companies that are questioning whether a USB is differentiating their chip.”

The push for more standards
Platforms also require standards, and there is mounting pressure on all of the standards bodies to ramp up the number and quality of standards—and to avoid dual standards such as UPF and CPF. But hidden in all of this also is a recognition that vendors will have to pick their battles. They can’t compete on all fronts and still have progress in standards.

“Standards are created largely around efficient ways of exchanging data in design and manufacturing,” said Steve Schulz, president and CEO of Si2. “If you had to re-do models for every foundry chip that would quickly get out of scale. Standards allow companies to get to market faster.”

That becomes more difficult in stacked, however, which involves more companies from across the supply chain. The promise of stacked die is re-usability, possibly with entire logic or analog “platforms” as part of the stack.

“Everything about 3D is a supply-chain view,” said Schulz. “You need to understand the whole landscape to do anything in 3D. How do you describe hot spots on a die? What’s the basic connectivity between the package and the pins? How are you going to develop the interposers? If you create process design kits will they need to understand the process impact of TSVs? And when is all of this going to happen? We’re not sure about the time frame.”

Conclusions
Dealing with time-to-market pressures has always been a concern, but rarely did being late to market mean missing out on the market entirely. That reality is changing, however, putting pressure on teams to figure out ways to ensure quicker turnarounds with better results.

Software, in particular, is a problem that needs to be dealt with effectively. As Cadence’s Hand says, “We need to bring down design and manufacturing costs, but software is still the killer.”

To some extent this is likely to force some hiring in the industry. Companies never replenished their ranks after laying off engineers in 2008. It also will require more tools, because automation is much faster in the hands of trained engineers than spreadsheets and trial and error. And it will require renewed cooperation to push through standards in areas where companies can agree it’s not necessary to compete—or where competition may slow down entire markets.

These changes also are likely to reshape the IC industry in ways we cannot even begin to comprehend at the moment. At the base of all of this is a fundamental and global shift that time to market will no longer be determined from the bottom up. It will be driven from the top down—by the consumers of the technology who are willing to spend quickly and decisively rather than mulling purchases for months or years. The winners will be those that can figure out a way to meet that need—and the losers will be either quickly absorbed or, worse, forgotten.

By Ed Sperling
Mentor’s Dennis Brophy digs into what’s happening with IEEE 1666, the revision of the SystemC standard that includes transaction-level modeling support. This is a good move for the system-level design world.

Cadence’s Richard Goering has his own take on the SystemC standard, as well. As he notes, this is the first revision of the standard in six years. That’s an indication of just how complex this stuff has become.

Synopsys’ Doug Amos examines partitioning in FPGA combinatorial pathways and the best ways to achieve it. This is like thinking of multiple FPGAs as a single system. It’s an interesting concept.

Si2’s Steve Schulz looks at managing patents and how to avoid some nasty surprises while working collaboratively on standards. Attorneys probably don’t want you to read this stuff. These kinds of missteps are good for business—well at least their business.

DeepChip’s John Cooley reports concerns over single-vendor flows vs. best-in-class tools. Given the fact that most companies insist on using multiple vendors’ tools—there wouldn’t be a lot of noise over CPF-UPF interoperability otherwise—this may be a lot of posturing on all sides.

Mentor’s Dave Rich peels back the covers on UVM, notably why you need to use it, how to use it, and what to expect. There are lots of links, as well. Plan on sticking around awhile.

Cadence’s Jim Newton unfurls part four of his epic on SKILL for the skilled, this one essentially a class about classes.

Mentor’s Faheem Sheikh provides some tips to working with multicore implementations and what to do about device drivers. Considering the human limitations of programming symmetrically instead of serially, there are some practical ceilings for the number of cores in a multicore design. Once you figure out that number, here are some things you’ll need to know.

Semico’s Tony Massimini reports a positive buzz in the MEMS market, from upbeat market predictions to talk about improving time to market. But the highlight of a recent MEMS conference was ski goggles with a heads-up display. If this is anything like driving while reading e-mail, expect more carnage on the slopes.