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Posts Tagged ‘Si2’

Two Tiers EDA Industry

Thursday, June 16th, 2016

Gabe Moretti, Senior Editor

Talking to Lucio Lanza you must be open to ideas that appear strange and wrong at first sight.  I had just that talk with him during DAC.  I enjoy talking to Lucio because I too have strange ideas, certainly not as powerful as him, but strange enough to keep my brain flexible.

So we were talking about the industry when suddenly Lucio said: “You know the EDA industry needs to divide itself in two: design and manufacturing are different things.”

The statement does not make much sense from an historical perspective, in fact it is contrary to how EDA does business today, but you must think about it from today and future point of view.  The industry was born and grew under the idea that a company would want to develop its own product totally in house, growing knowledge and experience not only of its own market, but also of semiconductor capabilities.  The EDA industry provides a service that replaces what companies would otherwise have to do internally when designing and developing an IC or a PCB.  The EDA industry provides all the required tools which would have otherwise been developed internally.  But with the IoT as the prime factor for growth, dealing with the vagaries of optimizing a design for a given process is something most companies are either unprepared to do, or too costly given the sale price of the finished product.  I think that a majority of IoT products will not be sensitive to a specific process’s characteristics.

The Obstacles

So why not change, as Lucio forecasts.  The problem is design methodology.  Unfortunately, given the design flow supported today, a team is supposed to take the design through synthesis before they can analyze the design for physical characteristics.  This approach is based on the assumption that the design team is actively engaged in the layout phase of the die.  But product developers should not, in general, be concerned with how the die is laid out.  A designer should have the tool to predict leakage, power consumption, noise, and thermal at the system level.  The tools need to be accurate, but not precise.  It should be possible to predict the physical behavior of the design given the characteristics of the final product and of the chosen process.  Few companies producing a product that is leading edge and will sell in large volume will need to be fully involved in the post synthesis work, but the number of these companies continues to shrink in direct proportion to the cost of using the process.

EDA startups should not look at post synthesis markets.  They should target system level design and verification.  The EDA industry must start thinking in terms of the products its customers are developing, not the silicon used to implement them.  A profound change in both the technological and business approach to our market is needed, if we want to grow.  But change is difficult and new problems require not just new tools, but new thinking.  Change is hard and almost always uncomfortable.

Software development and debug must be supported by a true hardware/software co-design and co-development system.  At present there are co-verification tools, but true co-development is still not possible, at least not within the EDA industry.

As I have said many times before “chips don’t float” thus tier one of the new EDA must also provide packaging tools, printed circuit board (PCB) design tools, and mechanical design tools to create the product.  In other words we must develop true system level design and not be so myopic to believe that our goal is Electronic System Level support.  The electronic part is a partial solution that does not yield a product, just a piece of a product.

The Pioneers

I know of a company that has already taken a business approach that is similar to what Lucio is thinking about.  The company had always exhibited at DAC, but since its new business approach it was not there this year.  Most customers of eSilicon do not go to DAC, they go to shows and conferences that deal with their end products’ markets.  The business approach of the company, as described to me by Mike Gianfagna, VP of Marketing at eSilicon, is to partner with a customer to implement a product, not a design.  eSilicon provides the EDA knowhow and the relationship with the chosen foundry, while the customer provides the knowledge of the end market.  When the product is ready both companies share in the revenue following a prior agreed to formula.  This apparently small change in the business model takes EDA out of the service business and into the full electronic industry opportunity.  It also relives companies from the burden of understanding and working the transformation of a design into silicon.

Figure 2: Idealized eSilicon Flow (Courtesy of eSilicon)

What eSilicon offers is not what Lucio has in mind, but it comes very close in most aspects, especially in its business approach to the development of a product, not just a die.

Existing Structure

Not surprisingly there are consortia that already provide structure to help the development of a two tiers EDA industry.   The newly renamed ESDA can help define and form the new industry while its marketing agreement with SEMICO can foster a closer discourse with the IP industry.  Accellera Systems Initiative, or simply Accellera, already specializes in design and verification issues, and also focuses on IP standards, thus fitting one of the two tiers perfectly.  The SI2 consortium, on the other hand, focuses mostly on post synthesis and fabrication issues, providing support for the second tier.  Accellera, therefore, provides standards and methodology for the first tier, SI2 for the second tier, while ESDA straddles both.

The Future

In the past using the latest process was a demonstration that a company was not only a leader in its market, but an electronics technology leader.  This is no longer the case.  A company can develop and sell a leading product using   a 90 or 65nm process for example and still be considered a leader in its own market.  Most IoT products will be price sensitive, so minimizing both development and production costs will be imperative.

Having a partner that will provide the know-how to transform the description of the electronic circuit into a layout ready to manufacture will diminish development costs since the company no longer has to employ designers that are solely dedicated to post synthesis analysis, layout and TCAD.

EDA companies that target these markets will see their market size shrink significantly but the customers’ knowledge of the requirements and technological characteristics of the tools will significantly improve.

The most significant impact will be that the EDA available revenue volume will increase since EDA companies will be able to get revenue from every unit sold of a specific product.

System Level Power Budgeting

Wednesday, March 12th, 2014

Gabe Moretti, Contributing Editor

I would like to start by thanking Vic Kulkarni, VP and GM at Apache Design a wholly owned subsidiary of ANSYS, Bernard Murphy, Chief Technology Officer at Atrenta,and Steve Brown, Product Marketing Director at Cadence for contributing to this article.

Steve began by nothing that defining a system level power budget for a SoC starts from chip package selection and the power supply or battery life parameters. This sets the power/heat constraint for the design, and is selected while balancing functionality of the device, performance of the design, and area of the logic and on-chip memories.

Unfortunately, as Vic points out semiconductor design engineers must meet power specification thresholds, or power budgets, that are dictated by the electronic system vendors to whom they sell their products.   Bernard wrote that accurate pre-implementation IP power estimation is almost always required. Since almost all design today is IP-based, accurate estimation for IPs is half the battle. Today you can get power estimates for RTL with accuracy within 15% of silicon as long as you are modeling representative loads.

With the insatiable demand for handling multiple scenarios (i.e. large FSDB files) like GPS, searches, music, extreme gaming, streaming video, download data rates and more using mobile devices, dynamic power consumed by SOCs continues to rise in spite of strides made in reducing the static power consumption in advanced technology nodes. As shown in Figure 1, the end user demand for higher performance mobile devices that have longer battery life or higher thermal limit is expanding the “power gap” between power budgets and estimated power consumption levels.

Typical “chip power budget” for a mobile application could be as follows (Ref: Mobile companies): Active power budget = 700mW @100Mbps for download with MIMO, 100mW @IDLE-mode; Leakage power <5mW with all power-domain off etc.

Accurate power analysis and optimization tools must be employed during all the design phases from system level, RTL-to-gate level sign-off to model and analyze power consumption levels and provide methodologies to meet power budgets.

Skyrocketing performance vs. limited battery & thermal limit (ref. Samsung- Apache Tech Forum)

The challenge is to find ways to abstract with reasonable accuracy for different types of IP and different loads. Reasonable methods to parameterize power have been found for single and multiple processor systems, but not for more general heterogeneous systems. Absent better models, most methods used today are based on quite simple lookup tables, representing average consumption. Si2 is doing work in defining standards in this area.

Vic is convinced that careful power budgeting at a high level also enables design of the power delivery network in the downstream design flow. Power delivery with reliable and consistent power to all components of ICs and electronic systems while meeting power budgets is known as power delivery integrity.  Power delivery integrity is analogous to the way in which an electric power grid operator ensures that electricity is delivered to end users reliably, consistently and in adequate amounts while minimizing loss in the transmission network.  ICs and electronic systems designed with inadequate power delivery integrity may experience large fluctuations in supply voltage and operating power that can cause system failure. For example, these fluctuations particularly impact ICs used in mobile handsets and high performance computers, which are more sensitive to variations in supply voltage and power.  Ensuring power delivery integrity requires accurate modeling of multiple individual components, which are designed by different engineering teams, as well as comprehensive analysis of the interactions between these components.

Methods To Model System Behavior With Power

At present engineers have a few approaches at their disposal.  Vic points out that the designer must translate the power requirements into block-level power budgeting to come up with specific metrics.

Dynamic power estimation per operating power mode, leakage power and sleep power estimation at RTL, power distribution at a glance, identification of high-power consuming areas, power domains, frequency-scaling feasibility for each IP, retention flop design trade-off, power-delivery network planning, required current consumption per voltage source and so on.

Bernard thinks that Spreadsheet Modeling is probably the most common approach. The spreadsheet captures typical application use-cases, broken down into IP activities, determined from application simulations/emulations. It also represents, for each IP in the system, a power lookup table or set of curves. Power estimation simply sums across IP values in a selected use-case. An advantage is no limitation in complexity – you can model a full smart phone including battery, RF and so on. Disadvantages are the need to understand an accurate set of use-cases ahead of deployment, and the abstraction problem mentioned above.  But Steve points out that these spreadsheets are difficult to create and maintain, and fall short for identifying outlier conditions that are critical for the end users experience.

Steve also points out that some companies are adapting virtual platforms to measure dynamic power, and improve hardware / software partitioning decisions. The main barrier to this solution remains creation of the virtual platform models, and then also adding the notion of power to the models. Reuse of IP enables reuse of existing models, but they still require effort to maintain and adapt power calculations for new process nodes.

Bernard has experienced engineers that run the full RTL against realistic software loads, dump activity for all (or a large number) of nodes and compute power based on the dump. An advantage is that they can skip the modeling step and still get an estimate as good as for RTL modeling. Disadvantages include needing the full design (making it less useful for planning) and significant slowdown in emulation when dumping all nodes, making it less feasible to run extensive application experiments.  Steve concurs.  Dynamic power analysis is a particularly useful technique, available in emulation and simulation. The emulator provides MHz performance enabling analysis of many cycles, often times with test driver software to focus on the most interesting use cases.

Bernard is of the opinion that while C/C++/SystemC Modeling seems an obvious target, it also suffers from the abstraction problem. Steve thinks that a likely architecture in this scenario has the virtual platform containing the processing subsystem and memory subsystem and executes as 100s of MHz, and the emulator contains the rest of the SoC and a replication of the memory subsystem and executes at higher speeds and provides cycle accurate power analysis and functional debugging.

Again,  Bernard wants to underscore, progress has been made for specialized designs, such as single and multiple processors, but these approaches have little relevance for more common heterogeneous systems. Perhaps Si2 work in this area will help.


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