By Ed Sperling
System-Level Design sat down with Ivo Bolsens, CTO of Xilinx; Charlie Janac, CEO of Arteris; Ravi Varadarajan, an Atrenta fellow; Sumit Dasgupta, senior vice president of engineering at Si2; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that discussion.
SLD: As we start re-using IP sometimes it won’t work in a stacked configuration the same way it does in a 2D structure. How big a problem is that?
Janac: With the interposer that shouldn’t be a problem. You’re only talking about logic-to-logic and memory where there is a problem.
Dasgupta: It depends on whether it’s hard IP or soft IP. If it’s expressed in RTL then maybe it can be synthesized and laid out, in which case everything you’ve said for regular logic applies to this IP block, as well. You’ve got to think 3D.
Reiter: Even with 2.5D Xilinx didn’t just take an FPGA and mount it in flip-chip fashion. With 2.5D you want to redesign your SoC to be more cost effective because 20% to 30% of the die is in the periphery in the I/Os. The power dissipation is in the I/Os. Those are all cost elements.
Varadarajan: In 2.5D, are there special buffer drivers?
Bolsens: Yes, there are special buffers. But there are other things you don’t need. You don’t need ESD surge, for example, which you would need in other buffers and I/Os. That causes power consumption and adds to cost.
Varadarajan: Is there any advantage to a buffer layer where you put large IPs onto it?
Bolsens: When you say 2.5D you make the decision that you don’t put the active layer into the interposer. Our interposer is just meant for interconnect. It has four layers of metal. Otherwise the interposer gets more expensive. That’s a tradeoff you make.
SLD: What’s the starting point in standards? Is it getting enough functioning chips out the door to really understand the issues?
Reiter: Based on what I’m hearing from the equipment industry, we need to come soon to a design for testability convention for 2.5D and 3D. Not only for the final test, but also for spec-in-progress testing. The Imec proposal is to make the bottom die bigger and have probing pads so you can test if the die is good before you put another die on top of it. I’m looking at the need to teach chip designers how to design for 3D. We should start with design for test.
Dasgupta: IEEE is going down that path. But as for what we should be doing, we’re collecting information as we go along. I don’t think we will create standards and say this is it. It will be a spiral method of development where we take little bits of everything at a time, starting from design planning down through the physical space and the verification space and finally to manufacturing. It’s going to be multiple versions of these standards as we go along. Si2 is finally getting started on this after two years. I expect this project will go on for several years.
Reiter: And we should not panic about the complexity because 22nm and 16nm will not be a cakewalk, either. Large corporations can choose between the two, but smaller companies really have no chance of doing a 16nm design because if one transistor is wrong the whole thing is dead.
SLD: The promise of 2.5D is you can take a 16nm design and put another layer on top of it, right?
Bolsens: Sometimes companies have this intellectual property about a certain vertical market segment, which they understand better than anyone else, and they can mold it into a chip. The problem is that to do that you need so much infrastructure that has no connection to your key competencies. Building services in a chip is not an easy thing to do, but in some cases it may be a differentiator between you and your competition. If the infrastructure is there and you can bolt your specific piece of silicon that captures your IP and you can leverage all the infrastructure, that’s an interesting value proposition.
Janac: Does that mean the eSilicon model prevails?
Reiter: I have eSilicon in my road map for exactly this reason. eSilicon will help small companies deal with complexity and get products out. In a 2D SoC you have to live with the process the rest of the SoC is using. Here you can rewrite the die business.
SLD: Does the adoption of standards slow down this whole movement into 3D?
Dasgupta: That’s difficult to answer because there are no standards. There is development going on. The pace at which people are beginning to clamor for standards is the right pace. Two or three years ago no one was asking for them. Today, all the leading players are asking about standards. That’s music to our ears. We know there’s demand out there. I don’t think standards are prohibiting progress, but if there were standards we would have faster progress, proliferation and adoption.
Reiter: I would hope some large players would bring out 2.5D and 3D chips in volume, which would really shock the industry into catching up. Then this big crowd of industry players left behind will put enough pressure on the industry to create standards so they can catch up. This lock-step game should not take too long, but two years is too short.
Dasgupta: No matter what standard you’re talking about, each one has its own heartbeat. You cannot be too early or too late. Herb’s point is well taken. At the beginning of every technology there are certain leaders who think that everything they do is IP and they will not talk about it with anyone. After a couple competitors come along and show they’ve been doing similar things, suddenly things open up. In 3D and 2.5D we are reaching that point.
Reiter: I can endorse this because I’m talking to some of the very big guys. These big corporations will not be able to cost-effectively manufacture everything that goes into a 3D configuration. They will want to buy pieces from the outside, and they may want to buy entire companies. A UPF corporation today only gets half the value from a CPF player if they’re folding it into the organization. The big guys are already thinking that standards will be good for them.
SLD: As we go forward, companies won’t have to do all the unique analog processes. They may take a processor, which may be a commodity, and put another piece of analog on it, which may be a commodity, as well. So aren’t we really commoditizing a lot of the pieces.
Reiter: Yes, and our industry may split into providers and consolidators—corporations that take a lot of these pieces and put them together. That’s a big business model change. It won’t happen overnight, but it is one of the possible outcomes.
Bolsens: One of the challenges is understanding business models better. I personally think one of the things that will drive standards will be business rather than technology. That will make the standards move faster than we have seen in the past. We also need standards to understand who’s going to do what and who’s responsible for what. The reason that package-on-package is picking up steam is that it’s really clear who owns that technology and where it fits into the whole chain. With 3D is it the packaging house, the foundry? Clarification of that will drive standards.
Dasgupta: TSMC had a presentation where they kept asking, ‘What is the business model?’ Every one of us needs to make money, of course. They were talking about the relationship between the OSATs and the foundries. This is very well understood in the 2D space, but in the 2.5D space and 3D space it gets fuzzy depending on whether it’s via first, via middle or via last. Today the foundries keep 80% of the profit. Once the OSATs get more sophisticated that will change. The business model, the financial model and the legal model have to change. Now you’re stacking die from different sources. If it fails, who’s responsible? Will there be a repair policy? Who’s going to repair it?
Reiter: This is a huge technical challenge and a huge capital investment.
Bolsens: That’s another reason we need standards. The OSATs are playing with very thin margins. But if we see them playing a critical role in this it will require an investment in technology. If they don’t see a return, that’s a problem for this technology. We need to understand that.
SLD: What happens to NoC technology here? Does that become standardized?
Janac: The NoC is a highly configurable IP, and in many ways it’s situational IP. Many companies will take it and use it in different ways. The actual silicon part, though, may become fixed.
Bolsens: One of the thing the NoC does is it allows you to make an abstraction of the physical interconnection. It will make it easier to adopt 3D technology. It could make it more transparent, whether it’s 3D or 2D.
Janac: With the logic tools we see this today whether it’s one die or two die, the network is the same in a logical sense. It also allows you to do a better job of isolation and partitioning.
Dasgupta: It’s divide and conquer.
Reiter: And where I see a NoC hopefully as very useful is in logic redundancy. Memory redundancy is easy, but logic redundancy is very difficult. You can turn off units and get better yield and control your costs.