By Ed Sperling
Cadence’s Richard Goering examines the high stakes at new process nodes, where investment throughout the supply chain is exploding. Forget about bonuses for the foreseeable future. Goering also follows the Si2 Conference’s focus on low-power standards, most notably interoperability between competing power formats.

Synopsys’ Navraj Nandra looks at 28nm chips in volume production and what still needs to be done—scaling analog/mixed signal and meeting higher voltage compliance requirements. It doesn’t get any easier from here, either.

Mentor’s Colin Walls pays homage to another luminary who just passed away—Dennis Ritchie, the creator of the C programming language. His legacy is pervasive.

Speaking of C, a language dispute has erupted in John Cooley’s DeepChip, this one over C/C++ and SystemC. There are no clear answers, but there is a lot of history to wade through.

Synopsys’ Allen Watson looks back on the PC era and what’s replacing it. You probably have one example in your pocket—or in your wall charger. There are some videos to go along with this, as well, which you probably can access from your mobile device if you can actually see the screen.

Si2’s Steve Schulz looks at the enormous value of GlobalFoundries’ contribution of DRC+ data structures to Si2. Think of it as an open standard that will be integrated into another open standard—OpenDFM. s/

Cadence’s Jason Andrews unleashes part four of his epic about how to use a UART in virtual platforms—this one focused on capturing logging information about a running system.

Mentor’s Robin Bornoff examines the concept of “rubbish in, rubbish out,” as it applies to thermal IC package models and concludes that all thermal models are wrong–maybe.

Synopsys’ Tom De Schutter, writing in TLM Central, compares scale-car models with transaction-level models. The parallels are interesting, even though you can’t drive either of them.

And in case you missed the most recent issue of the System-Level Design newsletter, here are some standout blogs worth reading:

–Mentor’s Jon McDonald has some revelations about ESL while driving in Italy.

–Cadence’s Frank Schirrmeister puts Kurzwell’s Singularity to the mobile test.

–Synopsys’ Achim Nohl looks at early software development and the supply chain.

–Sonics’ Steve Hamilton questions why there isn’t more interest in eDRAM—and why it’s misunderstood.

–And Arteris’ Kurt Shuler give an interesting retrospective on Steve Jobs.

By Ed Sperling
Mentor’s Mike Jensen examines system simulations and how to troubleshoot them. If this sounds painful, here’s a glimpse of real pain. Check out the segment beginning at 11:14 of this movie.

Cadence’s Tom Anderson jumps into the fray about the future health of SystemVerilog and whether its learning curve is reason to jump ship. There don’t seem to be many other ships around, though.

Synopsys’ Eric Huang looks at Thunderbolt and USB 3.0 and concludes they’re complementary. The jury is still out on this one. We’re not even sure where the courtroom is.

Si2’s Steve Schulz gives a preview of Si2Con, which will be the 16th conference focusing on industry progress in areas like CPF and UPF. Don’t blame Si2 for that one.

Mentor’s Colin Walls looks at C libraries and ponders the benefits of smaller libraries. Think about repositories vs. useful information and you’ll understand.

Cadence’s Richard Goering examines the challenges in test, which is a hot topic these days—particularly at advanced nodes and in the upcoming stacked die. The Big Three EDA vendors are all investing heavily in this area.

Synopsys’ Hannah Watanabe contends that Facebook helps engineers. It might, providing they have enough time and energy to fiddle with this stuff—and maybe a lack of concern about what they or others write on the walls.

By Ed Sperling
Cadence’s Richard Goering takes a look at a trio of top 10 lists for flash memory trends. This is an interesting way of really getting to the meat of a subject quickly. Bring your knife and fork.

Mentor’s Robin Bornoff is using thermal simulation for an optimal household underfloor heating system. Try explaining that to your contractor.

Synopsys’ Mick Posner and Doug Amos examine the new DVB-T2 mobile broadcasting standard in Britain, which was tested within days of approval using an FPGA prototype. Given the political ramifications of mobile messaging—witness what’s going on in North Africa—just wait until this gets going.

Si2’s Steve Schulz asks an interesting question: Do we need analog design intent standards? Given time-to-market pressures, this is certainly worth discussing.

Deepchip’s John Cooley casts a spotlight on the departure of former Cadence CMO John Bruggeman. He’s not alone in following this move, but has there ever been this much attention paid to the departure of a CMO before?

Cadence’s Joe Hupcey took a road trip to find out what real people are working on. The good news is that assertion-based verification is going mainstream.

Mentor’s Colin Walls tries to explain to people what he actually does. (He’s an embedded software engineer.) But what’s even more important is being able to explain it concisely inside your company. If you can’t do that, expect an e-mail from the HR department.

Synopsys’ Eric Huang is boasting about the speed of a HAPS platform using USB 3.0 PHY. I/O speed is quite important. So is the energy it takes to push electrons back and forth at high speed.

Cadence’s Jack Erickson disputes an EDN article, saying that SystemC is essential for raising the level of abstraction. This should be an interesting discussion.

Semicon’s Tony Massimini attends ComicCon—the comic book convention—which now is heavily electronic. The shocker is the lack of 3D—the viewable kind, that is.

How do you measure F max for MOS transistors? Answer: Adjust your testbench. Cadence’s Arthur Schaldenbrand has some tips for making this happen.

And in case you missed the most recent Low-Power Engineering newsletter, here are some standout blogs:

–Synopsys’ Cary Chin examines the next bottlenecks and why it’s important to solve them quickly.

–Mentor Graphics’ Barry Pangrle digs into interconnects, which are responsible for a third of total chip power.

–Cadence’s Luke Lang discusses why a top-down approach for coding power intent is the winner.

– Apache’s Norman Chang finds new challenges in stacking die.

–And Tensilica’s Chris Rowen gives a preview of what to look for at the Hot Chips conference, which kicks off today.

By Ed Sperling
System-Level Design sat down with Ivo Bolsens, CTO of Xilinx; Charlie Janac, CEO of Arteris; Ravi Varadarajan, an Atrenta fellow; Sumit Dasgupta, senior vice president of engineering at Si2; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that discussion.

SLD: As we start re-using IP sometimes it won’t work in a stacked configuration the same way it does in a 2D structure. How big a problem is that?
Janac: With the interposer that shouldn’t be a problem. You’re only talking about logic-to-logic and memory where there is a problem.
Dasgupta: It depends on whether it’s hard IP or soft IP. If it’s expressed in RTL then maybe it can be synthesized and laid out, in which case everything you’ve said for regular logic applies to this IP block, as well. You’ve got to think 3D.
Reiter: Even with 2.5D Xilinx didn’t just take an FPGA and mount it in flip-chip fashion. With 2.5D you want to redesign your SoC to be more cost effective because 20% to 30% of the die is in the periphery in the I/Os. The power dissipation is in the I/Os. Those are all cost elements.
Varadarajan: In 2.5D, are there special buffer drivers?
Bolsens: Yes, there are special buffers. But there are other things you don’t need. You don’t need ESD surge, for example, which you would need in other buffers and I/Os. That causes power consumption and adds to cost.
Varadarajan: Is there any advantage to a buffer layer where you put large IPs onto it?
Bolsens: When you say 2.5D you make the decision that you don’t put the active layer into the interposer. Our interposer is just meant for interconnect. It has four layers of metal. Otherwise the interposer gets more expensive. That’s a tradeoff you make.

SLD: What’s the starting point in standards? Is it getting enough functioning chips out the door to really understand the issues?
Reiter: Based on what I’m hearing from the equipment industry, we need to come soon to a design for testability convention for 2.5D and 3D. Not only for the final test, but also for spec-in-progress testing. The Imec proposal is to make the bottom die bigger and have probing pads so you can test if the die is good before you put another die on top of it. I’m looking at the need to teach chip designers how to design for 3D. We should start with design for test.
Dasgupta: IEEE is going down that path. But as for what we should be doing, we’re collecting information as we go along. I don’t think we will create standards and say this is it. It will be a spiral method of development where we take little bits of everything at a time, starting from design planning down through the physical space and the verification space and finally to manufacturing. It’s going to be multiple versions of these standards as we go along. Si2 is finally getting started on this after two years. I expect this project will go on for several years.
Reiter: And we should not panic about the complexity because 22nm and 16nm will not be a cakewalk, either. Large corporations can choose between the two, but smaller companies really have no chance of doing a 16nm design because if one transistor is wrong the whole thing is dead.

SLD: The promise of 2.5D is you can take a 16nm design and put another layer on top of it, right?
Bolsens: Sometimes companies have this intellectual property about a certain vertical market segment, which they understand better than anyone else, and they can mold it into a chip. The problem is that to do that you need so much infrastructure that has no connection to your key competencies. Building services in a chip is not an easy thing to do, but in some cases it may be a differentiator between you and your competition. If the infrastructure is there and you can bolt your specific piece of silicon that captures your IP and you can leverage all the infrastructure, that’s an interesting value proposition.
Janac: Does that mean the eSilicon model prevails?
Reiter: I have eSilicon in my road map for exactly this reason. eSilicon will help small companies deal with complexity and get products out. In a 2D SoC you have to live with the process the rest of the SoC is using. Here you can rewrite the die business.

SLD: Does the adoption of standards slow down this whole movement into 3D?
Dasgupta: That’s difficult to answer because there are no standards. There is development going on. The pace at which people are beginning to clamor for standards is the right pace. Two or three years ago no one was asking for them. Today, all the leading players are asking about standards. That’s music to our ears. We know there’s demand out there. I don’t think standards are prohibiting progress, but if there were standards we would have faster progress, proliferation and adoption.
Reiter: I would hope some large players would bring out 2.5D and 3D chips in volume, which would really shock the industry into catching up. Then this big crowd of industry players left behind will put enough pressure on the industry to create standards so they can catch up. This lock-step game should not take too long, but two years is too short.
Dasgupta: No matter what standard you’re talking about, each one has its own heartbeat. You cannot be too early or too late. Herb’s point is well taken. At the beginning of every technology there are certain leaders who think that everything they do is IP and they will not talk about it with anyone. After a couple competitors come along and show they’ve been doing similar things, suddenly things open up. In 3D and 2.5D we are reaching that point.
Reiter: I can endorse this because I’m talking to some of the very big guys. These big corporations will not be able to cost-effectively manufacture everything that goes into a 3D configuration. They will want to buy pieces from the outside, and they may want to buy entire companies. A UPF corporation today only gets half the value from a CPF player if they’re folding it into the organization. The big guys are already thinking that standards will be good for them.

SLD: As we go forward, companies won’t have to do all the unique analog processes. They may take a processor, which may be a commodity, and put another piece of analog on it, which may be a commodity, as well. So aren’t we really commoditizing a lot of the pieces.
Reiter: Yes, and our industry may split into providers and consolidators—corporations that take a lot of these pieces and put them together. That’s a big business model change. It won’t happen overnight, but it is one of the possible outcomes.
Bolsens: One of the challenges is understanding business models better. I personally think one of the things that will drive standards will be business rather than technology. That will make the standards move faster than we have seen in the past. We also need standards to understand who’s going to do what and who’s responsible for what. The reason that package-on-package is picking up steam is that it’s really clear who owns that technology and where it fits into the whole chain. With 3D is it the packaging house, the foundry? Clarification of that will drive standards.
Dasgupta: TSMC had a presentation where they kept asking, ‘What is the business model?’ Every one of us needs to make money, of course. They were talking about the relationship between the OSATs and the foundries. This is very well understood in the 2D space, but in the 2.5D space and 3D space it gets fuzzy depending on whether it’s via first, via middle or via last. Today the foundries keep 80% of the profit. Once the OSATs get more sophisticated that will change. The business model, the financial model and the legal model have to change. Now you’re stacking die from different sources. If it fails, who’s responsible? Will there be a repair policy? Who’s going to repair it?
Reiter: This is a huge technical challenge and a huge capital investment.
Bolsens: That’s another reason we need standards. The OSATs are playing with very thin margins. But if we see them playing a critical role in this it will require an investment in technology. If they don’t see a return, that’s a problem for this technology. We need to understand that.

SLD: What happens to NoC technology here? Does that become standardized?
Janac: The NoC is a highly configurable IP, and in many ways it’s situational IP. Many companies will take it and use it in different ways. The actual silicon part, though, may become fixed.
Bolsens: One of the thing the NoC does is it allows you to make an abstraction of the physical interconnection. It will make it easier to adopt 3D technology. It could make it more transparent, whether it’s 3D or 2D.
Janac: With the logic tools we see this today whether it’s one die or two die, the network is the same in a logical sense. It also allows you to do a better job of isolation and partitioning.
Dasgupta: It’s divide and conquer.
Reiter: And where I see a NoC hopefully as very useful is in logic redundancy. Memory redundancy is easy, but logic redundancy is very difficult. You can turn off units and get better yield and control your costs.

By Ed Sperling
System-Level Design sat down with Ivo Bolsens, CTO of Xilinx; Charlie Janac, CEO of Arteris; Ravi Varadarajan, an Atrenta fellow; Sumit Dasgupta, senior vice president of engineering at Si2; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that discussion.

SLD: Putting memory on top of logic doesn’t necessarily require 3D standards, does it? That can be a 2.5D configuration.
Reiter: That’s correct. It could be isolated by an interposer with logic on the other side because of temperature challenges.
Janac: This is the most practical application we see. The logic-to-logic will come later because of the complicated technology that’s involved.
Reiter: And network on chip will give a lot of headroom for expansion of this configuration.
Dagupta: I’ve been tracking this for about 5 years. I think we will see 2.5D next year.
Janac: The other thing that’s driving it besides memory bandwidth is that people are running out of I/Os. They’re multiplexing I/Os just to get multiple peripheral standards out through the I/O. That’s crazy. Somehow additional I/O availability has to be freed up. The only way to do that is to go through silicon.
Bolsens: That’s one of the main reasons we initiated our 2.5D product. If you look at the I/O bandwidth efficiency, we are getting about 100 times better gigabits per watt capabilities. People are trying to improve the bandwidth with gigabit transceivers. But there’s also a cost of power and latency. That’s one of the things this technology is solving. I/O hasn’t kept up with the capabilities of transistors on a die.
Varadarajan: We have customers doing logic-on-logic/memory. They’ve gone to memory on logic, and there is available real estate on the memory die. So they look at which IP subsystem can be moved to the memory die. They are starting to explore that in a test chip scenario, but not in full production.

SLD: Will something speed this up?
Varadarajan: We have been inventing standards on the fly. Do you need two RDL (redistribution) layers or three RDL layers? You want to invent standards because if you have a choice between increasing the pitch between two RDL layers or three layers, which one will allow you to do the routing without condition and meet timing. When companies begin to work in these areas, it pays to have more standardization.

SLD: When we get into real 3D stacking, we will need a whole new set of standards, right? We’ll even need some standards around layout.
Dasgupta: We also need standards for how to model a TSV. That includes everything from a simple resistor to distributed transmission lines with parasitic transistors.
Bolsens: If you just look at a 20nm transistor next to a TSV, it’s a like a skyscraper next to a small shack. If you can imagine what the impact will have on a 20nm transistor—it’s something you can’t ignore. The modeling of a through-silicon via is going to be an important aspect.
Reiter: Even before we begin to measure certain standards we have to address the thermal mechanical effects. Today, in 2D SoCs, there is no worry about the chip’s expansion. There are some underfill and epoxy challenges, but these are overcome by the packaging guys. Now the chip architect has to be aware that if he puts two chips together that expand differently, or if you have a CPU with a 100-amp current and a sensitive analog chip on top of it, you have magnetic interference. There will be a lot of basic education necessary even before we can give standards a chance.

SLD: What happens to yield when we get into a stacked die?
Bolsens: That’s a logical extension of complexity. The challenge we will have is that if you think of future 3D systems where you’re going to partition the system into different planes, how do you test all the different parts? Today, every die works independently. In the future, you’re going to have to think about building a system on chip in three dimensions where you have incomplete systems on incomplete systems. How you test that will definitely be a challenge.
Dasgupta: I spent most of my career at IBM managing physical design tools. One of the things we told the router guys was to avoid vias. It was a discontinuity. It was not an RC or part of a transmission line. It causes reflections and interference, and its reliability is lower compared with a wire. And now suddenly we are enamored with this thing that is going to punch through layers of silicon. Somewhere we need to solve this madness. We need to make sure the quality of the TSV is equal to or better than a normal via. Otherwise we are going to have a lot of bad stacks.
Janac: Wide I/O is 1024. That’s the standard. And very deep.
Dasgupta: Yes, it’s the deep part that scares me.
Bolsens: This is still not millions. We need to see things in perspective. We are adopting this technology in a very careful way. There are a lot of challenges ahead, but that’s almost like boiling the frog. You do it very slowly.
Reiter: In my book, 3D is not an IC design technology. It’s a system technology. Something we really need to think about as quickly as possible is redundancy and self-repair. Otherwise we may never get something to the designer that inspires confidence. If you have a million vias, you better think about redundancy. With 0.01% failing, that’s a dozen or more.

SLD: But won’t you be using fewer vias with TSVs? And in addition, won’t that change design because most of these will be in the center of the chip, not at the periphery?
Janac: It certainly doesn’t help floor-planning.
Reiter: And IP re-use is not taking the 2D IP we now have and putting it into a 3D system. We have to reconceive a lot of our IP to make it suitable for 3D. Cost is everything, too, so we have to think about 3D from the beginning.
Dasgupta: There was statement made by an engineer from one company where they put logic on one layer, memory on another and I/O on the third layer. His conclusion was that to get significantly better performance you have to partition and floor plan in 3D. You can’t think 2D and expect it to work in 3D.

SLD: Then do we really know what standards have to be set?
Dasgupta: We are just scratching the surface on that.
Reiter: We have to understand and set a priority. Two years will not be enough.
Dasgupta: We got approved on a standards project two years ago and we haven’t done anything. Our board of directors asked what we’ve done so far and we said nothing. Their response was, ‘Good, because we’re not ready.’
Bolsens: That’s also where you see the importance of consortia like Imec and Sematech. Several industry leaders are working together to do the pathfinding approach and understand all the challenges and what we need to do there.
Reiter: There is also ITRI in Japan and Leti in France. Georgia Tech is also doing a lot of work in this area. 3D relies heavily on packaging. While the outside pin count may be reduced, it clearly needs more sophistication inside in regards to getting parastics under control.

SLD: How close are we on 2.5D?
Bolsens: It better work. There are some simplifications in 2.5D. You don’t have an active-on-active structure. You have an active-on-passive layer. You also have considerable thermal challenges with active on active, so the risks are lower with 2.5D. That’s where we have our first 28nm product. That’s where you’ll see some of the memory guys show up with solutions. But what we have done at Xilinx is build a captive product. All the silicon comes from inside, so life is a lot easier. It’s when you start combining chips from different vendors, aggregating them, and figuring out who’s responsible for that and for test—that’s when you start running into problems in the industry that still have to be solved. For captive products it’s a lot easier.
Reiter: Intel also announced some 2.5D products. They had to get an Altera FPGA and an Atom processor to make the periphery configurable. And in regard to 3D production, a number of memory vendors have announced products with as many as eight die. Memory will be the first one to utilize 3D because you can design it and use it multiple times.
Janac: It’s a simpler problem.
Reiter: There have been other announcements, too, but none of it is in volume production. I assume that’s because of cost.
Dasgupta: Limiting it to memory limits the risk. It’s the same die, the same technology node, and the distribution of the TSVs is easier to control because it’s a more regular structure.

By Ed Sperling
System-Level Design sat down with Ivo Bolsens, CTO of Xilinx; Charlie Janac, CEO of Arteris; Ravi Varadarajan, an Atrenta fellow; Sumit Dasgupta, senior vice president of engineering at Si2; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that discussion.

SLD: How far has the industry progressed with standards for 3D stacking to help speed along this technology?
Reiter: Is this open or proprietary standards?

SLD: Both, because one often leads to the other.
Dasgupta: That’s a good point. If you have proprietary standards then its evolution is not nearly as rapid as an open standard with many voices talking about it and many minds contributing to it. It is good to start with something that has been tested inside as a proprietary standard, but if it is opened up that’s the ideal mix. If it doesn’t start from zero that’s good, but openness is necessary.
Bolsens: Standards, in the end, have to be open. One of the things you want to achieve is to create enough critical mass and momentum around certain technology to make sure that the efforts—especially in new and emerging fields—are well spent and that there is a return on investment. Everyone needs to benefit from them. We are in the very early phase of development of this technology and everyone wants to make sure their efforts pay off.
Reiter: Standards are a lot of effort—and I’m speaking from experience. I drove the PrimeTime signoff standard. This was a three-year effort for me, and at Synopsys we invested 50 man-years to make it an industry standard. Today 95% of designers are using it for timing signoff, but three years is a long time.
Janac: A lot of standards that are made in standards bodies haven’t seen the heat of battle in customer designs and they haven’t been tested in the real world. Sometimes they’re convoluted. It’s the difference between a horse and a camel. The camel is a horse designed by committee. If you have something that has been used in production it’s much more robust, much more useful, and much more practical than something created by a standards body that hasn’t had the discipline of trying to get a design through production.
Dasgupta: I agree. If you start from the ground up by committee—and VHDL is a good example—it is painful. Verilog, in contrast, was already proven before it was delivered into an open environment. That’s the right model. You need to start off with something that’s already been proven. And if you keep it closed, then you don’t get the intellectual contributions that come with an open standard. At the point you’ve proven it, that’s where you open it up to the industry to make it widely accessible, implementable and accessible.
Varadarajan: We’re building an early stage prototyping system for 3D design exploration. We are right in the midst of all of this. If you stack a die front side to back, what sort of parasitics are you going to look at with microbumps and TSVs. A lot of this information is not available. We are working with technology steering committees such as LETI and Imec and hopefully what comes out of this is useful for the mainstream. When you have a stack configuration, how do you specify that? Do we have an XML specification? We need to see that either as a standard, or at least a specification with multiple people contributing to that. I do believe that 3D is real. Next year you’re going to start seeing logic on logic and interposers. Having multiple people using that is critical so we don’t have a repeat of UPF and CPF. We don’t want multiple standards evolving at once.
Reiter: That’s a very important point. If you want to succeed with a standard you have to bring it out at the right time and make sure there is enough momentum behind it to make the industry line up behind it. UPF vs. CPF was a very expensive accident for our industry.

SLD: Power will become an important part of this, for sure.
Dasgupta: We just made a contribution to IEEE of a subset of the CPF standard specifically to align some of the semantics representing power constraints. The syntax is not as important as clarity and similarity of semantics. Si2 has been a member of the 1801 working group. The goal is to bring them together.

SLD: What standards do we need for 3D to work?
Bolsens: It covers the whole ecosystem. How do you handle between foundries, packaging and assembly houses. You need agreements on the technology files you hand off to foundries. The whole modeling of the interfaces. We have to find agreements on how the interfaces will look, how they will be models, how they will work with technology from different origins. It’s a pretty complex thing. It reaches from EDA to design houses, testing, even equipment for thin-wafer handling. It requires a lot of players.
Reiter: Unless the equipment is lined up the cost will be unaffordable.
Dasgupta: At the RTL conference two years ago, a major semiconductor company announced that it had solved all the technical roadblocks to announcing a product. So where is it. There still isn’t a product. The reason is that there is still not a financial incentive to going to 3D, so 2D remains more competitive. There are things that happen vertically and things that happen horizontally. How is information exchanged between floor planning other areas and then transferred back.
Reiter: We cannot invent a totally new environment. We have 100,000 IC designers out there and they have their own way of doing things. As we introduce new standards and new technology, we have to make sure we don’t disconnect them.

SLD: The list of what has to be done with standards in 3D sounds like it will involve thousands of man-years of work.
Bolsens: I wouldn’t be surprised at that. There are so many different organizations involved. For 3D stacking there will be Si2, Jedec, Sematech, SEMI. No one organization will solve the whole 3D problem. It’s a multidisciplinary challenge. Different parts of our ecosystem will have to take care of it.
Dasgupta: The biggest challenge we face is time. If you look at the 2D space, many of the standards we use today have evolved over 20 to 25 years. We’re looking for that level of standards in two years.
Reiter: I don’t think two years is realistic. It will take longer.
Dasgupta: I think it will, too.

SLD: Where is 3D at this point? How real is it?
Janac: There are 2.5D test chips.
Reiter: And 3D, as well. There are big companies working on 3D stacks because the form factor is so much better.
Janac: There is logic to logic/memory, and there is the 2.5D, which is logic/memory.
Bolsens: I think the big driver will be logic/memory. That’s going to really make this technology mainstream because everyone is struggling to meet the bandwidth requirements. Providing wide memories with lower power and latency will be the killer app.

By Ed Sperling
Synopsys’ Eric Huang pays a visit to the Microsoft Store and finds a really smart salesperson who seems to know just about everything there is to know about the products for sale. And yes, that is somewhat unexpected.

Cadence’s Jean-Michel Fernandez talks about creating SystemC peripheral models. Fernandez represents Cadence’s Team ESL, which is an interesting development in its own right.

Speaking of software, Mentor’s Colin Walls looks at which language is best for embedded purposes. The answer once again appears to be C. This looks like a pattern.

Si2’s Steve Schulz does some white-water rafting in the Grand Canyon and thinks about vertical stacking. Our vote would have gone to liquid cooling, especially given the travel pictures.

Synopsys’ Hezi Saar examines mobile Web browsing trends and finds traffic is up in the summer. He blames it on better weather. But is it reversed below the Equator?

Cadence’s Richard Goering interviews Open-Silicon CEO Naveed Sherwani about an exponential verification nightmare. Sounds like Freddy Krueger with an EE degree. Check out the video.

LSI India’s Ballori Bannerjee, writing in Synopsys’ VMM Central, digs deep into registers. When it comes to verification, this stuff is critical to know.

Semico’s Joanne Itow looks at Renesas’ remarkable recovery from the Japanese earthquake and tsunami, getting its fab up and running in record time with production output running even more efficiently. There are a few words in Japanese here that we had to look up and have no idea how to pronounce, but this is still a remarkable story.

Cadence’s Kari Summers is back with another five-minute tutorial, this one on where to find EDI videos. This is like a guided site search.

Finally, Synopsys’ Darcy Pierce counts the ways in which blogs help engineers—and all in easily digestible bites. This is like brain snacks.

By Ed Sperling
Synopsys’ Hezi Saar digs into the definition of a subsystem and how it changes depending on what you’re looking at. All signs point to the growing importance of subsystems—particularly with stacked die—so you might want to start reading whatever you can find on this subject.

Cadence’s Richard Goering interviews Si2’s Steve Schulz about standards for hardware-software integration and modeling and OpenLPM, the next bridge between CPF and IEEE 1801, aka UPF 2.0. And if that looks like a lot of acronyms, realize there should only be one power format and one acronym—and a pox on whoever forced us to memorize all these excess letters.

Just in case you wondered if Mentor’s Harry Foster had wrapped up his epic on functional verification, the answer is no. He’s back with part nine, and this one is packed with trends like functional verification techniques, formal property checking, FPGA prototyping, and simulation regression times. There’s a lot of great information in here, which unquestionably should be turned into a book.

Harry Gries pulls up a video clip about cat juggling and compares that to time management, project management and micromanagement. If you’re a cat lover, ignore the video.

Synopsys’ Karen Bartleson pulls together three really smart teens to talk about what’s cool and what’s not at DAC. Considering the real audience for most high-volume chips is this age bracket, you might want to listen. This was an interesting presentation on the show flow, and it’s captured here once more in audio.

Cadence’s Prabal Bhattacharya digs into model validation and assertion-based verification for mixed signal designs. Anything that can help AMS over the next couple feature shrinks is welcome.

Mentor’s Colin Walls believes USB 3.0 will win, if for no other reason than all PCs are equipped with USB ports. But it won’t meet the needs of high-def video because the existing mass storage transport protocol can’t take advantage of faster data rates. There’s always a bottleneck to solve and this one is being addressed, albeit very methodically and slowly.

Synopsys’ Doug Amos and Mick Posner strut out Will Shakespeare and Ben Franklin (who posthumously seems to have changed the spelling of his last name) to prove their point about the need to be prepared for FPGA-based prototyping. So far, however, it looks as if the industry is woefully unprepared—at least given the traffic on expert forums.

Cadence’s Kari Summers is back with a new five-minute tutorial about how to rotate a cell in a design with the right mouse button. This is how you make the most of that dead time standing in line at Starbucks.

By Ed Sperling
Synopsys’ Frank Schirrmeister follows a DAC panel on ESL and discovers that management is actually in favor of—perhaps even thrilled about—adopting ESL. That’s one excuse that doesn’t work anymore.

Mentor’s Tom Fitzpatrick digs into the register modeling package in UVM 2.1.2. Considering the industry is clamoring for more standards because it makes verification much easier, this is a good thing.

Cadence’s Richard Goering follows a panel discussion on 20nm, which looks at the trouble spots and how to address them. This may be the next node, but it also may take a lot longer than two years for even advanced companies to get there—and certainly for enough people to get there to make it economically worthwhile.

Synopsys’ David Hsu dropped some pithy observations about DAC. We assume most of these observations are about cloud and they’re quite positive. So someone, somewhere, will be happy. Quick, go tell the boss. We’re upgrading to first on the way back from DAC.

Si2’s Steve Schulz puts some perspective on the move to bridge IEEE 1801 and the Common Power Format. Chipmakers say competing standards have created havoc for their designs because they don’t use only one vendor’s tools or flows.

Mentor’s Robin Bornoff has uncovered a strategy most of us have long suspected would be applied to leaky semiconductors, namely using liquid nitrogen as a coolant. Don’t try this at home, of course. You’d probably destroy the house, and if they kids get a hold of it they’ll destroy everything in the neighborhood. Just as a point of reference, liquid nitrogen boils at -321 degrees Fahrenheit.

By Ed Sperling
Cadence’s Richard Goering follows Jim Hogan’s talk about the democratization of MEMS. This market is showing big gains lately, but to really release the emergency brake will require a different design approach.

Mentor’s Robin Bornoff revs up the engine and turns on the neon underbody lighting in this look at the overclocking market, shifting effortlessly from cars to PCs and from hot products to heat sinks. This should be an interesting series.

Synopsys’ Eric Huang looks at the rise of USB 3.0 in laptops and PCs, and uses his platform to advertise new jobs at Cadence. That’s a first.

Si2’s Steve Schulz looks at the standards efforts in place at DAC, as well as a party with a purpose—no, not the Denali party. That may be a standard, but we’ve yet to find a legitmate purpose.

Cadence’s Qingyu Lin digs into CPF low-power simulation with an AMS design. This is great inside information that you’d probably only find at a technical conference where there are no windows, bad acoustics and terrible coffee. Yes, we’ve all been there.

Mentor’s Colin Walls looks at delivering power over USB. That should cut down on the connections—as well as the energy requirements.

Synopsys’ Karen Bartleson and Yvette Huygen interview Holly Stump and Carol Hallett about challenges for women in technology. This is an important topic, and one where some progress is being made.

Cadence’s Jason Andrews looks under the covers at Ubuntu, the Debian-derived Linux, and traces his steps backward from an error message.

Semico’s Tony Massimini examines different kinds of bits—oil drill bits—and the sensors needed to relay accurate information.

Cadence’s Hermant Shah rolls out part two of his miniseries on miniaturization through embedding packaged components. But you still have to pick those pre-packaged components carefully.

Cadence’s Kari Summers is back with another five-minute tutorial, this one on fixing SI violations.