"Job's Law makes sense - its about the user experience and this is how Apple creates end user value and loyalty" - Jack Browne
Deep Insights for Chip Architects and Engineers
Five experts sound off to System-Level Design on the state of synthesis and what’s needed in the future: Shawn McCloud, product line director for Catapult C Synthesis at Mentor Graphics; Chris Eddington, director of marketing for system-lvel products at Synopsys; Brett Cline, VP of marketing at Forte Design Systems; Andy Biddle, director of business development at Magma and Sanjiv Kaul, executive chairman at Oasys.
By Cheryl Ajluni
At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs).
The concept of 3D stacking or integration technology is not new. In fact, 3D stacking of dies has been successfully demonstrated and is currently being commercially employed in some embedded domains (e.g., stacking DRAM memory on CPU cores). A recent 3D IC report from Yole Développement suggests that by 2012, the number of 3D IC-processed wafers could surpass 10 million units, driven in part by handset, wireless and computing applications. Given the intense interest and work going into developing 3D integration technology, this prediction seems just about right—assuming, of course, that a few challenges can first be met.
Very simply put, 3D integration consists of stacking integrated circuits and connecting them vertically so that they behave as a single device. A 3D chip is therefore just a stack of multiple device layers with direct vertical interconnects tunneling through them. So what’s the big deal about 3D integration?
Today’s semiconductor chips face extreme pressure to achieve increased performance, while reducing their size and accommodating lots of new functionality. When these factors coalesce in traditional 2D chips, longer interconnects result. In SoCs, longer interconnects translate into reduced speed and increased power consumption.
A key benefit of 3D integration is that it can reduce the length of interconnects. Additionally, it provides higher transistor density, faster interconnects and heterogeneous technology integration, with potentially lower power, cost and faster time-to-market. As Matt Nowak, director of engineering in the VLSI technology group of Qualcomm’s CDMA technology division, pointed out in a DAC 2008 presentation, the 3D approach “achieves extremely high densities, allowing us to use heterogeneous technologies and reduce form factor. The key is that it enables the use of new differentiating technologies to build new architectures that cannot be built in existing technologies.”
Up to this point, most efforts in 3D integration have focused on developing different fabrication techniques for stacking multiple device layers and forming the vertical interconnects. Much of the work has been done through collaborations with academia, industry organizations and government-sponsored laboratories around the world. One of the key technologies to come out of this research is a next-generation interconnect technology known as Through-Silicon Via (TSV). The TSV is a vertical electrical connection that passes completely through a silicon wafer or die to produce multilevel chips with an optimum combination of cost, functionality, performance, and power consumption. By using TSV technology, 3D ICs can pack greater functionality into a smaller footprint and realize shorter critical electrical paths, resulting in faster operation.
Some of the other developments to come out of ongoing 3D integration research were recently recognized at the Electronic Components and Technology Conference. Sandia National Laboratories presented details of its W TSV process, which is said to provide a suitably low-resistance metal with a coefficient of thermal expansion close to Si, a via fill that is conformal, and can be readily integrated into IC fabrication. IMEC introduced a novel process for die-to-wafer bonding (using Cu-Cu bonds) of its 3D SIC technology and a scalable TSV technology for 3D wafer-level packaging. Its TSV technology is designed for 3D structures where interconnects are fabricated after standard CMOS processing.
SEMATECH also is focusing its 3D research on TSV technology, particularly for implementation. The industry organization is actively working to bring together partners from across industry—chipmakers, equipment and materials suppliers, assembly and packaging service companies—to make 3D TSV suitable for high-volume manufacturing (Figure 1).
Figure 1. In contrast to the 2D-SoC or 3D System-in-Package, 3D TSVs offer a cost-effective way to achieve high density and performance, while also being able to integrate non-CMOS products with CMOS. The SEMATECH 3D project is based on cost modeling to assure products will be both manufacturable and affordable.
While ongoing research and development is absolutely critical to the success of 3D integration, perhaps one of the greatest challenges it faces is tool support in terms of design techniques and methodologies. Without it, engineers have virtually no efficient way to exploit the technology’s benefits. Tool support is especially critical when it comes to 3D integration because vertical stacking tends to increase thermal resistances, further exacerbating temperature-induced problems that can negatively affect system reliability, performance and leakage power. The use of 3D also will significantly complicate the typical design flow.
The key, of course, lies in creating a standardized design environment and methodology for physical design of 3D chips that could support a range of different tools. Having the tools integrated in one place would make it easier for designers to explore and make architectural decisions and then, to hand those decisions off to next stages in the design process.
3D IC integration is still in its infancy and, as a result, tools developed today for one specific application (e.g., stacked memory) may not be suitable for heterogeneous integration tomorrow. Nevertheless, there are some tools available now, with more in development. Some of these tools include:
Javelin Design Automation. 3D PathFinding provides a detailed 3D flow for accurate performance/power/cost estimates that can be used for rapid design exploration and optimization of 3D stacked ICs. Developed in collaboration with IMEC and Qualcomm, the solution extends Javelin’s existing PathFinding methodology and j360 Silicon PathFinder physical design prototype platform to support virtual chip design (Figure 2).
Figure 2. Javelin’s 3D PathFinding solution allows the designer to assess the impact of various 3D interconnect strategies throughout the IC design and fabrication process, in a matter of just a few hours or days. Silicon process engineers can use it to fine-tune their technology to the system architecture specifications.
These tools, developed through work conducted as part of research programs sponsored by the Defense Advanced Research Projects Agency (DARPA), enable 3D IC design and analysis (Figure 3). MAX-3D is a 3D mask layout tool whose technology file includes all properties of stacking process, wafer orientations, bond materials, via electrical/material properties, and also incorporates 2D foundry design kits. R3Integrator is used for die/interposer/package co-design with TSVs. R3CAD is a java-based, multi-platform tool for 3D design research and prototype study and R3Artist is an embedded 3D layout editor (Figure 3).
R3Logic is currently collaborating with STMicroelectronics and CEA-LETI to develop a full 3D design flow for 3D heterogeneous system and system-in-package design.
Figure 3. R3Artist features single and multiple wafer technologies, integrated material properties database and solid model extraction, including dielectric layers.
3DCACTI estimates the optimum access times and power dissipation of a cache using 3D IC technology for a given number of active device layers and by partitioning device layers for various technology nodes. Based on the estimation, it searches for the optimized configuration that provides the best delay, power and area efficiency trade-off according to the cost function for a given number of different 3D partitions.
3D Magic is a comprehensive layout methodology for 3D circuit-layout editing and extraction with MAGIC, an open source layout editor developed by UC Berkeley. PR3D is a placement and routing tool for standard cell design in 3D. Both tools were developed through MIT’s Interconnect Focus Center Research Program. MIT also developed SysRel (System-Level IC Reliability) for assessing the interconnect reliability of 3D ICs from a thermal-aware perspective at the circuit-layout level.
With the pressure on traditional 2D chips mounting, 3D integration has begun to establish itself as a viable means of breathing more life into Moore’s Law. It certainly touches on all the hot buttons in the industry today, namely low power, cost and time-to-market. The challenge will be in ensuring that these benefits are realized in a timely and efficient manner. 3D-specific design tools and methodologies are coming to meet this challenge head on. In the meantime, the tools available now and the groundwork for future tools and methodologies being laid by industry organizations, academia and commercial companies alike, will go along way in ensuring 3D integration plays a critical role in the future of the semiconductor industry.
By Clive “Max” Maxfield
System Level Design (SLD) is one of those terms that means different things to different people. For some, SLD is understood to refer to the process of capturing (and verifying) a complex ASIC/ASSP/SoC design at a high level of abstraction. Another term that we often hear in this regard is Electronic System Level (ESL) design.
Trust me, you don’t want to get me talking about ESL. A couple of years ago I wrote an opinion piece for a DAC newsletter entitled “What the hell is ESL?” You would be amazed at the number of folks who e-mailed me after reading that piece saying, “Thank goodness, I thought it was only me who was confused.” But we digress…
I absolutely agree that SoCs are going to get bigger and better (and scarier), and that companies like Cadence, Mentor, Magma, and Synopsys – along with all of the smaller EDA companies whose mission it is to create SoC design and verification tools – are going to continue to astound us with their latest and greatest offerings.
But I also have some problems with this. For example, very few products these days can justify the tens of millions of dollars it can cost to design and deploy a custom silicon chip. Another consideration is that when you create an SoC, your algorithms are effectively “frozen in silicon,” which can be extremely awkward when standards and protocols are continually evolving all around us.
One alternative is to use a Field Programmable Gate Array (FPGA) as the implementation platform for the design. Of course we all know that early FPGAs were logic limited, power-hungry, and generally not very interesting. But times have changed. Some FPGA families boast incredibly high capacity and high performance; others offer extremely low power; still others provide mixed-signal capabilities; and all offer configurable fabric that can be adapted to whatever tasks are required.
This doesn’t mean that FPGAs are suitable for every application, but they are currently appearing in all sorts of systems, from handheld, battery-powered units to supercomputers whose performance make your eyes water.
Another consideration is that future generations of electronic products will not be used as standalone devices. Instead, they will be intelligent elements in an interconnected ecosystem. As one rather obvious example, look at Apple’s iPod. When considered in isolation, this is only a vaguely interesting media-playing device. What has made the iPod so widely successful—especially when compared to its competition—is its associated media purchase and download ecosystems in the form of iTunes.
This type of “big picture” view increasingly will apply to products of all shapes and sizes. Consider a company that creates residential air conditioning units for example. Customers are certainly going to be interested to hear about new units that are more efficient, quieter and more powerful, but only to a point. What will really interest them is when their air conditioning system is augmented with connectivity features that allow them to monitor and interact with the system from anywhere in the world. Imagine, for example, returning from vacation, realizing that you have arrived in the middle of an unexpected heat wave, and calling your air conditioner from your car and instructing it to start cooling your home in preparation for your arrival.
Similarly, imagine a smart air conditioner that can communicate with its manufacturer and/or your service provider. If your air conditioner notices an unexpected vibration or a loss in performance, it could automatically log a request for a service before system failure occurs. (This would have been really useful at my house a couple of summers ago.)
What all this means is that “System Level Design” cannot simply focus on the development of a silicon chip in isolation. Instead, we have to work from the top down at a very high level of abstraction, starting by considering the user “experience,” the user interface, and the way in which this product is going to interact with the outside world. And only then should we actually start to think about the underlying implementation. Put another way, it’s important to decide just what it is we actually want to do, and then we can decide how to go about doing it.
The majority of today’s EDA environments are ferociously complicated, not the least that they require their users to learn special languages such as VHDL and Verilog. But a lot of folks who have really good ideas don’t know these languages and they don’t think like hardware design engineers. Wouldn’t it be better to make the tools more intelligent so that they can understand the languages favored by different users, such as C/C++, Java, Python, and so forth. I know there are some interesting C/C++ synthesis tools around, but a lot more could be done in this area.
As a somewhat related topic, it’s no longer sufficient to design the various parts of a product in isolation. That includes the FPGA, the circuit board on which it rides, the enclosure in which everything resides, and the firmware and software that run on the device. Instead, what is required is a unified environment in which everything can be developed and verified in the context of everything else.
Yes, the “big boys” in EDA have environments like this … but have you actually tried to use one? It’s hard enough to gain expertise in even a small portion of one of these environments. Running the entire thing with only a couple of people is well-nigh impossible. And then there’s the cost of all these tools.
The reason all of this is so important is that we are increasingly relegating product designs to fewer and fewer people that require incredible levels of training and expertise. This may work for the most complex SoC devices, but it is not a good way to go for the majority of products. What we need are solutions that will unleash the creative and innovative potential of a wide range of users. Instead of leaving things to technological experts, we need to empower new waves of users who can conceive world-changing ideas and products.
By Ed Sperling
Until several years ago, analog was a world apart from digital. Analog engineers could comfortably avoid many of the issues of Moore’s Law, viewing it as a costly bad habit with an equally bad outcome.
Most analog engineers gloated privately that they could still develop chips at 250nm, or at worst 130nm, while their digital counterparts were struggling to keep up with issues such as lithography, current leakage, new interconnects, different wafer sizes and new gate designs, just to name a handful. It also was before virtually all ASICs had morphed into systems on chip, which include both analog and digital.
Now the only question is whether those chips are mostly analog or mostly digital—which largely determines who’s in charge of the design team—but the design, simulation, layout and verification of these complex SoCs bring both worlds together into an unstable mixture.
On the tools side, companies are scrambling to bring these two worlds together into some sort of order. And while it may be particularly attractive to engineering managers, who are trying to get chip designs out the door in an ever-shortening time frame, it’s bringing yet another specialty into the design team—analog engineers, with a uniquely different way of looking at the world.
Graham Etchells, director of product marketing for Synopsys’ analog/mixed signal group, said there will never be full automation of the analog piece of the design, but there will at least be more automation. “Our goal is to put capabilities into the tools to make it easier to do things,” he said. “In the simulation and analysis environment, what we’ve done is allow a designer to set up simulations, run them, script all the measurements they want to do and view the results in a wave view analysis tool.”
Getting analog engineers to use the new tools is another matter, though.
“There’s a real dichotomy here,” Etchells said. “These guys are looking for ways to speed up what they do, but they don’t trust the automation and in some cases it doesn’t work. What we’ve been doing is putting capabilities into the tools that allows them to still control what’s going on, but it makes it easier for them to do things. In layout, for example, we added an autoconnect feature that allows you to snap your connection to pins or source drains or gates without having to zoom in and make sure the connection is exactly on the grid. We’ve also introduced an automatic bus command up to thousands of bits. Doing that by hand is a real pain.”
Virtually all of the major EDA vendors see a big need for continued analog tools development. Rajeev Madhavan, CEO of Magma Design Automation, said that mixed signal assembly is “cumbersome and error-prone.” In a keynote speech at ISQED, Mahdhavan said that everytime there is a handoff there are problems.
“The only way we’re handling this is with brute force,” he said. “As you get deeper into new geometries, the level of accuracy has to go to a new level of detail.”
He said that an unpredictable flow, which is common in mixed signal designs, can result in an 80% increase in engineering costs—and it gets worse. At 40nm and below, transistor currents can vary 30% to 50% and the difference between digital and mixed signal design re-spins is 1.2 versus 3 for mixed signal.
But while most tools vendors see big promise and opportunity in the analog space, selling it to the engineers who will use those tools is another matter entirely. SoCs have created convergence among some varied groups that are changing the focus of those groups. David Smart, a fellow at Analog Devices, said the real shift is who’s in charge of the design team. In the converter space, for example, some of the product lines are now predominantly digital and run by digital engineers, while others are still predominantly analog with digital engineers working under their leadership.
For Smart, the real pain points in analog are narrow areas, which are not enough for the classic EDA tools vendors to make significant investments. Also important and ripe for general improvements are areas such as simulation and place-and-route.
“Place and route inside of analog cells has not caught on well,” he said. “Layout is labor-intensive and it limits how many times you can change the design. Right now we try to get it pretty close to perfect on the first pass. If you come to the end and the interconnect line is too long and to fix it you have to shuffle all this stuff around, you can’t just push a button. From an intellectual standpoint, automating all of this is very appealing, but there’s nothing around. Still, it would be good to have tools so you’re not surprised with the results.”
Smart also said that the reason many EDA tools have not been accepted by engineers is that they usually don’t work as well as someone who is an expert at analog design. “We’ve seen a lot of attempts, but the tools are usually not superior to what an analog expert can do.” He noted that Analog Devices frequently teams seasoned experts with young engineers skilled in the newest tools and arrives at a better result than just relying on automated design.
It’s currently not possible, for example, to automate verification on multiple analog circuits because each circuit is different. Simulations sometimes take weeks, which is another area where improvements are needed. SPICE has progressed to Fast SPICE for big circuits, which was regarded by analog engineers as inaccurate, to Accurate Fast SPICE. But for most engineers, it’s still too slow.
Tools vendors are committed to making a dent in this space, however, in large part because analog is no longer a separate world. In the future, there likely will be applications engineers and business people, who will make quick decisions about build vs. buy, marketers (who traditionally have stood on the sidelines even though they have enormous influence over the feature sets in chips) and software application writers, who at least will be involved in establishing the proper programming interfaces. What a difference a process node makes.
Analog design has always been considered one of the last bastions of truly creative design, where industry rules don’t necessarily apply and where independent thinking is rewarded by fat profit margins.
That’s about to change., however. Standards are coming to the analog world, driven in large part by the convergence of analog and digital on a system on chip and the need to get SoCs out the door on time and within budget.
“This is a pain point in design,” said Shrenik Mehta, chairman of the standards group Accellera. “If you are getting productivity, people want to re-use that. With analog right now you can’t. You need to get new expertise every time.”
Accellera introduced its first Verilog analog standard during the Design Automation Conference last summer. The standard provided standards for assertions and modeling, but the feature set was limited, said Mehta. He noted that the next version will provide interoperability among the tools.
No less controversial among designers is the standard for power. Accellera’s Unified Power Format (UPF) is pitted directly against Si2’s Common Power Format. However, with the backing of most of the industry’s large players behind UPF—including Mentor Graphics, Synopsys, Magma and Sun Microsystems, it will be an uphill battle for Si2 and Cadence, which turned over CPF to Si2.
UPF has been submitted to IEEE. The first round of balloting generated sufficient votes for the standard to pass, sources say. The next step is for the regulatory community to submit its corrections. Finally, after that process, the standard can be published.
–Ed Sperling
By Ed Sperling
The network on a chip (NoC) approach is gaining ground as an essential part of a system on a chip (SoC), providing the same kind of time-to-market advantage that well-tested intellectual property blocks provide.
This follows almost eight years of hype about NoCs potential with little to show for it. Times have changed and there appear to be two main drivers, one technological and the other business-related. From a technology standpoint, the real key is that chip designs are becoming far too complex to create all the interconnects necessary to get an SoC out the door on time and on budget. From a business perspective, the downturn has cut into staffing of design teams so severely that most companies don’t have the manpower left to develop complex interconnects on a chip that also has multiple cores, multiple power islands, as well as shared busses and memory.
“The key trend that makes such technologies more important is simply the increasing levels of integration, which significantly increase the amount and complexity of the on-chip communication—particularly in the sharing of key resources such as external DRAM,” said Jim Hogan, a venture capitalist familiar with this market. “This complexity permeates every part of the SoC design, from the increasing fraction of circuit delay due to wiring at deeper process nodes up through the massively deeper pipelining required to keep modern DRAMs operating at high efficiency, to the QoS scheduling required to ensure that general purpose software on CPUs can co-exist with real-time communications and multimedia traffic. NoCs provide a structured framework for managing these growing complexities and will therefore become the dominant approach for complex SoCs.”
But structured does not mean standardized. Far from it, in fact. While NoCs fit into standardized EDA flows and work with standards, they are one of the key components that must radically change from design to design.
“At 45nm, and with some designs at 65nm, companies have started to see issues with interconnects” said Charlie Janac, CEO of Arteris. “Projects cost more, they last longer, or they’re being canceled. There’s more problem solving, and the interconnect is more important. When we had single-core chips, it was a choice between a mainframe versus distributed network computing. Now we’re dealing with four to six cores, algorithmic engines, graphics, peripherals and on-chip/off-chip memory. All of this requires more communication on a chip.”
So what exactly is a NoC? Definitions vary, and likely will evolve as NoCs become both more necessary and more widely deployed. And some of the standard definitions are fuzzy at best. Wikipedia, for example, defines a NoC as “an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip.”
Most chip architects view NoCs as more of an evolutionary step than a radically new concept, though, with the difference being that a NoC is now a discrete part of the development process instead of including it as a piece of something else.
“I like to use the phrase ‘network on chip’ to describe what we do and have been doing for a few years,” said James Aldis, SoC architect at Texas Instruments. “My definition is based around the idea of the NoC being a separate component in the top-level assembly, with a point-to-point interface to each other top-level component. This is distinct from a traditional ‘bus’ where the bus is the top-level assembly. The alternative view is that a NoC is really something with a network-style architecture, where you send out bus requests and responses on the same wires. This alternative view means that the external interfaces of the NoC are not traditional ‘bus-style’ but rather ‘network-style.’ Transactions are captured in packets rather than being represented by separate address, data and command busses. This alternative view is not yet real in the IP industry. You can’t buy IP with this sort of interface on its boundary. It may be used internally in some companies.”
The NoC is particularly attractive at advanced process nodes because of the increasingly complexity and the ability to isolate some of that complexity in the network.
“With the advent of SOCs, a lot of complexity has moved into the interconnect. No one building such chips is really using the old “bus” paradigm anymore,” said Geert Rosseel, senior director at Pixelworks. “The interconnect now has to manage communication between IP blocks having very heterogeneous bandwidth and latency requirements and possibly living on different clock and power domains. The interconnect is now managing CPU-type requests with networking and real-time media (video and audio) traffic, usually all directed to shared resources such as memory. In my opinion, everyone building an SOC is already implementing some kind of complex on-chip communication system.”
But the NoC takes that one step further.
“What sets the concept of a NoC apart is the idea of developing an architecturally clean and unified approach to solving this problem,” Rosseel said. “You put all communication complexity in the network with the IP conforming to some simple interface standard. Once you have this ‘clean’ separation, you can develop an interconnect based on internal protocols that are optimized to meet the performance, area and power requirements.”
The final caveat for most NoCs is that they have to embrace both new and existing technology. That includes a number of existing on-chip protocols, the Open Core Protocol (OCP), ARM’s Advanced extensible Interface (AXI) and AMBA High-Performance Bus (AHB), as well as an alphabet soup of proprietary and lesser-known acronyms.
Ian Mackintosh, chairman of OCP-IP, said the real key is to maintain openness, while embracing existing standards. “The world is heterogeneous,” Mackintosh said. “People have worked up from single bus generators to intelligent networks on chips where you need predictive performance of the NoC.”
OCP-IP has been working on a way to standardize NoC benchmarking to help sort through years of attempts to get this right. For further reading on this subject, check out the white paper entitled: “An Iniative Towards Open Network-on-Chip Benchmarks.”
By Ed Sperling
As with all network topologies, the general rule is the faster the better.
Jack Browne, VP of sales and marketing at Sonics, said his customers are asking for higher-speed interconnects. “Right now we’re at 300MHz,” he said. “They want to more than double that in the very near future and eventually get to 1GHz.”
Getting to that speed is no simple matter, and several approaches are under consideration.
One approach now being tested is a wireless network on a chip. Intel, STMicroelectronics and Philips are all experimenting with these techniques, sources say. And in the commercial NoC space, companies such as Arteris, Sonics, Silistix and Inventure are working on similar technologies.
Parthe Pande, assistant professor at Washington State University, said it’s too early to tell which approach will win. “This is a big research problem,” Pande said. “On-chip wireless networks are very promising. The big problem there is the on-chip antennae and how small you can make them. One approach is carbon nanotubes, but there are manufacturing problems.”
Serialized packets are another approach, but the tradeoff so far has been increased latency. At least part of that is caused by the complexity of designing systems with dedicated wires, shared busses and segmented busses, as well as algorithms that do not take advantage of all the options. Parallelization remains one of the chief conundrums for all levels of chip and software design.
Brad McCredie, an IBM’s chief architect for the Power6 chip, said to understand what’s happening on a chip becomes evident when you look outside the chip because everything is being consolidated into the chip.
“There’s been a lot of research into optical and on-chip optical, but economics never let that happen,” he said. “Whether it happens in the future we don’t know. But between chips, there is a firm direction toward a parallel bus. In cluster configurations we’re seeing packets.”
He said IBM currently is working on 3GHz packet-switch networks on chip for DARPA. But those chips are using parallelized packet switching. The bulk of the work so far has been serialized, and experts say that has created latency issues.
“The main bottleneck right now is parallelizing software,” said Pande. “This is a very hot research topic right now. Packets are another big research problem.”
One approach is to divide the packets into six parts, slimming down the data being sent and avoiding storage of the packets in cache. But Pande said there is still an enormous amount of work to be done, and so far there is no clear winner emerging from the research.
By Ed Sperling
The trouble with standards is that many of them arise out of need rather than through careful planning, and often unilaterally.
The typical scenario in chip design is that a company has an issue to solve, so it comes up with a solution. When it gets what it believes is critical mass behind the standard, the company that developed the solution opens it up to the rest of the industry, hoping that it will either attract new customers or get enough of a jump on the market to create incremental business.
This has been repeated with languages—hardware description and software programming, to name a couple—as well as intellectual property and just about every other tool used in chip design, development and verification. And when there is more than one approach, those competing and often incompatible technologies are typically integrated so that everything can work together and the industry can move on to the next challenge.
That appears to be happening now in the on-chip interface world, where ARM’s AMBA, IBM’s CoreConnect and OCP-IP are all battling for attention. Both ARM and CoreConnect are entrenched in their individual markets, but with multicore chips becoming common the separate approach presents challenges to engineers.
“All of this technology is good,” said Sudeep Pasricha, who wrote a book called “On-Chip Communication Architectures: System on Chip Interconnect,”, and assistant professor in Colorado State University’s department of electrical and computer engineering. “The bad is there are a lot of issues making it all work together. If you integrate an ARM core with a CoreConnect bus standard, there’s a mismatch of protocols. You can fix it. You can develop components that work with the different standards. But it’s expensive and it takes time.”
The problem gets exponentially worse in multicore chips, where every device is basically a network on chip running under a system on chip. Cores need to communicate across that network, but frequently they are heterogeneous collections of IP. That means multiple vendors building technology on a single substrate using different protocols and interfaces. The opportunity for confusion increases with every core.
In fact, Pasricha said IBM is in the process of developing its own NoC for the Cell processor that uses packet switching for chips with 50 to 100 cores. The interface is being custom-developed by IBM, he said.
OCP-IP, meanwhile, is looking to represent the middle ground in all of this, raising up the level of abstraction by adding connections in much the same way that middleware does for disparate application software. “Our approach was to develop a socket to deal with all kinds of IP, whether it’s a graphics processor or a media processor,” said Ian Mackintosh, chairman of OCP-IP. “AMBA is very well accepted around the processor subsystem, but OCP (Open Core Protocol) will handle the broader system better. We also have worked closely with OSCI (the Open SystemC Initiative) so we are TLM 2.0 compatible. Our TL3 is compatible with TLM 2.0.”
OCP-IP currently is benchmarking NoCs to ensure there is no performance degradation when various interfaces are used. “This is becoming critical because of the diverse sets of IP that are being used,” said Mackintosh. “We’re not dealing with just one processor anymore.”
And just to make matters even more confusing, the industry isn’t dealing with a single NoC approach, either. In addition to IBM’s new NoC and Texas Instruments’ OMAP platform, there are four other commercial NoC players: Sonics, Silistix (United States), Arteris (France), and Inventure (Japan).
The bottom line: Even as we resolve some of the confusion, more is being added.