By Ed Sperling
Mentor Graphics boosted the functionality of its PCB tools, adding 3D field solvers and thermal/power co-simulation analysis. This is particularly important for high-speed interconnects such as SerDes, which requires 3D modeling for signal integrity analysis.

Cadence roared back to life in Q4 with revenue of $308 million compared to $249 million in the same period in 2010, and net income of $11 million (or $46 million non-GAAP) compared to a loss of $37 million in 2010 (or $18 million non-GAAP). The company anticipates revenue will be in the range of $305 million to $315 million this quarter, with annual revenue in the range of $1.24 billion to $1.28 billion.

Sonics and Tensilica are working together to integrate Tensilica’s DSP processor interface with Sonics’ OCP-IP interface. The goal is to boost on-chip performance while making it easier to integrate IP. These kinds of deals are helpful in getting SoCs to market more quickly. Sonics also issued its formal response to rival Arteris’ countersuit.

By Ed Sperling
In what is turning into a legal war over network on chip technology, Arteris filed a counter complaint against Sonics for patent infringement.

Arteris charges that Sonics’ new SonicsGN infringes on two of its patents. It also denied that it has infringed on any of Sonics patents, which Sonics claimed in the lawsuit it filed in November against Artertis lawsuit against Arteris. Arteris is seeking damages and “equitable relief” from Sonics.

Sonics declined to comment.

Historically, patent infringement cases in the technology sector have started when markets are either heating up or when they are in steep decline. In EDA, for example, the majority of legal battles were fought when the industry was in high growth and acquisition mode. In the PC era, the famous battles between Apple and Microsoft were initiated early in the boom cycle.

NoC technology is still in its nascent stage, but it is gaining in popularity at advanced process nodes because of the enormous quantity of IP and the ability to add flexibility into a design on a variety of fronts, including power management.

By Ed Sperling
Fabs and foundries frequently have been the savior of flawed designs, fixing problems such as power and performance, identifying design issues and often developing solutions to those problems.

Over the next couple of process nodes, and in stacked die that will span multiple processes, there will be far fewer saves coming from the back end. Double and triple patterning, stress effects, new materials and the laws of physics are forcing a change in direction. In fact, for the first time design teams will have to make up for a slew of changes and challenges on the manufacturing and packaging side, employing new methodologies, new tools and deeper levels of expertise.

In a keynote speech at the SEMI Industry Strategy Symposium last week, Applied Materials chairman and CEO Mike Splinter sounded the alarm over the changes ahead. “Change is accelerating,” said Splinter. “Compared with the last 15 years, the next five years will have more changes and more inflection points. And it’s not just about complexity. It’s happening at the foundational level of how an IC is made.”

He’s not alone in that assessment. Bernie Meyerson, an IBM fellow, said CMOS is now in “the end game.” While CMOS certainly isn’t going away, there are physical limits for what can be done to extend it. That has spawned extensive research into alternative materials such as silicon on insulator and graphene, new elements for insulation, as well as new structures such as FinFETs and carbon nanotube FETs.

So what does this mean for design at advanced nodes? Lots more work on design for manufacturability, more complexity in achieving the same kinds of boosts in performance and energy efficiency that were taken for granted at older nodes, and much more up-front checking of just about everything.

“From 40nm to 28nm to 20nm, the number of checks for physical verification will grow by leaps and bounds,” said Michael White, director of product marketing for Calibre. “There are almost 1,000 more DRC checks from 40nm to 28nm between early production and volume production. We are also capturing additional context-dependent yield detractors. For example, historically we have had spacing checks. Now we have spacing checks and we need to check all of the other geometries in the neighborhood, including lithography and fill issues. Those are extra constraints.”

Lithography used to be something design teams never had to consider. But the delay in EUV will require double patterning at 22/20nm and potentially even triple patterning of at least some portions of the chip at 14nm. This becomes particularly challenging for design teams, because one of the approaches under serious consideration is something called spacer-assisted double patterning. In simple terms, a polygon design may look nothing like what’s on the mask using SAPD. This is akin to driving a car in reverse using the rearview mirror where nothing that appears in the mirror resembles the road.

Stacking effects
One solution to these issues is stacking of die, whether in 2.5D or 3D configurations. The so-called “More Than Moore” approach bundles technologies together at nodes that make sense for a particular function, rather than trying to fit everything into the most advanced process. So while the logic or memory may be created at 22nm or 14nm, for example, analog may be developed at 130nm.

This all makes sense in theory, but it also adds a new dimension of complexity that ripples back and forth between the design and the manufacturing worlds. It also exposes the entire supply chain into the design process, because problems detected anywhere along the chain can affect multiple other areas—and it’s possible that no single segment can solve them alone.

“Over the next three to five years chips will go vertical,” said Naveed Sherwani, CEO of Open-Silicon. “The question is how we are going to put together 3D ICs and what will go into them. There is a lot that needs to be done in this area.”

Sherwani contends that tools and methodologies should make it easier and quicker to do derivative designs. That’s the goal, and at least part of the solution involves companies learning to use the tools they have more effectively, and to apply some discipline to their methodologies. It’s easy to get blinded by the number of permutations and choices from the growing complexity.

“As process geometries continue to get smaller and the amount of IP used increases, the complexity of the design process becomes a major issue, which puts pressure on the entire development team from a coordination and communication standpoint,” said Simon Butler, CEO of Methodics “Also, with software elements and power constants, which are really just other types of IP, added to the already very complex mix of things, design teams need better ways to manage the entire SoC development process and synchronize all the moving parts. Internal design organizations already struggle with managing remote design teams. Now, with a disaggregated design chain consisting of separate companies, the need for real-time collaboration and managed data exchange is critical.”

That sentiment is echoed across the industry. Frank Schirrmeister, senior director for the Cadence System Development Suite, said that in principal tools allow engineers to model almost everything they need. “This isn’t a tool problem. It’s a discipline problem. But the other side of this is that in 1993 logic synthesis was pretty simple. Twelve years later, the whole process is not longer understandable by any engineer.”

Margin call
One of the most effective ways to deal with unknowns in the past is guard-banding—the process of building extra safeguards into ICs. That worked until about 65nm, but at advanced nodes it can cause performance degradations or drain batteries more quickly, or both.

“The guard band for synthesis is a smaller percentage at 28nm and it’s even smaller at 20nm,” said Jack Browne, senior vice president of sales and marketing at Sonics. “So you’ve got to be able to interoperate with the right guys. We’re all trying to manage a horrible amount of complexity and simplify it. The problem is there is too much that’s new and not enough experience points so that people can make the safe choices. There are significant unknowns on everyone’s road map.”

One potential solution—and one that’s being considered by a number of large chip and IP companies—is to harden everything into pre-qualified, pre-verified subsystems. While this limits the number of permutations, it does take some of the risk out of using those blocks. But too many hardened subsystems also can limit the ability of companies to differentiate their designs. And while that works well at a company like Apple, it does not work so well at a chip company trying to sell technology to Apple’s competitors.

“With subsystems you’ve closed the black box and given up the chance to turn some of the dials,” Browne said. “We’re seeing this with the TI OMAP team, which has accumulated a significant number of libraries and with Broadcom. And Toshiba has created video and RF subsystems.”

Caution ahead
All of these issues have raised questions about what needs to be fixed in the design flow, what needs to be extended, and how this will unfold over time. The reality is that changes may be slow because there is serious uncertainty about exactly what problems will erupt, where and when.

“There’s always a risk of getting too far ahead with the tools,” said Steve Smith, senior director of platform marketing at Synopsys. “We will add capabilities to current tools to make them 3D aware, but the goal is to enable engineers to do what they do best. We’re already dealing with multicorner, multimode design, and 3D will be another dimension. We might have coupling effects and we certainly will have a challenge with temperature. But most of the processes are familiar, and changing things in a working flow is always risky.”

By Ed Sperling
Just in time for the holidays. Cadence’s Tom Anderson finds some real-world assertions, including some embarrassing typos that can change the meaning—and value—of products. Details, details. Santa, you delivered the wrong present to the wrong house on the wrong day.

Mentor’s Jay Gorajia digs into the guidelines for production planning and scheduling. There’s a lot of really good information here. Take notes.

Synopsys’ Hannah Watanabe pulls together the best of the company’s recent Interoperability Forum, which featured speakers from ST, ARM, Accellera and some private venture capitalists. There are a lot of road maps to study. So little time, such small features.

Cadence’s Richard Goering reports on a panel about how power minimization and optimization dominate front-end design. That seems to be the consensus everywhere, and the problem isn’t going away.

Semico’s Joanne Itow attends Semicon Japan and finds lots of optimism for the future, particularly in the used equipment market. There’s a lot of good insight about the intricacies of this market, including some unexpected tidbits.

DeepChip’s John Cooley surveys the market about concerns over Synopsys’ acquisition of Magma. The biggest negatives involve less competition. But why are the 10% who are in favor of this move and the 9% who are neutral so quiet?

Mentor’s Colin Walls does take two on RTOS test harnesses, and where and when to use them. Given the focus on software debugging and test, this is a very good topic.

Synopsys’ Doug Amos looks at deadlines and what can go wrong. Sorry, Christmas has been canceled this year.

Cadence’s Jack Erickson points to a high-level synthesis discussion by Freescale engineers involving a C-to-silicon FPGA prototype based on control logic rather than dominated by the datapath. This is a twist.

And in case you missed the most recent issue of the System-Level Design newsletter, here are some standout blogs:

–Mentor’s Jon McDonald looks at the tradeoffs between AT and LT.

–Cadence’s Frank Schirrmeister brings good tidings and not-so-good tidings for software developers.

– Synopsys’ Achim Nohl talks about ways to improved battery life with virtual prototypes.

–Sonics’ Frank Ferro zeroes in on what makes a product successful. Hint: It’s more than just the technology.

–Arteris’ Kurt Shuler takes a children’s story and applies it to the semiconductor IP industry.

–Atrenta’s Mike Gianfagna makes some predictions about how the EDA industry will change in 2012. If they come true, there will be more dropping next New Year’s Eve than a ball.

–Methodics’ Simon Butler tracks the challenges in design and IP management across the globe and finds similar problems everywhere.

By Ed Sperling
Mentor Graphics introduced an integrated component-to-system thermal characterization and analysis solution that combines hardware test with its FloTherm software. This is a particularly interesting more for the LED and IC packaging arenas, given the focus on leakage and heat.

Cadence won a deal with Panasonic for its Palladium XP platform, which combines simulation, acceleration and emulation. The tools will be used in a variety of digital consumer electronics.

HiSilicon has licensed eSilicon’s 40nm ternary content-addressable memory macros for its networking chips.

Blu-Wireless has licensed Sonics’ on-chip communications IP for its wireless communications processors aimed at the unlicensed 60 GHz market. Blu-Wireless will use the IP for a new generation of multi-gigabit communications for consumer electronics.

Synopsys claimed a share of the victory in GlobalFoundries first complex 20nm tapeout, complete with double patterning. A number of Synopsys tools were used to achieve silicon success.

By Ed Sperling
Cadence’s Jack Erickson adds another angle to make vs. buy: re-use. It’s still make vs. buy, but with the extra dimension of time.

Mentor’s Colin Walls wants to know what the plural of Linux is? There are, after all, multiple distributions of the OS. But his quandary stems from the assumption that it’s a noun. Maybe it’s an adjective, as in, “Linux versions” or “Linux OS.”

Synopsys’ Eric Huang compares the user habits of people who buy the iPad vs. the Kindle Fire. The good news is the TSA hasn’t stopped anyone for using a device with the word “Fire” on it.

DeepChip’s John Cooley reports a potential customer is looking for details about the usefulness of Apache and Atrenta tools. Opportunity knocks.

Cadence’s Richard Goering calls attention to an ARM TechCon paper about using virtual platforms for multicore software development. Given complexity and time-to-market issues, there may not be a choice.

Mentor’s Robin Bornoff digs into the wonders of cooling systems for a desktop PC. It’s a lot of work for something that could have been designed differently.

Synopsys’ Tom De Schutter looks into recycling and re-using of TLM models, which is possible as long as you can meet the requirements.

Semico’s Jim Feldhan predicts that plug-in electric vehicles will be in high demand by consumers. We’d like to add to that an increased demand for three-car garages and higher insurance costs.

Cadence’s Frank Schirrmeister questions whether software development will cause another industrial revolution. At the very least, it will have a big effect on current industry.

And in case you missed the latest System-Level Design newsletter, here are some standout blogs from that issue: http://chipdesignmag.com/sld/wp-content/newsletter/2011/11/

–Mentor’s Jon McDonald comes up with a revelation about ESL over dinner.

– Synopsys’ Achim Nohl looks at software bugs and how to stop them from wreaking havoc on a design.

–Cadence’s Frank Schirrmeister focuses on the extensibility of TLMs and why it’s so crucial.

–Atrenta’s Tiffany Sparks exposes the stressful reality behind some over-used buzzwords.

–Arteris’ Kurt Shuler looks at China’s push into communications infrastructure and energy efficiency and the resulting market opportunities.

–Sonics John Bainbridge examines the concept of decoupling to improve performance and power management.

–And Methodics’ Simon Butler takes a look at an SoC-oriented design data management system and how to avoid lots of problems.

By Ed Sperling
Hitting market windows with IC designs has always been a struggle, but the race to the finish line is becoming more critical—and much more difficult. The reason: Market windows themselves are shrinking.

Products that used to stick around for years may now only last for months, replaced by newer versions that offer either better performance or lower power. In many cases, particularly for the hottest consumer markets that drive the highest volumes, there isn’t even time for competing on cost with derivative chips. The so-called long tail of design now looks significantly shorter, overtaken by a quick ramp up to the next SoC.

This raises a slew of new concerns among chip designers about which market opportunities are worth the risk, at which process node, and how to get there quickest with the least amount of risk. It also raises issues among tools developers about how many customers there will be for tools if the largest customers skip process nodes. And it raises the stakes across the board for making bad decisions, because they can no longer be amortized across dozens of derivative designs.

Changing market dynamics
What’s behind much of this is a shift in consumer buying habits. It’s not that consumers necessarily buy more devices, but they buy them much more quickly after the release date. The iPhone 4S was a classic example. Within four days of its introduction sales had topped 1 million units, something that took years for previous product lines.

“We used to be able to use a shotgun approach,” said Mike Gianfagna, vice president of marketing at Atrenta. “Now it’s more like a precision rifle shot. And if you don’t hit it just right, the market is gone.”

Time-to-market has escalated from important to critical. But for most companies that also involves a disaggegrated supply chain, which tends to slow down the design process more compared with IDMs such as Intel and Samsung, which have regular communications between fab, design teams and debug operations.

“What we’re heading toward is virtual re-aggregation,” said Gianfagna. “But that’s going to require speed and perfection, a lot of standards, and changes throughout design.”

It also changes the rules about how companies go to market with new ideas and technology.

“Traditionally, people went into market to test the waters,” said Neil Hand, group marketing director for Cadence’s SoC Realization Group. “The way things are now, you have to get it right. And if you’re successful, you have to quickly turn out new products. Product planning is important, but you also have to build in flexibility.”

Multi-patterning, packaging, and physics
It also requires some techniques and approaches that were not even considered in the design process until very recently. Sequential flows are now concurrent, with manufacturing now an important element of the early design phase. One area that is a particular trouble spot involves lithography, where EUV has been considered the best hope for etching extremely thin lines. EUV was expected to be commercially viable years ago. It’s still in the development stage, which is why the industry is heading to double patterning at 22/20nm. And that slows down the whole process significantly.

“Double patterning means you’re splitting a single mask up into two masks,” said Wally Rhines, chairman and CEO of Mentor Graphics. “And at 14nm we’re still uncertain whether the solution will be EUV or triple patterning. It could be either one. It depends on the development schedule of EUV. We may have a node that starts out without EUV and ends up with EUV. From the perspective of power and throughput it’s still a long way from production-worthy. The backup is triple patterning. It’s undesirable from a cost point of view.”

For an industry that has banked heavily on proven techniques and processes, this is a remarkably untested future with a very uncertain throughput and cost structure, filled with a variety of other risk factors.

Stacking of die will complicate that further, because understanding the stress impact of TSVs remains fuzzy, at best. Interposers are slightly better tested, particularly more advanced versions that potentially use new materials. In addition, wide I/O standards are still being developed, and so are ways of connecting all the pieces together, testing and debugging them, and figuring out how to deal with heat dissipation.

There’s also a question about what will get valued most in this new approach—and where the development dollars will go for tools. That also can affect time to market, because if the tools aren’t updated or integrated companies will have to do that work themselves—something they’ve done in areas such as rapid prototyping until recently, when commercially integrated solutions became available.

“It’s a little like the automotive or aircraft industry,” said Rhines. “The people who put the pieces together are system integrators. They deal with multiple die. They deal with software. They deal with interconnects. They are system designers. Then the individual die, an the individual IP, are component suppliers to each other. Today that IP serves as a barrier, but it will commoditize. System integrators get paid more than component suppliers, and components become commodities.”

Unbundling and future changes
One way to facilitate these kinds of changes is by unbundling the individual pieces in an SoC.

“There are really relatively few new hardware blocks being added to new designs,” said Drew Wingard, chief technology officer at Sonics. “The exception is the continued improvement in processor cores from ARM or graphics engines. Mostly it’s continued pressure on integration, and we believe strongly the only way to deal with this effectively is to isolate the components.”

He noted that interdependencies make it difficult to advance one component in a package without also making changes to another component. That has proven particularly problematic for mixed signal blocks, where shrinkage of digital features has forced similar but extremely painful shrinkage of analog processes. By separating those worlds, progress can be made in both portions of the block when it makes sense.

“If you can decouple the verification you can divide and conquer,” said Wingard. “That allows you to do verification at the subsystem level and re-use testbench code. A lot more companies also are thinking about designs in a platform-based way. A platform is a set of decisions you’ve made, and then you abstract up and down.”

Platforms have been talked about for years as a future direction. Intel, which used to churn out dozens of different chips for various PC markets, adopted a platform approach with the introduction of its Core architecture. ARM has done the same with its Cortex line. And while SoC developers have had a much more difficult time with this approach, many of components within those chips are developed using a platform approach.

But every decision has ramifications in an SoC. While it’s okay to unbundle the components, everything is tied to everything else in ways that extend well beyond the chip.

“When you develop a chip in the wireless space you have to make sure you’re in sync with the carriers, the handset makers, and the whole value chain,” said Kurt Shuler, director of marketing at Arteris. “This becomes a problem when you start shrinking the design time. It used to take 18 to 24 months to gather requirements to put a chip out there. Now the best designs take 9 to 12 months, and the most advanced companies are pushing to get that down to 6 to 9 months. The only way to do that is with a platform approach where you have one hardware and software platform and you can re-use the hardware and software investment.”

Re-use is driving a significant portion of Synopsys’ business these days. It’s no longer just IP blocks that are being sold. It’s IP plus software, and often in conjunction with services.

“We absolutely believe the next major evolution is subsystems of larger integrated blocks,” said John Koeter, vice president of marketing for Synopsys’ Solutions Group. Those subsystems increasingly are customized for very specific markets, as well, to both reduce risk and decrease the time it takes to get an SoC out the door. “These are very market-specific, he said. In the audio area an MP3 will have codecs that are different from a home entertainment system. We’re also seeing an increased willingness among companies to outsource. It’s not just small companies, either. It’s also the big tier-one companies that are questioning whether a USB is differentiating their chip.”

The push for more standards
Platforms also require standards, and there is mounting pressure on all of the standards bodies to ramp up the number and quality of standards—and to avoid dual standards such as UPF and CPF. But hidden in all of this also is a recognition that vendors will have to pick their battles. They can’t compete on all fronts and still have progress in standards.

“Standards are created largely around efficient ways of exchanging data in design and manufacturing,” said Steve Schulz, president and CEO of Si2. “If you had to re-do models for every foundry chip that would quickly get out of scale. Standards allow companies to get to market faster.”

That becomes more difficult in stacked, however, which involves more companies from across the supply chain. The promise of stacked die is re-usability, possibly with entire logic or analog “platforms” as part of the stack.

“Everything about 3D is a supply-chain view,” said Schulz. “You need to understand the whole landscape to do anything in 3D. How do you describe hot spots on a die? What’s the basic connectivity between the package and the pins? How are you going to develop the interposers? If you create process design kits will they need to understand the process impact of TSVs? And when is all of this going to happen? We’re not sure about the time frame.”

Conclusions
Dealing with time-to-market pressures has always been a concern, but rarely did being late to market mean missing out on the market entirely. That reality is changing, however, putting pressure on teams to figure out ways to ensure quicker turnarounds with better results.

Software, in particular, is a problem that needs to be dealt with effectively. As Cadence’s Hand says, “We need to bring down design and manufacturing costs, but software is still the killer.”

To some extent this is likely to force some hiring in the industry. Companies never replenished their ranks after laying off engineers in 2008. It also will require more tools, because automation is much faster in the hands of trained engineers than spreadsheets and trial and error. And it will require renewed cooperation to push through standards in areas where companies can agree it’s not necessary to compete—or where competition may slow down entire markets.

These changes also are likely to reshape the IC industry in ways we cannot even begin to comprehend at the moment. At the base of all of this is a fundamental and global shift that time to market will no longer be determined from the bottom up. It will be driven from the top down—by the consumers of the technology who are willing to spend quickly and decisively rather than mulling purchases for months or years. The winners will be those that can figure out a way to meet that need—and the losers will be either quickly absorbed or, worse, forgotten.

By Ann Steffora Mutschler
The confounding ‘make versus buy’ decision is understandably muddled by design complexity. Millions of gates, thousands of blocks, dozens of cores, plus software, packaging, and worries about physical effects don’t make this decision any easier.

In some cases the process can be simplified by mandating that anything that doesn’t add differentiation really is an IP block, and as such, it should not be built in-house. The exceptions, of course, are large fabless semiconductor companies that have an internal IP group, and which can amortize the development costs across a large number of chips.

Alex Haggenmiller, director of central R&D at Lantiq, a developer of SoCs focused on next-generation networks and the digital home, said his company has a simple rule: “The one rule is everything that is standard and where you do not have to expect major changes, this we will license. USB, PCI, DDR—this is not worthwhile to do in-house because we don’t have many analog designers.”

Also, if the company does not have expertise for a particular IP it needs, and that available from a third party, it will be licensed, he said. “But if we see that we can differentiate on one or the other IP, and we have the know-how, then we will do it in-house. For example, a T PHY, a 10/000 or 1,000 Gbit Ethernet PHY, where you need to embed this and from a power perspective be very attractive, then we will do this in-house. The prerequisite of course is always that we have the know-how, because if you have to build up the know-how and then do an in-house development you lose too much time.”

For standard IP, Lantiq’s goal is to go 100% with external providers.

Depending on the user category, however, the reason behind the “make” decision can vary, said Kalar Rajendiran, senior director of marketing at eSilicon.

For a foundry, foundation IP such as basic standard cells, standard I/O, and memory-bit cells are core to their business. Second-tier foundries may decide to hire companies to build more than foundation IP for them because the third-party IP companies are busy developing IP based on top-tier foundries’ processes.

When it comes to semiconductor companies developing (n+1)-process-based products, because foundries are very tight-lipped about openly sharing technical information on their very leading edge processes, third-party IP companies are unable to develop IP for these processes early on. So these semiconductor companies work directly with the foundries to develop the required IP. Sometimes they hire third-party companies as contractors to develop IP for them. Because they are always staying at the very leading edge, they maintain an in-house IP development team, if not for developing the entire IP set, at least to manage and interface with the third-party IP company that is on contract.

Then, for companies developing products based on exotic-processes, Rajendiran noted that because there is not a large market for this kind of IP, it is difficult to convince a third-party IP company to develop this IP. So these companies will end up developing IP on their own or by hiring a contractor to develop it for them.

For all other users, buying from the broad third-party IP supplier base is what will make sense, he said. If some customization is required, the customer is better off negotiating an IP customization contract with an IP company or a value-chain producer. The difference is that with a value-chain producer, the customer shares the common goal of taking the IP into volume production as part of their ASIC or ASSP whereas with an IP company, which just agrees to customize the IP, the contractual responsibility typically ends when the IP is customized and the design database is delivered to the customer.

Particular market segments can make a difference too. In the mixed-signal arena, there is a significant move to outsource a lot of IP thanks to modern SoCs, which contain a high level of complexity in the interfaces, said Neil Hand, group marketing director for Cadence’s SoC Realization Group. “This means there are complex interfaces involving high-speed SerDes, analog front ends, and all kinds of mixed-signal IPs that are particularly sensitive to the design they are going in and require special skills. So then you ask, ‘Do I build out my own expertise to build this or just go buy the IP? When it doesn’t work, do I have the expertise to fix it?’ If I’ve got third-party IP, its the vendor’s responsibility to resolve the problem.”

Sonics’ Jack Browne agreed. “The make versus buy question around a microprocessor—MIPS, ARM, Tensilica or ARC—is really about the software and ecosystem and what you are trying to accomplish with it. The real make versus buy is what it costs to build your own ecosystem for a processor. Everybody needs software tool, compilers, debuggers and you can get a lot of that open source.”

With approximately 20% of designs today in the 100 million-gate range and above, interesting challenges are emerging for IP, EDA and software, observed Navraj Nandra, senior director of marketing for analog and mixed-signal IP at Synopsys. “From the IP side of it, customers are expecting ready-to-go blocks that are fully verified in the latest technologies. And for many customers, they’ve already gone through this make-versus-buy transition because they’ve realized in their design team in order to put together a 28nm, 100 million-gate chip it’s going to take a big design team comprised of design engineers, verification engineers and software engineers.”

Overdesign contributes to decision-making
It is safe to say that many – if not most – SoCs are overdesigned today. But what is the impact on the cost equation? Cadence’s Hand questions what the cost of overdesign is versus the cost impact of underdesign? “Right now, if you tried to design to the limit you have two impacts. First, if you get it wrong, you’ll miss the market and you’re no good anymore. Second, you may be limiting yourself in terms of how widely you can apply something.”

In that way, Hand says overdesign is necessarily a bad decision. “Overdesign may be the most cost-effective way of getting somewhere. Let’s say you need to get to a point as quickly as possible. If you’re not really worried much about power or squeezing every last drop out of the system, you can drop a much bigger processor in there, do a sloppy job on software, get to market sooner and maybe increase the cost of your device by a few pennies. I’m not saying people should do that, of course.”

Preferring to call ‘overdesign’ by a more user-friendly term, ‘redundancy,’ Synopsys’ Nandra explained that pressures leading to redundancy are the ability to make sure the design will work in different cases, along with the ever-daunting time to market.

“These chips are going into product lifecycles of a year at most, then the next generation comes out. Basically, they’ve got to work right off the bat. If you’ve got to go through another re-spin and fab cycle, you’re going to lose your market window. That’s where overdesign or redundancy comes in. What you’re trying to do is cover your bases. If the memory compiler doesn’t quite yield in this new technology, we’ll put lots of redundant bit cells in there to make sure that at least we’ll get this block to work in production. What you’ve done is halved your risk, but you may have increased the area. The overdesign happens to solve some of these challenges of yield, but you don’t always get an optimum design in terms of area or power consumption.”

Here is where the chip planning, IP management and architectural analysis tools promise to give greater visibility into what is being built, improve predictability, and give the cost perspective up front.

For now, the make versus buy decision is no easier than it has been in the past due to complexity. But pulling in data from early in the tradeoff stage can help not only with architectural decisions but shining light on the cost equation, as well.

By Ed Sperling
Sonics filed suit against Arteris for infringing on network on chip patents, while Arteris rebuffed the claims. Things must be really heating up in the NoC space. http://chipdesignmag.com/sld/blog/2011/11/03/sonics-sues-arteris/

Tower Jazz’s qualified Cadence’s mixed-signal solution and PDK for its 180nm and 350nm reference flow 2.0 using bipolar CMOS-DMOS (BCD) process technologies.

ARM acquired Prolific, a startup hat develops tools for optimizing power, performance and area.

Also on the IP front, Methodics entered the Japanese market with its SoC design data and IP management platforms. Japan is one of the leading adopters of advanced EDA tools and IP.

GlobalFoundries named a new CEO, Ajit Manocha, which is rather anticlimactic. He had been serving on an interim basis since June.

And TSMC reported its Q3 numbers. Revenue decreased 4.5% sequentially from Q2, but it was up 4% from the same period in 2010. What’s particularly interesting is the breakdown. The company said 40nm and 28nm accounted for 27% of total revenues, while 65nm accounted for another 27%.

By Ed Sperling
Sonics filed a patent infringement suit involving seven different patents against rival Arteris yesterday in U.S. District Court in San Jose.

The patents date back to 1998—five years before Arteris was founded—and range from end-to-end connectivity to scheduling of requests and decomposing and verifying configurable hardware. This is the first major action in the network on chip (NoC) arena, signaling that the market is really beginning to take hold as complexity and re-configurability become critical to SoC design.

Sonics is seeking a permanent injunction, treble damages and attorneys’ fees.

Arteris today said it does not believe it needs to take a license for any Sonics patent, claiming it has 31 international patents of its own. Arteris CEO Charlie Janac called it “disappointing” that Sonics is looking to slow down Arteris’ momentum through legal action rather than “competing fairly” in the market.