By Ed Sperling
The push to “smaller, faster and cheaper” hasn’t changed since ICs were first introduced, but the context for those requirements is beginning to shift—with enormous consequences.

What was once done on multiple chips continue to migrate to a single chip or package because of cost, but in some cases the decisions about goes where go well beyond an individual device to include a network of systems. Power and heat have forced some of those decisions. Others are being driven by shorter market windows that affect business decisions about exactly when to move to smaller, faster and cheaper, and whether to keep a design in two dimensions or move to three. In some cases, it even has evolved into a tradeoff about sharing resources to make up for additional costs elsewhere in a design.

“Form factor is everything in a lot of these cases, and you’re being forced to make tradeoffs involving a lot of different pieces,” said Mike Gianfagna, vice president of marketing at Atrenta. “But that requires you to know exactly what you’re doing. A lot of times you don’t. What happens when you reduce the number of layers? Do you know the impact on the system? You may not. But competitive pressure is also forcing you to rethink everything.”

Rethinking designs
Some of these changes are as fundamental as where the processing gets done. While the concept of cloud computing has been around since the days of time sharing on mainframe computers in the 1960s, the ability to offload processing and storage on the fly—and to load balance across compute farms around the globe—adds a modern twist to it all.

The result is a handheld device with the performance capabilities of a compute farm—but with the design focused far less on local processing and storage and more on communication and battery life.

This is evident with a number of upcoming communications schemes and protocols in the handheld market. LTE Advanced, for example, which is expected to find its way into smart phones and base stations over the next four years, focuses on reducing power while increasing performance. One of the best ways to do that is by shifting what processing is done where.

“One of the key decisions is how much processing and intelligence is in the cell phone versus the cloud,” said Graham Wilson, a product marketing manager at Tensilica. “You also have to understand deeply what cores are being used for. There is no room for fat. We’re also going to see a big shift in infrastructure from homogeneous to heterogeneous.”

That means rather than a giant cell tower on the highest hill or building, smaller boxes will be mounted on houses and strung together in a mesh network. “Every house will have its own femto cell or pico cell box so they’re less reliant on the macro cell and they work off each other,” Wilson said.

That changes what resources can be committed within a design to processing, to communication, to storage, and where it can be done best—whether it’s a central processing unit or lots of smaller processors for individual uses. It also boosts the ability to cut some costs in different places than just by shrinking the process geometries in a design.

The Low-Latency Interface working group of the MIPI alliance, for example, is currently working on a new standard that allows DRAM memory to be shared between two chips. NoC technology vendors, in particular, have seen this push because it requires a highly efficient network-on-chip infrastructure.

“The big advantage is that it allows you to get rid of an entire memory chip,” said Kurt Shuler, vice president of marketing at Arteris. “The modem and the application processor are sharing the same memory. You also reduce the number of pins, which is important because it allows you to use those pins for other things.”

He notes there is a very slight performance hit. But the ability to eliminate an entire memory chip can save a couple dollars in a design. Multiply that times millions of units and the savings are huge—far greater than just shrinking the features on a die.

Rethinking packaging
Stacking die offers another alternative to improving performance and time to market, but the tradeoff will be in cost unless additional components can be eliminated. Adding an interposer layer or TSVs will be expensive—at least initially—even though 2.5D and full 3D stacking hold the promise of dramatically improving performance through shorter distances, bigger pipes for data, and lower power because signals will not have to be driven as far.

While this packaging approach is still under development, foundries report that chips are rolling out using this approach. “This is already happening,” said Luigi Capodieci, R&D Fellow at GlobalFoundries. “It’s mostly a decision of which design processes to use in the chip, and that decision will have to be made by the chip designers.”

Stacked die also allow IP developed at older nodes—particularly analog—to be attached through Wide I/O to other chips developed at more advanced processes. That, at least in theory, substantially reduces the time it takes to design a chip because much of it can be based on what has been previously developed.

“Re-use leads to a reduction in time to market,” said Shrikrishna Gokhale, COO and managing director of Open-Silicon’s India unit. “This opens up the lifecycle of different IP and puts the emphasis on packaging and re-use.”

It also puts greater emphasis on software-hardware co-design, he said, and requires more emphasis on defining partitioning earlier in the architecture phase. In addition, it requires a rethinking of what gets done where. Some portions of the design that used to be in separate locations now have to be co-located in the same place because of the constant need to update models and data for both hardware and software teams.

“The logic front-end design needs to be done at the same location as the software,” he said. “That’s less important at the back end, which is the physical implementation.”

Other tradeoffs are less obvious, though, particularly to design engineers. One involves weight.

“Half the weight of a tablet is the battery,” said Drew Wingard, CTO of Sonics. “You can’t afford to add a bigger battery so you have to do an increasing amount of computation with lower power. That means you look at more efficient ways of doing that computing. One is using the GPU as a general-purpose CPU, which allows you to get a lot of performance at low energy.”

He noted that utilizing the GPU requires it to be easily accessible to software developers. And it requires much better management of clock domains, voltages and on-off functionality within an acceptable power budget. And to be really energy-efficient, users need to be able to easily input their own usage models.

Rethinking manufacturing
Some of the changes that are under way are forcing a major shift in manufacturing, too. Staying on the Moore’s Law road map has always been a given for high-volume digital designs, but with double patterning required at 14nm and the delay in extreme ultraviolet lithography, alternatives are being considered that could have ramifications throughout IC design.

“Double patterning is the biggest issue we’re dealing with right now,” said Jean-Marie Brunet, director of product marketing for model-based DFM and place and route integration at Mentor Graphics. “We’re even looking at triple patterning, but there is no way to have density balance between the layers when you do that.”

Lars Liebman, an IBM distinguished engineer, said his company has been working on commercializing self-assembly for finFETs because even multi-patterning isn’t sufficient beyond 14nm. That has implications throughout the design chain. For one thing, it can increase the density on existing process nodes. For another, many of the tools for automating design, particularly on the DFM side, will need to be rewritten.

Conclusion
Area, power and performance have always been the standard metrics for tradeoff in any IC design. What’s changing significantly is why those tradeoffs are being made and where the benefits will show up. Changes targeted at an individual chip in the past, or even a block or subsystem, may now be aimed at a much broader level.

The good news is that infrastructure changes—everything from manufacturing approaches to communications networks—evolve much more slowly and deliberately than those made in the individual device or chip. The bad news is that sometimes that moves so slowly that it can affect what’s done elsewhere in this much broader system. But some change is underway at every level, and managing that change—and the tradeoffs it will demand—will be much more challenging in the future.

By Ann Steffora Mutschler
With the cost of designing and producing even moderately advanced SoCs skyrocketing, semiconductor companies and systems houses must find ways to defray the cost across a larger number of end uses than ever. As such many companies have adopted a platform-based derivative design approach, with that the platform serving as the first SoC design of a new family.

That strategy is expected to become far more widespread as mainstream process nodes push beyond 40nm, outsourcing of entire subsystems becomes more popular, and stacking of die gains traction.

“There used to be this idea that you would define this platform and all the chips would be derivatives of that platform,” said Drew Wingard, CTO at Sonics. “Now it’s more of, ‘No, we can’t afford to think about trying to build the platform itself. Instead, we are going to build the first chip, but we are going to use a platform-based design approach, which basically says we’re going to set ourselves up so that we can make derivatives.’ The way to sell this to more people is to personalize it for different customers or for different markets or for different regions of the world by making these derivatives. I think that’s a very common need that’s expressed to us by our customers, and it’s all of course about defraying the cost.”

But what exactly is a platform? A commonly cited definition was provided by Alberto Sangiovanni-Vincentelli, a professor of electrical engineering at the University of California at Berkeley, who is best known for co-founding both Synopsys and Cadence. He defined a platform as a set of choices that you’ve made, and because you’ve made those choices you can then abstract upwards from them to a higher level of design abstraction. And because you’ve fixed those aspects, you can refine downward.

“So the question then in a platform design is, ‘What things do you fix, what decisions do make and what decisions do you make flexible,’” said Wingard. “What things can you make different in each of the different derivatives? That’s what gets interesting about this whole theory of platform-based design.”

Of course, companies like Intel have been derivative powerhouses from the very beginning, noted Naveed Sherwani, president and CEO of Open-Silicon. “That’s actually what their strength is. They would have one or two teams chase new designs, then they would have 5, 10, or 15 teams do derivatives. The challenge is not actually to do derivative engineering. The challenge is how to do derivative engineering in the most cost-effective fashion.”

What is considered cost-effective today, however, is a different formula from what applied five years ago.

“Derivatives are being used to chase smaller and smaller markets because markets are fragmenting,” Sherwani said. “We have the long tail effect. We don’t have that $3 billion market to chase. Those are few and far between. Now we have to go chase that $200 million or $400 million market. Previously you could be more inefficient in your derivative design and you could afford to be late, but now you have to be very efficient because you are chasing a smaller market.”

A second consideration is to determine if a derivative will be outsourced. That requires effort in every aspect of chip development. “You have to have a full vertical team, and that’s not quite the case when we’re doing ASICs. Somebody is giving us fully functional RTL and our job is to do physical design, tape it out and get a working part. That is a completely different phenomenon when you go to derivative design,” Sherwani continued.

Closely connected with this decision is the rapid rise in various forms of die stacking—system in package or 2.5D with a silicon interposer—which has given semiconductor and systems developers a greater degree of freedom to choose the right option for their situation.

In this realm, Jack Harding, president and CEO of eSilicon explained the company is seeing large semiconductor and systems companies who say, “I’ve got this large inventory of successful parts. I’ve got for example, 180nm die sitting on the shelf and I’ve got this other 65nm die I got from the guy down the street and I got this RF radio I got from Skyworks and I’m going to put that all together and make some sort of product as opposed to actually making a brand new chip. The thought process is much like making a derivative. You’re making an architecture, you’re considering the software implications, you want to use as much of each, but you’re approaching it from two radically different perspectives.”

One involves making a chip that is a superset of something a company has already created. A second involves piecing it together with components the company can acquire. “Or we can try to piece it together with stuff that you have or you think you can get,” Harding said. “Let’s make a chip that is packaged or a device is good enough and get that to your customers in six months instead of three years and the NRE is $100,000 instead of $6 million. If it really takes off, then we’ll go and make the ASIC and we’ll make that single, advanced node part. If you think about the need to have a derivative, there are really two vectors to go down. One is the die-level, advanced-packaging approach. The second is to simply modify the RTL and re-tape out a version of the chip which is kind of ‘close enough.’”

A third option, of course, is to never make a chip and simply go to an FPGA.

Outsourcing grows, but not because of cost
No matter which approach is used, outsourced teams play larger roles than in the past. “A lot of global companies have that mantra of you build one design in one location and then you ship it somewhere else for derivatives,” said Michal Siwinski, group director of product marketing in the system and software realization group at Cadence. “I’m seeing at least in the leading companies something a little bit different. The geo teams are not just being treated as a cost reduction. Rather, due to the sheer complexity of what it takes to build these massive SoC platforms, you basically have these globalized teams that might take a lead on a specific derivative.”

In general, the big savings that made headlines a decade agp by outsourcing to lower-cost labor areas are no longer an option.

“Due to the complexity of re-integration, I’m not seeing that so much now,” Siwinski said. “A whole product line with its derivatives might be led by one geography versus the other, but in general the complexity of doing that derivative and the time and cost are at this point so prohibitive on their own. If you consider that a new design is $150 million, and the derivative might be $100 million, that’s still not cheap. So it’s not about notions of having lower cost to the derivatives. Rather it’s utilizing a global workforce where a lot of that expertise needs to be built in all the geographies.”

Architectural decisions drive derivatives
With all of this complexity, there is a lot more up-front work required to define what the platform is and what new market segments it can serve, in addition to the main business unit’s market. “There’s more coordination within the corporation and more cooks in the kitchen up front,” said Kurt Shuler, vice president of marketing at Arteris. “That takes a long time and there’s a lot of coordination of the different groups, because what happens is when that platform goes from one business unit to another business unit, the IP that that second business unit uses may be totally different than what the guys who created the platform for.”

Jon McDonald, a technical marketer at Mentor Graphics noted, “When you think about outsourcing, it all comes back to understanding what needs to be done. The traditional approach when people just started RTL design was that it was easy when a group is all in one location. If you have a design group and they’re all together, they have meetings daily or weekly. Everybody is talking and you communicate a lot of things informally. When you go to outsource something you’ve got to have a contract. And it’s not just a business contract. There’s got to be a development contract. If that development contract is not very specific and very rigorous, there are opportunities for miscommunication, there are opportunities for something to be delivered that doesn’t satisfy the need.”

To combat this, in many situations the delivery contract is an executable transaction level model, which is completely unambiguous and allows each party to say, “This is what I need: this is the performance I need. You need to deliver a subsystem or part or whatever it is that does exactly what this does with this performance and this architecture,” he continued. “By putting a little bit more into the upfront specification/the upfront architecture, if you have an executable model for the upfront architecture and a prime [mil/aero contractor] hands that to a subcontractor, it makes the process so much easier because they know what it needs to do.”

By Ann Steffora Mutschler
From a planning perspective, creating derivative chips seems a straightforward task, but the process is much more complex than simply replacing or adding a peripheral—it starts with identifying the right team of engineers to perform that process.

“One of the needs in the market is somebody to have vertical expertise to do derivative design and yet be cost-effective,” observed Naveed Sherwani, co-founder, president and CEO of Open-Silicon. “Then, depending upon the vertical markets, you need to have many, many such derivative teams. A derivative team that can do router designs and switch fabric kinds of designs is not the one that can do a home gateway and is not the one that can do a WiFi chip and not the one which can do something else. You can pick your number—you can call it 15 or 30 verticals—and while there is some commonality between them, the front end of this may not be as common,”

As such, derivative teams must be very good at looking at somebody else’s design and making changes to that design. Specifically, the derivative team must be able to quickly pick up the architecture of the chip and understand the changes requested.

“Sometimes people say it is a derivative, but really it’s a brand new chip,” he pointed out. “Other times it is a true derivative—one that does not touch or alter the architecture of the chip in any significant way, does not change the data flow of the chip in any significant way, and which also doesn’t require you to re-time the whole circuit. As long as it is removing some IP, changing the number of ports, adding some functionality, that doesn’t change the architecture and the dataflow of the chip. Those are true derivatives.”

Another challenge that derivative teams face concerns how much data knowledge can be captured from the original team and how much of the original team is available to consult with the derivative team. In some cases the original team is very accessible, which makes it much easier. In other cases it is not.

“If the design team doing the derivative wasn’t involved in the original design, they do not necessarily understand the details of the formula that made that chip work (the so-called recipe),” said Mike Gianfagna, vice president of marketing at Atrenta. “That includes things like difficult-to-route areas, timing constraints, false paths, and placement restrictions for performance-sensitive digital blocks or analog modules. So you need a solid methodology for the original design that contemplates the outsourcing of the derivative. If you approach it that way, you can capture all the implementation recipe details as meta-data for the design which can then be part of the handoff. Capturing this meta data starts at the architectural level. This approach helps a lot.”

Further, truly understanding market needs and demands is critical. Drew Wingard, CTO of Sonics, said he has observed lots of people struggling to understanding that some of the interesting markets for SoCs—mobile phones, TVs, set-top boxes, tablets, automotive infotainment and telematics—change really fast. “So the idea that you’ve got the right smarts in your platform so that you can cover a couple of years’ worth of derivatives without changing any of your base assumptions has gotten increasingly difficult.”

Also, he noted that it is not uncommon to see a proposed derivative program get canceled in the first couple months. Once it gets to a certain critical mass, it seems more likely that it will continue through to the end. “We do see a lot of derivative-oriented design starts pop up and get started, and either the targeted end customer goes away or the speed with which the team is able to roll onto this derivative from that other program, which would have been the platform design or one of their other derivatives—happens a little too late. Suddenly that market window looks like it’s not as wide open as it was before.”

There may even be a loss of competitive capability when doing derivatives. Atrenta’s Gianfagna noted that doing a design from scratch will always yield the best fit for a given set of product requirements. Using the derivative approach will necessarily involve compromises, but as software becomes a larger and larger part of the system’s value, this downside decreases, he concluded.

By Ed Sperling
Mentor Graphics boosted the functionality of its PCB tools, adding 3D field solvers and thermal/power co-simulation analysis. This is particularly important for high-speed interconnects such as SerDes, which requires 3D modeling for signal integrity analysis.

Cadence roared back to life in Q4 with revenue of $308 million compared to $249 million in the same period in 2010, and net income of $11 million (or $46 million non-GAAP) compared to a loss of $37 million in 2010 (or $18 million non-GAAP). The company anticipates revenue will be in the range of $305 million to $315 million this quarter, with annual revenue in the range of $1.24 billion to $1.28 billion.

Sonics and Tensilica are working together to integrate Tensilica’s DSP processor interface with Sonics’ OCP-IP interface. The goal is to boost on-chip performance while making it easier to integrate IP. These kinds of deals are helpful in getting SoCs to market more quickly. Sonics also issued its formal response to rival Arteris’ countersuit.

By Ed Sperling
In what is turning into a legal war over network on chip technology, Arteris filed a counter complaint against Sonics for patent infringement.

Arteris charges that Sonics’ new SonicsGN infringes on two of its patents. It also denied that it has infringed on any of Sonics patents, which Sonics claimed in the lawsuit it filed in November against Artertis lawsuit against Arteris. Arteris is seeking damages and “equitable relief” from Sonics.

Sonics declined to comment.

Historically, patent infringement cases in the technology sector have started when markets are either heating up or when they are in steep decline. In EDA, for example, the majority of legal battles were fought when the industry was in high growth and acquisition mode. In the PC era, the famous battles between Apple and Microsoft were initiated early in the boom cycle.

NoC technology is still in its nascent stage, but it is gaining in popularity at advanced process nodes because of the enormous quantity of IP and the ability to add flexibility into a design on a variety of fronts, including power management.

By Ed Sperling
Fabs and foundries frequently have been the savior of flawed designs, fixing problems such as power and performance, identifying design issues and often developing solutions to those problems.

Over the next couple of process nodes, and in stacked die that will span multiple processes, there will be far fewer saves coming from the back end. Double and triple patterning, stress effects, new materials and the laws of physics are forcing a change in direction. In fact, for the first time design teams will have to make up for a slew of changes and challenges on the manufacturing and packaging side, employing new methodologies, new tools and deeper levels of expertise.

In a keynote speech at the SEMI Industry Strategy Symposium last week, Applied Materials chairman and CEO Mike Splinter sounded the alarm over the changes ahead. “Change is accelerating,” said Splinter. “Compared with the last 15 years, the next five years will have more changes and more inflection points. And it’s not just about complexity. It’s happening at the foundational level of how an IC is made.”

He’s not alone in that assessment. Bernie Meyerson, an IBM fellow, said CMOS is now in “the end game.” While CMOS certainly isn’t going away, there are physical limits for what can be done to extend it. That has spawned extensive research into alternative materials such as silicon on insulator and graphene, new elements for insulation, as well as new structures such as FinFETs and carbon nanotube FETs.

So what does this mean for design at advanced nodes? Lots more work on design for manufacturability, more complexity in achieving the same kinds of boosts in performance and energy efficiency that were taken for granted at older nodes, and much more up-front checking of just about everything.

“From 40nm to 28nm to 20nm, the number of checks for physical verification will grow by leaps and bounds,” said Michael White, director of product marketing for Calibre. “There are almost 1,000 more DRC checks from 40nm to 28nm between early production and volume production. We are also capturing additional context-dependent yield detractors. For example, historically we have had spacing checks. Now we have spacing checks and we need to check all of the other geometries in the neighborhood, including lithography and fill issues. Those are extra constraints.”

Lithography used to be something design teams never had to consider. But the delay in EUV will require double patterning at 22/20nm and potentially even triple patterning of at least some portions of the chip at 14nm. This becomes particularly challenging for design teams, because one of the approaches under serious consideration is something called spacer-assisted double patterning. In simple terms, a polygon design may look nothing like what’s on the mask using SAPD. This is akin to driving a car in reverse using the rearview mirror where nothing that appears in the mirror resembles the road.

Stacking effects
One solution to these issues is stacking of die, whether in 2.5D or 3D configurations. The so-called “More Than Moore” approach bundles technologies together at nodes that make sense for a particular function, rather than trying to fit everything into the most advanced process. So while the logic or memory may be created at 22nm or 14nm, for example, analog may be developed at 130nm.

This all makes sense in theory, but it also adds a new dimension of complexity that ripples back and forth between the design and the manufacturing worlds. It also exposes the entire supply chain into the design process, because problems detected anywhere along the chain can affect multiple other areas—and it’s possible that no single segment can solve them alone.

“Over the next three to five years chips will go vertical,” said Naveed Sherwani, CEO of Open-Silicon. “The question is how we are going to put together 3D ICs and what will go into them. There is a lot that needs to be done in this area.”

Sherwani contends that tools and methodologies should make it easier and quicker to do derivative designs. That’s the goal, and at least part of the solution involves companies learning to use the tools they have more effectively, and to apply some discipline to their methodologies. It’s easy to get blinded by the number of permutations and choices from the growing complexity.

“As process geometries continue to get smaller and the amount of IP used increases, the complexity of the design process becomes a major issue, which puts pressure on the entire development team from a coordination and communication standpoint,” said Simon Butler, CEO of Methodics “Also, with software elements and power constants, which are really just other types of IP, added to the already very complex mix of things, design teams need better ways to manage the entire SoC development process and synchronize all the moving parts. Internal design organizations already struggle with managing remote design teams. Now, with a disaggregated design chain consisting of separate companies, the need for real-time collaboration and managed data exchange is critical.”

That sentiment is echoed across the industry. Frank Schirrmeister, senior director for the Cadence System Development Suite, said that in principal tools allow engineers to model almost everything they need. “This isn’t a tool problem. It’s a discipline problem. But the other side of this is that in 1993 logic synthesis was pretty simple. Twelve years later, the whole process is not longer understandable by any engineer.”

Margin call
One of the most effective ways to deal with unknowns in the past is guard-banding—the process of building extra safeguards into ICs. That worked until about 65nm, but at advanced nodes it can cause performance degradations or drain batteries more quickly, or both.

“The guard band for synthesis is a smaller percentage at 28nm and it’s even smaller at 20nm,” said Jack Browne, senior vice president of sales and marketing at Sonics. “So you’ve got to be able to interoperate with the right guys. We’re all trying to manage a horrible amount of complexity and simplify it. The problem is there is too much that’s new and not enough experience points so that people can make the safe choices. There are significant unknowns on everyone’s road map.”

One potential solution—and one that’s being considered by a number of large chip and IP companies—is to harden everything into pre-qualified, pre-verified subsystems. While this limits the number of permutations, it does take some of the risk out of using those blocks. But too many hardened subsystems also can limit the ability of companies to differentiate their designs. And while that works well at a company like Apple, it does not work so well at a chip company trying to sell technology to Apple’s competitors.

“With subsystems you’ve closed the black box and given up the chance to turn some of the dials,” Browne said. “We’re seeing this with the TI OMAP team, which has accumulated a significant number of libraries and with Broadcom. And Toshiba has created video and RF subsystems.”

Caution ahead
All of these issues have raised questions about what needs to be fixed in the design flow, what needs to be extended, and how this will unfold over time. The reality is that changes may be slow because there is serious uncertainty about exactly what problems will erupt, where and when.

“There’s always a risk of getting too far ahead with the tools,” said Steve Smith, senior director of platform marketing at Synopsys. “We will add capabilities to current tools to make them 3D aware, but the goal is to enable engineers to do what they do best. We’re already dealing with multicorner, multimode design, and 3D will be another dimension. We might have coupling effects and we certainly will have a challenge with temperature. But most of the processes are familiar, and changing things in a working flow is always risky.”

By Ed Sperling
Just in time for the holidays. Cadence’s Tom Anderson finds some real-world assertions, including some embarrassing typos that can change the meaning—and value—of products. Details, details. Santa, you delivered the wrong present to the wrong house on the wrong day.

Mentor’s Jay Gorajia digs into the guidelines for production planning and scheduling. There’s a lot of really good information here. Take notes.

Synopsys’ Hannah Watanabe pulls together the best of the company’s recent Interoperability Forum, which featured speakers from ST, ARM, Accellera and some private venture capitalists. There are a lot of road maps to study. So little time, such small features.

Cadence’s Richard Goering reports on a panel about how power minimization and optimization dominate front-end design. That seems to be the consensus everywhere, and the problem isn’t going away.

Semico’s Joanne Itow attends Semicon Japan and finds lots of optimism for the future, particularly in the used equipment market. There’s a lot of good insight about the intricacies of this market, including some unexpected tidbits.

DeepChip’s John Cooley surveys the market about concerns over Synopsys’ acquisition of Magma. The biggest negatives involve less competition. But why are the 10% who are in favor of this move and the 9% who are neutral so quiet?

Mentor’s Colin Walls does take two on RTOS test harnesses, and where and when to use them. Given the focus on software debugging and test, this is a very good topic.

Synopsys’ Doug Amos looks at deadlines and what can go wrong. Sorry, Christmas has been canceled this year.

Cadence’s Jack Erickson points to a high-level synthesis discussion by Freescale engineers involving a C-to-silicon FPGA prototype based on control logic rather than dominated by the datapath. This is a twist.

And in case you missed the most recent issue of the System-Level Design newsletter, here are some standout blogs:

–Mentor’s Jon McDonald looks at the tradeoffs between AT and LT.

–Cadence’s Frank Schirrmeister brings good tidings and not-so-good tidings for software developers.

– Synopsys’ Achim Nohl talks about ways to improved battery life with virtual prototypes.

–Sonics’ Frank Ferro zeroes in on what makes a product successful. Hint: It’s more than just the technology.

–Arteris’ Kurt Shuler takes a children’s story and applies it to the semiconductor IP industry.

–Atrenta’s Mike Gianfagna makes some predictions about how the EDA industry will change in 2012. If they come true, there will be more dropping next New Year’s Eve than a ball.

–Methodics’ Simon Butler tracks the challenges in design and IP management across the globe and finds similar problems everywhere.

By Ed Sperling
Mentor Graphics introduced an integrated component-to-system thermal characterization and analysis solution that combines hardware test with its FloTherm software. This is a particularly interesting more for the LED and IC packaging arenas, given the focus on leakage and heat.

Cadence won a deal with Panasonic for its Palladium XP platform, which combines simulation, acceleration and emulation. The tools will be used in a variety of digital consumer electronics.

HiSilicon has licensed eSilicon’s 40nm ternary content-addressable memory macros for its networking chips.

Blu-Wireless has licensed Sonics’ on-chip communications IP for its wireless communications processors aimed at the unlicensed 60 GHz market. Blu-Wireless will use the IP for a new generation of multi-gigabit communications for consumer electronics.

Synopsys claimed a share of the victory in GlobalFoundries first complex 20nm tapeout, complete with double patterning. A number of Synopsys tools were used to achieve silicon success.

By Ed Sperling
Cadence’s Jack Erickson adds another angle to make vs. buy: re-use. It’s still make vs. buy, but with the extra dimension of time.

Mentor’s Colin Walls wants to know what the plural of Linux is? There are, after all, multiple distributions of the OS. But his quandary stems from the assumption that it’s a noun. Maybe it’s an adjective, as in, “Linux versions” or “Linux OS.”

Synopsys’ Eric Huang compares the user habits of people who buy the iPad vs. the Kindle Fire. The good news is the TSA hasn’t stopped anyone for using a device with the word “Fire” on it.

DeepChip’s John Cooley reports a potential customer is looking for details about the usefulness of Apache and Atrenta tools. Opportunity knocks.

Cadence’s Richard Goering calls attention to an ARM TechCon paper about using virtual platforms for multicore software development. Given complexity and time-to-market issues, there may not be a choice.

Mentor’s Robin Bornoff digs into the wonders of cooling systems for a desktop PC. It’s a lot of work for something that could have been designed differently.

Synopsys’ Tom De Schutter looks into recycling and re-using of TLM models, which is possible as long as you can meet the requirements.

Semico’s Jim Feldhan predicts that plug-in electric vehicles will be in high demand by consumers. We’d like to add to that an increased demand for three-car garages and higher insurance costs.

Cadence’s Frank Schirrmeister questions whether software development will cause another industrial revolution. At the very least, it will have a big effect on current industry.

And in case you missed the latest System-Level Design newsletter, here are some standout blogs from that issue: http://chipdesignmag.com/sld/wp-content/newsletter/2011/11/

–Mentor’s Jon McDonald comes up with a revelation about ESL over dinner.

– Synopsys’ Achim Nohl looks at software bugs and how to stop them from wreaking havoc on a design.

–Cadence’s Frank Schirrmeister focuses on the extensibility of TLMs and why it’s so crucial.

–Atrenta’s Tiffany Sparks exposes the stressful reality behind some over-used buzzwords.

–Arteris’ Kurt Shuler looks at China’s push into communications infrastructure and energy efficiency and the resulting market opportunities.

–Sonics John Bainbridge examines the concept of decoupling to improve performance and power management.

–And Methodics’ Simon Butler takes a look at an SoC-oriented design data management system and how to avoid lots of problems.

By Ed Sperling
Hitting market windows with IC designs has always been a struggle, but the race to the finish line is becoming more critical—and much more difficult. The reason: Market windows themselves are shrinking.

Products that used to stick around for years may now only last for months, replaced by newer versions that offer either better performance or lower power. In many cases, particularly for the hottest consumer markets that drive the highest volumes, there isn’t even time for competing on cost with derivative chips. The so-called long tail of design now looks significantly shorter, overtaken by a quick ramp up to the next SoC.

This raises a slew of new concerns among chip designers about which market opportunities are worth the risk, at which process node, and how to get there quickest with the least amount of risk. It also raises issues among tools developers about how many customers there will be for tools if the largest customers skip process nodes. And it raises the stakes across the board for making bad decisions, because they can no longer be amortized across dozens of derivative designs.

Changing market dynamics
What’s behind much of this is a shift in consumer buying habits. It’s not that consumers necessarily buy more devices, but they buy them much more quickly after the release date. The iPhone 4S was a classic example. Within four days of its introduction sales had topped 1 million units, something that took years for previous product lines.

“We used to be able to use a shotgun approach,” said Mike Gianfagna, vice president of marketing at Atrenta. “Now it’s more like a precision rifle shot. And if you don’t hit it just right, the market is gone.”

Time-to-market has escalated from important to critical. But for most companies that also involves a disaggegrated supply chain, which tends to slow down the design process more compared with IDMs such as Intel and Samsung, which have regular communications between fab, design teams and debug operations.

“What we’re heading toward is virtual re-aggregation,” said Gianfagna. “But that’s going to require speed and perfection, a lot of standards, and changes throughout design.”

It also changes the rules about how companies go to market with new ideas and technology.

“Traditionally, people went into market to test the waters,” said Neil Hand, group marketing director for Cadence’s SoC Realization Group. “The way things are now, you have to get it right. And if you’re successful, you have to quickly turn out new products. Product planning is important, but you also have to build in flexibility.”

Multi-patterning, packaging, and physics
It also requires some techniques and approaches that were not even considered in the design process until very recently. Sequential flows are now concurrent, with manufacturing now an important element of the early design phase. One area that is a particular trouble spot involves lithography, where EUV has been considered the best hope for etching extremely thin lines. EUV was expected to be commercially viable years ago. It’s still in the development stage, which is why the industry is heading to double patterning at 22/20nm. And that slows down the whole process significantly.

“Double patterning means you’re splitting a single mask up into two masks,” said Wally Rhines, chairman and CEO of Mentor Graphics. “And at 14nm we’re still uncertain whether the solution will be EUV or triple patterning. It could be either one. It depends on the development schedule of EUV. We may have a node that starts out without EUV and ends up with EUV. From the perspective of power and throughput it’s still a long way from production-worthy. The backup is triple patterning. It’s undesirable from a cost point of view.”

For an industry that has banked heavily on proven techniques and processes, this is a remarkably untested future with a very uncertain throughput and cost structure, filled with a variety of other risk factors.

Stacking of die will complicate that further, because understanding the stress impact of TSVs remains fuzzy, at best. Interposers are slightly better tested, particularly more advanced versions that potentially use new materials. In addition, wide I/O standards are still being developed, and so are ways of connecting all the pieces together, testing and debugging them, and figuring out how to deal with heat dissipation.

There’s also a question about what will get valued most in this new approach—and where the development dollars will go for tools. That also can affect time to market, because if the tools aren’t updated or integrated companies will have to do that work themselves—something they’ve done in areas such as rapid prototyping until recently, when commercially integrated solutions became available.

“It’s a little like the automotive or aircraft industry,” said Rhines. “The people who put the pieces together are system integrators. They deal with multiple die. They deal with software. They deal with interconnects. They are system designers. Then the individual die, an the individual IP, are component suppliers to each other. Today that IP serves as a barrier, but it will commoditize. System integrators get paid more than component suppliers, and components become commodities.”

Unbundling and future changes
One way to facilitate these kinds of changes is by unbundling the individual pieces in an SoC.

“There are really relatively few new hardware blocks being added to new designs,” said Drew Wingard, chief technology officer at Sonics. “The exception is the continued improvement in processor cores from ARM or graphics engines. Mostly it’s continued pressure on integration, and we believe strongly the only way to deal with this effectively is to isolate the components.”

He noted that interdependencies make it difficult to advance one component in a package without also making changes to another component. That has proven particularly problematic for mixed signal blocks, where shrinkage of digital features has forced similar but extremely painful shrinkage of analog processes. By separating those worlds, progress can be made in both portions of the block when it makes sense.

“If you can decouple the verification you can divide and conquer,” said Wingard. “That allows you to do verification at the subsystem level and re-use testbench code. A lot more companies also are thinking about designs in a platform-based way. A platform is a set of decisions you’ve made, and then you abstract up and down.”

Platforms have been talked about for years as a future direction. Intel, which used to churn out dozens of different chips for various PC markets, adopted a platform approach with the introduction of its Core architecture. ARM has done the same with its Cortex line. And while SoC developers have had a much more difficult time with this approach, many of components within those chips are developed using a platform approach.

But every decision has ramifications in an SoC. While it’s okay to unbundle the components, everything is tied to everything else in ways that extend well beyond the chip.

“When you develop a chip in the wireless space you have to make sure you’re in sync with the carriers, the handset makers, and the whole value chain,” said Kurt Shuler, director of marketing at Arteris. “This becomes a problem when you start shrinking the design time. It used to take 18 to 24 months to gather requirements to put a chip out there. Now the best designs take 9 to 12 months, and the most advanced companies are pushing to get that down to 6 to 9 months. The only way to do that is with a platform approach where you have one hardware and software platform and you can re-use the hardware and software investment.”

Re-use is driving a significant portion of Synopsys’ business these days. It’s no longer just IP blocks that are being sold. It’s IP plus software, and often in conjunction with services.

“We absolutely believe the next major evolution is subsystems of larger integrated blocks,” said John Koeter, vice president of marketing for Synopsys’ Solutions Group. Those subsystems increasingly are customized for very specific markets, as well, to both reduce risk and decrease the time it takes to get an SoC out the door. “These are very market-specific, he said. In the audio area an MP3 will have codecs that are different from a home entertainment system. We’re also seeing an increased willingness among companies to outsource. It’s not just small companies, either. It’s also the big tier-one companies that are questioning whether a USB is differentiating their chip.”

The push for more standards
Platforms also require standards, and there is mounting pressure on all of the standards bodies to ramp up the number and quality of standards—and to avoid dual standards such as UPF and CPF. But hidden in all of this also is a recognition that vendors will have to pick their battles. They can’t compete on all fronts and still have progress in standards.

“Standards are created largely around efficient ways of exchanging data in design and manufacturing,” said Steve Schulz, president and CEO of Si2. “If you had to re-do models for every foundry chip that would quickly get out of scale. Standards allow companies to get to market faster.”

That becomes more difficult in stacked, however, which involves more companies from across the supply chain. The promise of stacked die is re-usability, possibly with entire logic or analog “platforms” as part of the stack.

“Everything about 3D is a supply-chain view,” said Schulz. “You need to understand the whole landscape to do anything in 3D. How do you describe hot spots on a die? What’s the basic connectivity between the package and the pins? How are you going to develop the interposers? If you create process design kits will they need to understand the process impact of TSVs? And when is all of this going to happen? We’re not sure about the time frame.”

Conclusions
Dealing with time-to-market pressures has always been a concern, but rarely did being late to market mean missing out on the market entirely. That reality is changing, however, putting pressure on teams to figure out ways to ensure quicker turnarounds with better results.

Software, in particular, is a problem that needs to be dealt with effectively. As Cadence’s Hand says, “We need to bring down design and manufacturing costs, but software is still the killer.”

To some extent this is likely to force some hiring in the industry. Companies never replenished their ranks after laying off engineers in 2008. It also will require more tools, because automation is much faster in the hands of trained engineers than spreadsheets and trial and error. And it will require renewed cooperation to push through standards in areas where companies can agree it’s not necessary to compete—or where competition may slow down entire markets.

These changes also are likely to reshape the IC industry in ways we cannot even begin to comprehend at the moment. At the base of all of this is a fundamental and global shift that time to market will no longer be determined from the bottom up. It will be driven from the top down—by the consumers of the technology who are willing to spend quickly and decisively rather than mulling purchases for months or years. The winners will be those that can figure out a way to meet that need—and the losers will be either quickly absorbed or, worse, forgotten.