By Ed Sperling
Synopsys rolled out a suite of integrated tools specifically for both 2.5D and 3D stacked die, setting the stage for a huge change in how ICs are designed and packaged over the next decade. The company also introduced its audio subsystem, complete with IP, tools, a processor and audio codecs. In addition, Synopsys teamed up with Altera and TSMC for silicon-accurate parasitic modeling and extraction at 28nm, and it created parasitic extraction models for double patterning with an industry consortium.

Mentor Graphics added support for the Yocto Project, allowing its embedded Linux middleware to support the various flavors of Linux development without putting the burden on developers. This is an important step forward in the commercialization of Linux, where development has been piecemeal in keeping with its university/scientific roots. Mentor’s tools allow developers to build embedded systems without worrying about which hardware to use. Mentor Graphics also teamed up with Triad Semiconductor to create a low-cost, mixed-signal tool the companies claim can slash costs and development time for mixed-signal ICs. Triad is based in Winston-Salem, N.C.

Cadence announced verification IP support for two new enterprise-level cloud storage standards, NVM Express and 12GB/second SAS (serial-attached SCSI).

By Ann Steffora Mutschler
Engineering teams across the globe continue to pound the process geometry treadmill to stay on the curve of Dr. Moore to achieve better speed or lower power or smaller die—and it all adds up to increased complexity in the design and packaging. However, with advanced forms of die stacking such as package-on-package, silicon-in-package, 2.5D silicon interposer technology and other techniques, engineering teams now have more degrees of freedom around how chips are constructed.

A significant consideration in moving from one process generation to the next is that there are many IP functions that must migrate. “Sometimes it’s too expensive to port it from one generation to the other and you may not need it as far as the speed or as far as the power,” noted Shafy Eltoukhy, vice president of manufacturing operations for Open-Silicon.

This is where advanced die stacking comes into play. The engineering team may consider going to 28nm for one particular aspect of the function—for example, to get a better speed in the ARM processor—while there are a lot of other interfaces for a particular die that may not have to be in that advanced process node. A USB 2.0 or 3.0 does not have to be in 28nm to achieve the requirements—it could be in 90nm or 40nm, he said.

“The whole notion of re-using IP is common, though something not as commonly discussed is the reusability of die. What we’ve been seeing a fair amount of is companies saying, ‘I’m going to use advanced packaging techniques that are available today and I’m going to take this older generation die that I’ve got sitting on the shelf. And I’m going to make a much smaller new chip to complete it or extend it or interface to it. And I’m going to put that all into a multi-chip module, or advanced packaging structure, and circle back and use a lot of the IP that is in actual hardware form and make that available.’ It’s not mainstream, but reusing IP 15 years ago wasn’t mainstream either,” said Jack Harding, president and CEO of eSilicon.

Engineering teams tend to have a certain function they really want to squeeze and go to the next generation, but there are a lot of other functions in the design that don’t have to be in the latest generation, Eltoukhy observed. In advanced SoCs, customers are paying first and foremost for the IP development. “You are paying more dollar-wise per silicon area for a function that does not have to be in 28nm.”

What process node makes sense
Naturally this leads to a discussion about not bringing every single function into the next generation, especially because some analog and RF functions do not scale very well. So why not stay in the previous generation and partition the design in order to leverage older technology where available and not re-invent it?

“What I have to do instead is some kind of interface between this technology and the new technology. I put only the function that I want in the technology that can handle it and leave the other somewhere else,” he noted.

The question then becomes how to connect these together. “You certainly can connect them on the package level, which people used to call MCM (multi-chip module). You can actually get multiple die and bolt them in the substrate of the package and connect them. But the package technology has been way, way behind compared to the silicon technology, and you may end up with much higher power and slow interfaces and so on,” Eltoukhy explained. This has led to the development of silicon interposer technology in order to replace the substrate interconnect or the package interconnect, which is commonly known as 2.5D stacking.

Essentially, silicon interposer technology connects one die to another instead of connecting to a package, thereby reducing power and improving speed. Xilinx already has made its version of 2.5D-stacked technology available with certain product families.

Another use of 2.5D would be in a processor design that needs to talk to a DRAM, he continued. “Most people have a DDR interface and you go through the board to interface with the memory. But this approach is slow and large. Instead of buying a DRAM package from a DRAM vendor, we ask the vendor to sell us a known good die, which can be attached with processors on an interposer so you don’t have to go outside the chip. The DRAM can talk to the processor right away and the form factor will be much, much smaller. So there are multiple applications for that interposer—mixing the process nodes so that you can reduce the cost and so on, and improving the yield or bringing up some known good die from the DRAM to your die.”

“The application processors, which are really only delivered with package-on-package memory, end up with a very easy knob in that system—they can pile on different amounts of DRAM. To them it’s almost the same design and it is the same software. A couple of bits different in the software and suddenly they’ve got a new derivative part,” said Drew Wingard, CTO of Sonics.

“In many cases the die itself has more package attachment or wire bonding sites than the package may have pins, so you may take the same die and put it into a different package with different amounts of I/O resources available, and then sell those chips—even though they are the same fundamental chip design—at different price points. That’s been going on for a long, long time but with some of the more advanced packaging technologies, there are new degrees of freedom there,” he added.

While sounding tantalizing, all of these options are still under development. Complicating widespread deployment are two factions in the industry at odds as to the right path forward. On one side are the semiconductor foundries, which would like to enable customers to use a transposer because, at the end of the day, they want to sell more dies to put on the interposer, Eltoukhy explained. “They say, ‘We can give you the interposer but you buy the dies from us and we can glue it together for you.’”

In another camp are packaging providers such as Amkor and ASE that fear losing business to the foundries and would also like to offer the interposer to their customers so they won’t go and do the interposer with their foundry. “These two camps are fighting now because it requires some investment from a capex point of view,” he added.

Managing complexity, saving dollars
In addition to dealing with complexity, advanced die stacking techniques can save big dollars, eSilicon’s Harding asserted. “You could measure it just in terms of NRE dollars, you could measure it in engineer years of work, you could measure it in terms of time to revenue. By any metric, going down the advanced-package, multi-die solution is better by two orders of magnitude than just actually making a new chip, and I would argue it’s probably better by one order of magnitude by just doing RTL modification, which still has high NRE and a lot of technical risk, albeit you have a product that is closer to being the final product. These decisions are classic risk-reward.”

By Ed Sperling
System-Level Design sat down to discuss electronic-system-level design with Stephen Bailey, director of emerging technologies for the design verification technology group at Mentor Graphics; Michael McNamara, vice president and general manager of Cadence’s System-Level Division; Ghislain Kaiser, CEO of DOCEA Power, and Shawn McCloud, vice president of marketing at Calypto. What follows are excerpts of that conversation.

SLD: As power becomes more of a consideration, both with more third-party IP and what is considered mainstream design moving down to 40nm and beyond, will the companies using ESL change?
Kaiser: It’s not a just question of power consumption. It’s power consumption and power techniques and implementation in software and hardware. The ideal flow will have at the system level some tools and methodology to analyze and estimate power very quickly, and then to have implementation down to the silicon. Unfortunately that’s not possible today. Nevertheless, there is interest to explore power and implement power using a refinement methodology for meeting the power budget in a design flow and making decisions earlier. One part is to implement power reduction techniques and to keep consistency between the system-level definition and implementation. That’s the first phase of UPF/CPF. We need to move this standard to a higher level. For the software part, we need to make sure that is well captured at the system level and implemented in the software development phase. The main system level goal for power is to define the critical use cases for power and the most efficient implementation. We have to look at the ‘V’ cycle process flow. The system level is in front of the validation of the system. What is missing today is, when customers get back their silicon how is it possible to validate the power consumption? They run the software, measure the power consumption, and get maybe 500 milliwatts. Is it correct? Do they have some bugs? They’re working blind. The information should come from the system-level design.
McCloud: There’s a reason why the power of the actual subsystem on the chip is very critical. It’s not just a question of battery life. It’s also thermal integrity and power and supply integrity. As we pass 45nm it’s very difficult to scale your supply voltage to reduce power. If you don’t do anything, you’ll see a chip that has four times the number of transistors and four times the amount of power in the same die space. That would be impossible.
McNamara: That was the death of a processor at one large company. There was too much power density.
McCloud: It becomes critical from a thermal perspective. Your chip is going to burn up or you’re going to have supply dropouts and the chip will ultimately fail.
McNamara: It’s a matter of getting the power there and the heat out. Even if the chip survives, you don’t want to burn the hand of the person holding the phone.

SLD: So with growth of third-party IP, does it change system-level design?
Bailey: The way I see the market going, there already are 2.5D devices where there are hardened 2.5D platforms. Xilinx, Altera and Microsemi have products in this area. When you look at the economics involved, this opens the door for a lot more companies to get involved in electronic-system-level design than before because they don’t have to hire and spend millions of dollars just to get the chip out, let alone any of the software. Even if it costs them $25,000 to $50,000 for leading-edge chips at the latest process nodes, that’s nothing compared to the millions of dollars it would have cost them to engineer that up front. They can focus on a small amount of differentiating logic or just software. It’s a much lower cost for NRE, so a lot more companies can afford to be startups and try to do something innovative. They can take these chips into consumer markets and new market-specific applications.
McNamara: The Zynq platform from Xilinx is one of them. We’re working with a company that will use those in scanners for inventory. You only need a thousand of these. But now you can build a fully customized device with volume 1,000 for no NRE. You’re basically buying an FPGA SoC. Now you can do system-level design with that and determine what goes into software, what goes into the FPGA, and what goes into the peripherals.
Bailey: You might have some custom peripherals on there and maybe an accelerator block.
McCloud: We see a similar trend between early production in FPGAs and volume production in ASICs in Japan. They’re making very high-end TVs in low volume. The consumer market is all about time-to-market, which may be a six-month development cycle. ASICs can take a long time, so they’re doing early production with FPGAs. HLS makes this possible. It’s the same C/C++/ESL model being used to go to the FPGA for early production and then re-targeted for an ASIC.

SLD: What standards are necessary in the short-term to make all this work?
McNamara: With transaction-level modeling, we need version 3.0. One of the big missing pieces is the separation of communication from computation. If there’s a standard way of representing a communication port that I can model, that would be useful. The virtual platform can be just a pass-through, with no need to model it. When it’s being synthesized to logic, you’re using the OCP bus or AXI or Amba 3. There are different choices for the communication. That should be something you just swap in or out for doing the calculations. You want HLS that can work with a communication model and a computation model as an ensemble, that has all the details you need of the protocol. That’s important for the next level. When you go from the transaction level to RTL, you have to get to signals and wires. You don’t need to model the signals at the transaction level. It’s just a block of data. That’s one standard that’s need. The other thing that’s needed is a way to extract power from the lowest level and represent it at the system level. There are two aspects to that. One is, what is the cost of an ‘and’ operation on an A9? What is the cost of a divide operation? You can do some software profiling to get the cost of power in the processor cores. Then there’s the other bunch of logic that is an MPEG-3 or MPEG-4 decoder. How do you represent the power in a way you can trade off designs in a way that is more than ‘A’ is better than ‘B’? We have to improve on 30% accuracy. We also have to pull in software. We’ve talked about software as a user of power. What about software shutoff of a radio? And there’s some other software that’s not aware it’s shutoff and is dependent on data from this radio. There’s a correctness modeling that needs to be there.
Kaiser: The power needs standardization at the system level to capture the power behavior and the power interface with the software and the hardware. You need to keep consistency from the system level to implementation, taking into account exploration and software and hardware implementation. Those are the three topics that need to be considered in hardware standardization.
McCloud: TLM 2.0 is certainly in the right direction, but it does need further standardization around power policies and performance policies. We need a better way to standardize moving power up to the ESL level. UPF and CPF have to move up to the ESL level, as well. There needs to be some progress in that direction. And we need to do a better job of connecting these point tools in a flow, even if that means going across companies. We have great point tools. How do we bring those together to create an overall ESL solution?
Bailey: I chaired the UPF committee through the first couple of revisions. UPF definitely could be used at the TLM level. In addition, there will be continued innovation and new bus fabrics on SoCs. GALs (generic array logic devices) will grow in use, and that will create new on-chip bus structures. There will be new interfaces external to the chip, as well. You’ll see more standardization pushing up into the software levels of these protocols so there is less to change in software stacks because the underlying hardware protocol will change. The other thing in standardization is that with the move up in abstraction, verification will move up in abstraction beyond that. You can’t have verification at the same level of abstraction as HLS or TLM. It has to move up further. You’ll see some standardization in verification, as well, beyond UVM and OVM. People need to know what to test, to make sure they’ve tested what they want to test, as well as being sure their results are correct. That’s what verification should be about, not writing testbench plumbing code.
McNamara: There could be a stage of having a testbench language for TLM, and there are efforts in UVM to address that, but the real leap forward is testing the hardware/software system. If I’m supplying IP, today that IP has a driver. Sometimes it’s fairly large. If you look at memory IP, there’s a lot of software that comes with it. How do you not just verify the hardware, but also the software to make sure there are not any deadlocks in these device drivers? And then you need to eliminate deadlocks between these devices and IP you’re buying from other people.
McCloud: One of the biggest challenges we hear about is unpredictability of systems. You’ve got RTL, software and you upload it on emulation That’s very late in the design process. You need to pull that forward and verify the software and hardware and all the pieces working together.
Kaiser: Anticipating issues is key to the system level. But being able to keep the flow consistent, and being able to provide information from the system level to implementation teams for power consumption to have guidelines and specifications earlier is a problem if your specification is frozen at the RTL level. Your planning is impacted. If you can freeze your specification earlier you can get the specification closure earlier. That’s a key benefit.

By Ann Steffora Mutschler
In an ideal world, all new SoC technologies would make the lives of design engineers easier. While this may be true of some techniques, it is not the case with one advanced memory interface technology on the horizon, Wide I/O.

There are claims that Wide I/O could reduce cache, but so far this is not widely understood. In fact, exactly how Wide I/O will be used, what the benefits will be and when it will become a mainstream technology are hazy at best

Marc Greenberg, director of marketing for Cadence’s SoC realization group believes Wide I/O will reduce cache but cautions that there is no one answer for that because every system is going to do it a little bit differently. “In some cases you might say some of the L2 or L3 cache could move into a Wide I/O device. That’s certainly a possibility. Or maybe not all of it, but perhaps some of it—maybe none of the L2 but all of the L3. It’s also possible that the Wide I/O becomes sort of an L4 cache to some other, even more distant memory; it becomes a new layer in the memory hierarchy,” he said.

Greenberg believes all of these options will likely be seen in different chips.

Cadence's Greenberg: No simple answers.

“The real thing about cache is that you want to keep small, fast memory close by, and then slower, larger memories farther away. Unless you have a super-fast memory off-chip, Wide I/O will not remove cache from on-chip. The fastest off-chip memory today is still much, much slower than on-chip SRAM, so you’ll always have cache on-chip as far as possible,” said Prasad Saggurti, product marketing manager and senior staff for embedded memory in Synopsys’ test and repair group. “As you need to go to larger sizes—if you go to L2 cache, even that tends to be on-chip. You could have a situation wherein instead of doing DRAM and using that as a L3 or so on being the main memory, you might have an intermediate that replaces DRAM or complements DRAM by having a Wide I/O to regular memory and then have this.”

Synopsys' Saggurti: Cache will always be on-chip.

In general, Wide I/O is seen as a way to take care of I/O speeds so instead of going to a DRAM through a high-speed serial interface, Wide I/O could be used to reduce latency.
Early adopters of Wide I/O have been in the mobile space for cell phones and tablets. In that case, the Wide I/O is replacing the main memory, observed Cadence’s Greenberg.

“There have been people hinting at not being able to stack enough DRAM on top of, perhaps, a tablet processor, so you might want to have another tier of RAM further out in memory. In that case, the Wide I/O becomes either an L3 or L4 to some even more distant memory.”

Steve Hamilton, applications architect at Sonics, stressed that stacking could theoretically maximize L2 and L3 caches, even though that is not likely any time soon. He said there are some people looking at using through-silicon vias to place a denser memory close to processors. A bigger cache can be placed in the same space, but there are a number of reasons—both physical and economic—why that does not yet make sense.

“This would require a custom memory chip to perfectly match the floorplan of the SoC,” said Hamilton. “Economics don’t support that. Managerially, you would then need to coordinate two custom chip developments to intercept at some point. That adds risk. Then there are restrictions on where the TSV columns could be placed on a die that we don’t fully understand yet. The dies expand and contract in operation due to heating. That may stress the connections or crack the die if it’s not engineered correctly. We don’t have enough experience yet to know those rules.”

Sonics' Hamilton: Unlikely to reduce cache.

It makes a lot more sense to start with a single common interface point, as this allows for mechanical expansion. By defining it as a physical standard, just as other interfaces have done, it allows independent manufacturers such as the DRAM and SoC vendors to do their own thing. The common standard also amortizes the development costs over a larger set of applications. So something like Wide I/O is a perfect starting point for TSV technology, he said.

But when it comes specifically to Wide I/O, Hamilton doesn’t believe the technology will reduce cache at all. “Wide I/O provides a wider (4-channels) interface to DRAM, but operates at a lower frequency than DDR3. Wide I/O also has some painful restrictions on page access rates. So the total bandwidth is only slightly improved. Worse, this is just I/O bandwidth. The actual access time to DRAMs (latency) is not changing at all. Caches are used to minimize read latency and increase memory bandwidth (for an access stream having locality). So as long as there is external DRAM of any type (with high latency) there will be caches.”

This is the most frustrating thing for SoC developers who need low latency, high bandwidth, and low power from DRAM, and not high density. Meanwhile, DRAM vendors keep marching down the path they understand—more density with each generation. They only reluctantly have moved to newer specs that increase I/O bandwidth. But these specs are increasingly hard to use. They rely, for example, on access in larger chunks than processors may need, while doing nothing to address latency.

“As long as the server guys—who need density—are the majority of demand there is not sufficient motivation for the DRAM vendors to optimize for what the mobile folks need,” Hamilton believes.

Interestingly, eDRAM does have the potential to reduce caching. “Processors generally use private L1 caches, and share L2 caches across small (2 to 4) clusters. eDRAM radically improves latency (and bandwidth, and power). So it becomes possible to consider eliminating or reducing L2 caching when eDRAM is used,” he noted.

By Cheryl Ajluni

At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs).

The concept of 3D stacking or integration technology is not new. In fact, 3D stacking of dies has been successfully demonstrated and is currently being commercially employed in some embedded domains (e.g., stacking DRAM memory on CPU cores). A recent 3D IC report from Yole Développement suggests that by 2012, the number of 3D IC-processed wafers could surpass 10 million units, driven in part by handset, wireless and computing applications. Given the intense interest and work going into developing 3D integration technology, this prediction seems just about right—assuming, of course, that a few challenges can first be met.

Exploring the third dimension

Very simply put, 3D integration consists of stacking integrated circuits and connecting them vertically so that they behave as a single device. A 3D chip is therefore just a stack of multiple device layers with direct vertical interconnects tunneling through them. So what’s the big deal about 3D integration?

Today’s semiconductor chips face extreme pressure to achieve increased performance, while reducing their size and accommodating lots of new functionality. When these factors coalesce in traditional 2D chips, longer interconnects result. In SoCs, longer interconnects translate into reduced speed and increased power consumption.

A key benefit of 3D integration is that it can reduce the length of interconnects. Additionally, it provides higher transistor density, faster interconnects and heterogeneous technology integration, with potentially lower power, cost and faster time-to-market. As Matt Nowak, director of engineering in the VLSI technology group of Qualcomm’s CDMA technology division, pointed out in a DAC 2008 presentation, the 3D approach “achieves extremely high densities, allowing us to use heterogeneous technologies and reduce form factor. The key is that it enables the use of new differentiating technologies to build new architectures that cannot be built in existing technologies.”

Eyeing recent developments

Up to this point, most efforts in 3D integration have focused on developing different fabrication techniques for stacking multiple device layers and forming the vertical interconnects. Much of the work has been done through collaborations with academia, industry organizations and government-sponsored laboratories around the world. One of the key technologies to come out of this research is a next-generation interconnect technology known as Through-Silicon Via (TSV). The TSV is a vertical electrical connection that passes completely through a silicon wafer or die to produce multilevel chips with an optimum combination of cost, functionality, performance, and power consumption. By using TSV technology, 3D ICs can pack greater functionality into a smaller footprint and realize shorter critical electrical paths, resulting in faster operation.

Some of the other developments to come out of ongoing 3D integration research were recently recognized at the Electronic Components and Technology Conference. Sandia National Laboratories presented details of its W TSV process, which is said to provide a suitably low-resistance metal with a coefficient of thermal expansion close to Si, a via fill that is conformal, and can be readily integrated into IC fabrication. IMEC introduced a novel process for die-to-wafer bonding (using Cu-Cu bonds) of its 3D SIC technology and a scalable TSV technology for 3D wafer-level packaging. Its TSV technology is designed for 3D structures where interconnects are fabricated after standard CMOS processing.

SEMATECH also is focusing its 3D research on TSV technology, particularly for implementation. The industry organization is actively working to bring together partners from across industry—chipmakers, equipment and materials suppliers, assembly and packaging service companies—to make 3D TSV suitable for high-volume manufacturing (Figure 1).

Figure 1. In contrast to the 2D-SoC or 3D System-in-Package, 3D TSVs offer a cost-effective way to achieve high density and performance, while also being able to integrate non-CMOS products with CMOS. The SEMATECH 3D project is based on cost modeling to assure products will be both manufacturable and affordable.

Help: tool support needed!

While ongoing research and development is absolutely critical to the success of 3D integration, perhaps one of the greatest challenges it faces is tool support in terms of design techniques and methodologies. Without it, engineers have virtually no efficient way to exploit the technology’s benefits. Tool support is especially critical when it comes to 3D integration because vertical stacking tends to increase thermal resistances, further exacerbating temperature-induced problems that can negatively affect system reliability, performance and leakage power. The use of 3D also will significantly complicate the typical design flow.

The key, of course, lies in creating a standardized design environment and methodology for physical design of 3D chips that could support a range of different tools. Having the tools integrated in one place would make it easier for designers to explore and make architectural decisions and then, to hand those decisions off to next stages in the design process.

3D IC integration is still in its infancy and, as a result, tools developed today for one specific application (e.g., stacked memory) may not be suitable for heterogeneous integration tomorrow. Nevertheless, there are some tools available now, with more in development. Some of these tools include:

3D PathFinding

Javelin Design Automation. 3D PathFinding provides a detailed 3D flow for accurate performance/power/cost estimates that can be used for rapid design exploration and optimization of 3D stacked ICs. Developed in collaboration with IMEC and Qualcomm, the solution extends Javelin’s existing PathFinding methodology and j360 Silicon PathFinder physical design prototype platform to support virtual chip design (Figure 2).

Figure 2. Javelin’s 3D PathFinding solution allows the designer to assess the impact of various 3D interconnect strategies throughout the IC design and fabrication process, in a matter of just a few hours or days. Silicon process engineers can use it to fine-tune their technology to the system architecture specifications.

MAX-3D, R3Integrator, R3CAD, and R3Artist; R3Logic

These tools, developed through work conducted as part of research programs sponsored by the Defense Advanced Research Projects Agency (DARPA), enable 3D IC design and analysis (Figure 3). MAX-3D is a 3D mask layout tool whose technology file includes all properties of stacking process, wafer orientations, bond materials, via electrical/material properties, and also incorporates 2D foundry design kits. R3Integrator is used for die/interposer/package co-design with TSVs. R3CAD is a java-based, multi-platform tool for 3D design research and prototype study and R3Artist is an embedded 3D layout editor (Figure 3).

R3Logic is currently collaborating with STMicroelectronics and CEA-LETI to develop a full 3D design flow for 3D heterogeneous system and system-in-package design.

Figure 3. R3Artist features single and multiple wafer technologies, integrated material properties database and solid model extraction, including dielectric layers.

3DCACTI

3DCACTI estimates the optimum access times and power dissipation of a cache using 3D IC technology for a given number of active device layers and by partitioning device layers for various technology nodes. Based on the estimation, it searches for the optimized configuration that provides the best delay, power and area efficiency trade-off according to the cost function for a given number of different 3D partitions.

3D Magic and PR3D, Massachusetts Institute of Technology

3D Magic is a comprehensive layout methodology for 3D circuit-layout editing and extraction with MAGIC, an open source layout editor developed by UC Berkeley. PR3D is a placement and routing tool for standard cell design in 3D. Both tools were developed through MIT’s Interconnect Focus Center Research Program. MIT also developed SysRel (System-Level IC Reliability) for assessing the interconnect reliability of 3D ICs from a thermal-aware perspective at the circuit-layout level.

Conclusion

With the pressure on traditional 2D chips mounting, 3D integration has begun to establish itself as a viable means of breathing more life into Moore’s Law. It certainly touches on all the hot buttons in the industry today, namely low power, cost and time-to-market. The challenge will be in ensuring that these benefits are realized in a timely and efficient manner. 3D-specific design tools and methodologies are coming to meet this challenge head on. In the meantime, the tools available now and the groundwork for future tools and methodologies being laid by industry organizations, academia and commercial companies alike, will go along way in ensuring 3D integration plays a critical role in the future of the semiconductor industry.