By Ed Sperling
Synopsys posted strong growth for its fiscal Q2. Revenue was $393.7 million, compared to $338.1 million in the same period last year. Net income was $81.1 million, including a $32.8 million benefit from a settlement with the IRS. Excluding that benefit, net income was $48.3 million, which is 22% higher than the $39.5 million Synopsys reported in Q2 of 2010. This is the kind of news we all like to see.

ChipEstimate, which is owned by Cadence, launched a third-party IP portal that was localized for the Japanese design sector. This is interesting for two reasons. First, Japanese chipmakers are now relying on an increasing amount of third-party IP. Second, it offers Cadence another inroad into the Japanese IC business.

Atrenta uncorked the next version of SpyGlass, which includes improvements in everything from debug to power estimation to constraints management and testability. So is this now considered a tool or a platform—and is this the direction for successful tools in the EDA world? The answer could have a significant impact on startups. Meanwhile, STARC–the Japanese Semiconductor Technology Academic Research Center—adopted the new version of SpyGlass into its STARCAD-CEL reference flow.

By Ed Sperling
Mentor Graphics won a couple of power-related deals. The Semiconductor Technology Academic Research Center (STARC)—a group of top Japanese companies that includes Fujitsu, Renesas and Panasonic—has successfully used its Tessent test methodology for low-power ICs. And Fujitsu is using Mentor’s Calibre Proprammable Electrical Rule Checker to protect against electrostatic discharge and to support multiple voltage domains.

STARC also joined forces with Cadence for a 32/28nm DFM flow.

Synopsys rolled out its DDR PHY compiler for multiple flavors of DDR2 and DDR3, complete with unlimited “what if” types of scenarios.

eSilicon has begun work on a 28nm test chip. That opens the door for mainstream chip design to step up to the next node. To put this in perspective, large IDMs have begun work at 22/20nm and 15/14nm.

Arteris won two deals. Pixelworks is using Arteris’ FlexNoC network-on-chip interconnect fabric and its memory scheduler for its video-processing SoCs. RIM, meanwhile, is using TI’s OMAP processor, which includes Arteris’ NoC technology.

On the financial front, MIPS’ Q2 revenue grew 44% year over year to $21.9 million. Net income was $6 million vs. $2.8 million last year. Even more important, license revenue increased 85%. Company executives attribute much of the growth to Android.

TSMC’s revenue rose 19.6% in Q4 of 2010, compared with the same period in 2009, but sequentially the results were down 1.9%. Net income was up 3.1% sequentially and 27.2% year over year. What’s particularly interesting is that 40nm wafers accounted for 21% of the total revenues, and 65nm accounted for another 31%. TSMC considers both to be advanced technology nodes and said this is the first time they’ve accounted for 52% of the total.

By Ed Sperling

Mentor Graphics added SystemC support to its high-level synthesis Catapult C, basically trumping the competition in the HLS space. The advantage is that you can now run synthesis in the same language as high-level modeling. But given this is a game of leapfrog, don’t count on this lead to stay untouched.

Toshiba Information Systems standardized on Synopsys’ VMM-LP methodology, scoring one for the VMM side in what is often a contentious “non-war” between the non-rival verification methodologies OVM and VMM. And where is UVM in all of this?

Synopsys also expanded its IP portfolio with new 3G DigRF and Camera Serial Interface 2 controllers, and PHY for the Mobile Industry Processor Interface.

Atrenta inked a deal to develop an EDA tool quality management system with the Semiconductor Technology Academic Research Center in Japan. As part of the arrangement, STARC provided regression test specs and test cases to Atrenta, which has integrated them into its SpyGlass test suite.  STARC cut another deal with Cadence along similar lines.

In the standards world, Actel is now in compliance with the rigorous ISO 9001 and SAE/AS9100 standards, which mean its chips are now qualified for the most extreme conditions imaginable–and then some.

Ever wonder why Intel decided to build all those fabs in the desert? Check out the eight new solar operations the company is planning. Expected power generation is about 2.5 megawatts. Who needs power companies?

TSMC’s Q4 revenue increased 43% compared with the same quarter last year and net income increased 163%. That’s a lot of zeros in the right place. Either they were giving away wafers last year during the downturn or the number of companies developing chips at advanced nodes is way, way up.