System-Level Design sat down to discuss how to fix what’s broken with John Bruggeman, senior vice president and chief marketing officer at Cadence; Charles Janac, president and CEO of Arteris; Robert Hum, vice president and general manager of Mentor Graphics’ deep submicron division; Mike Gianfagna, vice president of marketing at Atrenta; and Bob Smith, vice president of marketing and business development at Magma. What follows are excerpts of that conversation.

SLD: Customer complaint No. 2: There are not enough tools around the edge, but the problems are now larger than what a startup can provide. How do you solve this?
Bruggeman: There are dozens of examples, but the economics don’t work. If you look at the birth of EDA, the semiconductor companies did everything, took a look at it, realized it was non-differentiating, and they spun it out. It doesn’t make sense for the EDA vendors to do it so the semiconductor companies will have to fund it. It’s the penalty for creating the EDA industry the way they did. But ultimately they’re going to spin it out and we’ll take it on. By then it will have enough maturity where it makes sense for us.
Hum: There might be some lessons out of the FPGA industry. There are a small number of players that dominate the market. They do their own place-and-route and they have their own tools. It seems the way the industry is heading there are some big players. TSMC may say for everyone who needs a standard flow that they provide one. Maybe they provide the tools, maybe they buy an EDA company. Maybe you pay for it when you produce so many chips.
Smith: The FPGA guys drove it to the point where the tools are free.
Hum: The tools are not free. They’re included. That’s a royalty model. But if things go the way they’re going, that could be one of the end points we end up with. Maybe the box standard flow comes from TSMC and GlobalFoundries.
Bruggeman: If they did that, it would be the end of the EDA industry.
Hum: It would. The ASIC industry got out of doing their own EDA because it was cheaper to use common stuff than their own proprietary stuff.
Gianfagna: If TSMC buys EDA, then we’re back to IDMs again and it will be time to spin it out in a few years. It’s a cycle. But you’ve re-created where it all started.
Bruggeman: It might not be a bad thing, but what will happen is a couple of smart EDA companies will see the industry is under massive change. We need to re-invent ourselves. Where is the new value we provide? I will argue it’s in the systems space. The same sort of solution set we provided to the ASICs and IC guys we can deliver to the systems guys, which is not anywhere close to where the TSMCs or foundry guys can play today. It is very conceivable that they could acquire an EDA company and define the flow and EDA as we know it is gone. What will happen is some other EDA companies will be very shrewd and say the next solution set is further up the stack. They will be solving a very hard and complex problem, which is not a software problem but an integration of hardware and software. And then there will be a much bigger industry.
Janac: The problem is that if the industry doesn’t make that leap it will continue to stagnate. It won’t grow, and it may shrink. There have been industries that have shrunk because they didn’t offer the customers value. The question is what’s the innovation people are willing to pay for? They’re not willing to pay for test. They’re not willing to pay for specialized hardware. But there are things people are willing to pay for, and those segments are going to grow.
Hum: The current problem we’re solving may be commoditized. We get to solve the next problem. Innovation is what drives this industry. Technology is not stopping. Von Neumann architectures are not the future. It’s all multiprocessing. How do you help people exploit multiprocessing? Things aren’t getting faster. They’re getting parallel. The software industry hasn’t done such a hot job solving this problem. There’s a whole other architectural side of the world that many companies have been reluctant to let go of because their architects are the smartest guys in the world.
Gianfagna: Maybe there’s a re-learning piece here. How good are we, as an industry, at finding new customers and selling to new customers? We have an abysmal track record there. We’re not willing to try to understand a new problem and adapt our sales. It’s a more difficult version of the same problem at 28nm vs. 180nm, and it’s the same people buying the tools. If you look up the stack at the people building the software, those are our new customers. They talk a different language and they have a different culture.
Hum: They also have a different perception of value.
Gianfagna: That’s an opportunity. We messed it up the first time.
Janac: The question is how you make a $400 million business out of a low ASP. It fundamentally operates on different dynamics than the EDA direct sales force model.

SLD: The customers say they have the EDA industry they’ve paid for. They also say they need lots more standards. And they say there’s an assumption at this point that they have to do the integration.
Janac: It has to be done, and every PCB maker integrates their PCBs. But they do it with standardized components using standardized software. It’s like building a castle out of Lego blocks. You can build it out of Lego blocks, which is what most people do, or you can carve the blocks yourself and build a castle. What they’re doing now is carving the blocks and building the castle, and it takes more money, takes more time and has more errors. We need to provide a platform on which this innovation takes place.
Gianfagna: How much standard infrastructure do you need to make that work from an industry level? And where are we today? It’s a big change.
Janac: One of the things that made Cadence was a language called Skill. Everything was standard about Cadence except for Skill. It allowed people to write features on top of the Cadence software without going to Cadence. You wound up with hundreds of thousands of lines of Skill code at major IDMs. Everything else was standard but this was sticky. I would say it was to the benefit of the industry the way Microsoft Office benefits the software industry. You can go anywhere in the world, fire it up on any system, and it works. Skill would work on any system and it was a marketplace standard. It was the same with Verilog. These standards have to be set, but they cannot be legislated. They have to be established by a powerful company behind them that manages to get it adopted on an industry basis. While Skill benefitted Cadence it also benefitted the industry.

SLD: The business model of the whole industry, coupled with disaggregation, are causing problems. For a company like ST, they can fill in the pieces and write their own tools. But is that the future.
Janac: ST also loses money, which is not a good model. So the question is how much of an R&D footprint do you want to have? That’s decreasing, which is why the industry is disintermediating.
The market decides. The question is what is your core value.
Gianfagna: One of the ways MediaTek became popular is they sell both hardware and software. And they sell into the Chinese marketplace like mad.
Hum: They also don’t take on new things.
Gianfagna: But they level of integration they provide is a value add.
Hum: They do cost reductions.
Gianfagna: It’s not just cost reductions.
Janac: I disagree. Saying someone is an innovator and a copier is misleading. When they get profitable they begin to innovate.
Bruggeman: I would argue they are an innovator now. They have a level of innovation we don’t associate with.
Hum: That’s cost innovation.
Janac: But their path to getting bigger is functional innovation.

By Ed Sperling
Mentor Graphics moved past Cadence into the No. 2 spot in EDA behind Synopsys, a position it hasn’t held for at least the past 15 years, according to new numbers from Gary Smith EDA. Mentor also is the clear market leader in PCB design with the Valor acquisition, which will get very interesting once 3D ICs begin hitting the market over the next couple of years.

According to the latest stats from the research/consulting company, Synopsys has 32.5% market share in EDA by revenue, followed by Mentor with 18.4% and Cadence with 18.1%. Magma had 2.8% and Agilent 2.7%.

But Cadence is hardly standing still. The company’s realignment around software and IP is just getting going and it continues to make gains in analog-mixed signal.Cadence’s QRC Extraction was adopted by STMicroelectronics for 40nm AMS design.

Synopsys inked a deal with SVTC Technologies, which provides development and commercialization services for chips in markets such as biotechnology and MEMS. SVTC will use Synopsys’ manufacturing tools to accelerate time to commercialization.

ARM rolled out its Development Studio 5 Application Edition to simplify the development of Linux and Android apps for ARM-based systems. What’s interesting is the product enables developers to begin debugging and testing before the hardware is available.

TSMC broke ground on its third 300mm fab in Taiwan. That sounds like a vote of confidence for the semiconductor industry.

Along the same lines, Intel reported its best quarter ever with revenue of $10.8 billion and net income of $2.9 billion. That should spur some additional business.

By David Lammers
Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanical stress had relaxed over time and the top die had delaminated.

3D researchers around the world are paying much closer attention to thermal and mechanical stress, particularly as ever-thinner die are stacked and connected. At last week’s 2010 Symposium on VLSI Technology in Honolulu, IMEC researchers described the mismatch in the coefficient of thermal expansion between copper through-silicon vias (TSVs) and the surrounding silicon. Using a 45nm digital analog converter test chip, the IMEC team measured transistor drive currents with TSVs located at various distances from the active circuits. Tensile stress near the TSVs was in the range of mega Pascals (MPa), declining to zero stress at a distance of about 10 microns from the TSV edge – a distressingly long distance for today’s leading-edge devices.

That kind of fundamental information (IMEC will deliver a more-complete paper at IEDM in December), Marchal said, is allowing EDA vendors and chip manufacturers to begin creating stress models. “Thermal and mechanical stresses induced by TSVs is a big worry for the community, but I believe there are different ways to mitigate them. A lot depends on what type of devices you use. Stress is not uniform for different types of devices; for example, long channel devices see more impact.”

At its Leuven facility, IMEC is fabricating a series of test chips, named after volcanos, which have sensors positioned at various places on the die to measure thermo-mechanical stress. “We position the smart sensors at the most critical places inside the stack, with the DRAM on top, to study the thermal and mechanical impacts. Then we provide the information to our supply chain partners, including the DRAM makers and packaging houses. Our partners, such as Qualcomm and STMicro, want to gain a head start. When they start RTL-level design they want to know what is feasible and what is not.”

Fig. 1: IMEC is working with several EDA partners to create a pathfinding flow for 3D prototype creation. (Source: IMEC)

While the EDA community is making progress, Marchal worries about is the relative absence of the packaging design community. Co-design of the die and package is particularly important as top die are thinned to 50 microns or less, positioned on top of a much thicker die.

“The die are becoming as thin as aluminum foil, and if you have the wrong glue, or different heat cycles, the die do not remain flat. That builds up stress across the die. The EDA and packaging communities need to be more active in how to analyze this,” Marchal said.

These challenges will be solved, particularly as increasingly large investments are being made in 3D TSV technology. At the DAC conference last week, Myung-Soo Jang, a design infrastructure manager at Samsung Electronics, described Samsung’s plan to use TSVs to link a mobile logic device with a 400 MHz DDR3 memory. “Because we are the world’s largest memory maker, which also has systems expertise from our cell phone business, we believe we have an advantage in this area,” Jang said.

Memory manufacturers such as Samsung and Toshiba, bring certain advantages, but fabless and foundry vendors are forming their own alliances, including EDA vendors and packaging houses. At DAC, L.C. Lu, director of the design methodology division at TSMC, called 3D TSV “the next killer application” and outlined a 3D design flow that TSMC is developing.

The mobile systems vendors need TSV interconnects to support the bandwidth needed for new data services, which include point-to-point video, a market set to accelerate over the next five years. High-definition video encoding requires about 12.8 GB/s of bandwidth between the processor and DRAM memory. The only way to do that in a mobile system is with TSV-connected logic-memory solution, using three or four tiers of die thinned to 30 to 40 microns. To achieve the same bandwidth, conventional DRAMs would require the power-hungry GDR5 DRAM standard, some 2,000 I/O pins, and a frequency that would kill any cell phone battery quickly.

Sitaram Arkalgud, director of Sematech’s 3D interconnect initiative in Albany, N.Y., said Sematech is focused now on a copper-copper bonding, vias-middle manufacturing flow that will come into use in several years. To tackle the stress challenge better standards are needed for how to measure and report thermal and mechanical stress levels. At next month’s Semicon West in San Francisco, Sematech and Germany’s Fraunhofer IZFP research center will hold a workshop on 3D stress management, including DFM-like approaches for managing stress, material properties, and measurement techniques.

Arkalgud said Sematech and SEMI are working on a data exchange format for TSV applications, and will hold a meeting on the subject at Semicon West and again at Semicon Europa in the fall.
“Especially as we go to thinner die the TCE and stress issues will be something we need to watch. To do that, we have to agree on how to measure it, so a data exchange specification needs to be there,” Arkalgud said.

By Ed Sperling
Faced with shrinking margins, manufacturing process fluctuations that could mean one more or one less atom in a transistor and proximity issues in layout the most advanced chipmakers have begun designing for variability.

Rather than working with fixed numbers, such as voltage, power and area, the goal of DFV is basically averaging all of these numbers. While this includes some level of margin, the approach actually can reduce the total margin in an SoC. But it also requires a whole different way of approaching a design, which is why the companies that are working with DFV have developed their own tools. So far there are no commercially available tools for DFV.

The law of averages
DFV is not a new concept, even though it has not been commercialized in tools. In fact, it’s been talked about for the better part of two decades. But at 32/28nm and beyond it may be the most cost-effective approach for chip development. Companies like Intel and STMicroelectronics already are developing chips using this approach, with the likelihood that it will become more standardized.

Several technologies do exist in this area, although much if it is considered deep research at the moment. The most prominent of the tools that have surfaced is Razor, which is an open-source version of dynamic voltage scaling. The stated purpose for Razor is dynamic detection and correction of circuit timing errors. Other approaches that have begun filtering into the market in the past couple years are adaptive timing, and some IP is now being offered with parameters of acceptable power.

But while this may be the subject of research, at least some of this technology is showing up in everyday products. Intel now offers burst mode on its processors, for example, which requires sensors to manage the variable power output to make sure the chip doesn’t overheat when additional current is applied to a single core. And as power becomes more of a consideration, so will DFV.

“DFV and design for low power are the same thing,” said Jan Rabaey, professor at the University of California at Berkeley and head of the Berkeley Wireless Research Center. “The goal is to try to let the chip address a lot of these issues and you measure and adjust accordingly.”

One of the interesting side notes of this approach is that it negates the use of corner cases. Designs that are statistical averages have their own built-in margin, which needs to be much more accurate than corner-based designs that work off a worst-case scenario approach. So even though there are margins, those margins in total consume less overhead in terms of power and performance than a corner-based design.

“We’re starting to use variability for average performance,” said Rabaey. “It’s a natural trend to go that way.”

Natural, perhaps. But also very difficult, particularly without the kind of automation that has made digital design so efficient for the past four decades. At the moment, most of the work in this area is being done by large IDMs and researchers. Big EDA companies are watching the trend, but a dozen interviews held at DAC show that so far they either have not seen a profit opportunity or they’re not talking about it other than to concede that it’s difficult stuff. That leaves companies using this approach on their own.

Indavong Vongsavady, digital design solutions and pilot project director at STMicroelectronics in Crolles, France, said the big problem his company has been grappling with is process variation at advanced nodes. A transistor at 22nm, for example, will behave differently with one extra atom of metal—or one less. And with millions of transistors on a chip, it’s almost impossible to ensure every atom will be where it’s supposed to be and that power and performance will not suffer or cause problems.

“Process variation has pushed us to design for variability,” said Vongsavady. “We take that into consideration with our IP.”

ST has begun using this approach at 32nm, which it expects to begin ramping in the second half of 2011. And numerous sources say all of the major IDMs are now experimenting with this model.

New math
Designing chips has always been about math, but it’s moving from geometry to a combination of geometry and purely mathematical models that are floating averages within a precisely defined set of parameters rather than fixed models with a wider range of accepted limits.

This is increasingly true for IP, place and route, synthesis and software, but it also is true even at the manufacturing level where computational scaling will likely supplement restrictive design rules with acceptable limits about variation. In the future the parameters will be narrower but there will be far more of them to contend with much further up in the design cycle.

By Ann Steffora Mutschler

The EDA industry has seen a number of large acquisitions as of late, most notably of Denali by Cadence, as well as CoWare, VaST and Virage Logic which were acquired by Synopsys, but just what impact does this realignment have on the biggest EDA customers? Commenting on these changes is Jean-Marc Chateau, director of system platforms and tools at STMicroelectronics, the world’s fifth largest semiconductor manufacturer, in this exclusive System-Level Design interview.

SLD: As one of the industry’s largest EDA tool customers, how do you view the recent acquisitions?
Chateau: It is very interesting what is happening. It looks like all of the big players – Cadence, Mentor and Synopsys – are waking up to say, ‘We should change speed on ESL and try to create a market,’ which has always been so far in the $200 million range. Synopsys has been very aggressive, first with Virtio [in 2006], then with CoWare and VaST. It’s quite interesting because it can bring consolidation around pieces that were not fully interoperable. There are positive aspects of SystemC but there are things lacking in the standard – there are still missing pieces. So every company including semiconductor companies – not only tool and IP vendors – they have been obliged to build their own extensions. The fact is that companies like CoWare and Synopsys have to solve the interoperability between models and tools of what they have acquired because it’s not enough to be SystemC compatible. It will be positive because they will have to solve the problem for us.

But on the negative side, the risk is that they will build a closed solution and try to milk the user community—especially the software community—with a proprietary solution to which, when you enter you can not get out, and you have to follow all the flow with their tools. So we are looking at what will happen. I believe it will take Synopsys two years to really consolidate a single modeling solution out of what they are buying today. Cadence is more on the IP because Synopsys was very strong on IP; Cadence was stronger maybe on tools and they are trying to complete their solution. Mentor has a lot of pieces as well but still not very coherent and consistent all together.

SLD: Given that ST had a development relationship with CoWare, will the acquisition by Synopsys change ST’s relationship with the companies in terms of ESL development?
Chateau: In terms of ESL, ST has a long history of internal development. We have quite a large team developing solutions for all the divisions of ST and ST-Ericsson and this started more than 10 years ago. We have been pioneering ESL, especially pushing for open standards such as OSCI TLM. We have been chairman of the board at the beginning and also involved with SPIRIT IP-XACT for assembly of different IPs into SoC and subsystems. Therefore, we have an internal solution that is widely used for complex SoCs in TV, set-top boxes and mobile phones. The usage we have of CoWare is marginal – focused on the processor. We use technology to manage the coprocessor and to generate ISS and also to configure the coprocessor attached to a flexible processor. We have our own internal processor called XP70 – Tensilica-like, let’s say – and CoWare is our supplier in terms of technology to configure this processor. It is widely used in many applications such as set-top boxes and mobile phones. But this is very marginal.

There is another usage of CoWare in ST-Ericsson, which comes from the legacy of the acquisition of NXP Mobile and Ericsson. They were using CoWare especially in NXP so there are some platforms or subsystems that are using CoWare models, but fortunately they followed the TLM standard and we have been able easily to build a completely interoperable platform from the various pieces in ST-Ericsson. So for us, CoWare is relatively marginal and the fact that it was acquired by Synopsys is not impacting us much.

SLD: Do you sense from what you hearing that the top EDA vendors understand users’ biggest challenges in ESL?
Chateau: It is much better than it was, I would say, because we have been talking with them for years on that and there is really a change today in those three companies. I see, for example, Cadence has launched EDA 360; Synopsys of course will have to merge Virtio and CoWare into one platform, but it may leave it aside for the moment and maybe merge it later. And Mentor, they try to put together what they have in a consistent way. The verification part was a bit forgotten before but it is more part of it.

What they have not understood in the past is that the cost of modeling is very high and we cannot afford, by any means, to duplicate the platform for several flavors. We have system-level platforms that require a higher level of abstraction above RTL. You have the architects that need performance from this platform with certain flavors. There are verification people, mostly the sub-verification people, who require some testbenches at a high level. You also need to have a virtual platform for software development. The three cases would require in theory different approaches of modeling, but we cannot afford this so what we did 10 years ago was to make a decision and say, ‘We are going to define one way to do models and we have to apply it all of the categories,’ because it is always difficult to populate fully in TLM a complete system platform with models. To do that three times – no way. I think if you look at all of those companies – VaST, CoWare, etc. – they are focused on either verification or software virtual platforms or architecture investigation, but not the three of them together. Now, it seems to me, it is my perception that they need to tackle all, having in mind that the biggest population is software development. But if you look at the software budget we put on the shoulder of the software designer, it is very light in terms of CAD. We buy very few tools; we mostly rely on point tools so to introduce the same business approach as in hardware design with CAD seats that cost several $10Ks will not work in the software world. I still think they dream a bit.

SLD: With Synopsys acquiring Virage and Cadence acquiring Denali, how do you view this consolidation?
Chateau: To me it was very obvious Synopsys was missing the embedded memory part in their portfolio. With Virage they don’t target anything but that part. I don’t think they are very interested in the other part. They will have to make a choice between the differentiation on parts I’m sure. For Denali and Cadence, it is a little bit different because Cadence is still very weak overall in its IP portfolio, so I have no comment on this. Denali is strong in models so that can be a good asset for the company to position because they have acquired also a lot of companies for VIP and transactors and this is key to build an offering in ESL. So I think they have a good strategy, which is a lower cost strategy than what Synopsys did. So, we’ll see.

SLD: Does ST mind that the IP it purchases come from the tool provider?
Chateau: We preach for interoperability and we are very active in standards for that purpose, so we would like to deploy the IPs with the tools as much as possible. This is why in OSCI we are very much attached to the fact that there is an open source simulator that you can run with any models from any IP vendor to see if it is really following the standard. Of course the companies would like to kill this and do only paper for the standard because they would like to make money out of simulators in Mentor, Cadence and Synopsys, and CoWare before the acquisition. I understand, but we are fighting to keep that preference because TLM OSCI SystemC cannot be as strict and non-ambiguous and RTL-like as Verilog and VHDL. You really need to have an open source to check interoperability. The higher level you go, the more reference you will need like this, and therefore, our wish is to be able to buy IPs wherever we want independently of the tools. Today, if you look at what we buy … our biggest supplier is Synopsys, but it’s not because of the tools.

By Ed Sperling
Moore’s Law marches on. Virage Logic rolled out its memory compilers and logic libraries for TSMC’s 28nm high-k/metal gate process. This follows Virage’s first 28nm test chip tapeouts late last year. Word on the street—from those willing to talk about it—is that 28nm is relatively straightforward from a feature-shrink standpoint, although power will still be an issue. But 22nm is giving everyone the chills.

Mentor Graphics rolled out a DO-254 platform with enhanced HDL coding. DO-254 is an FAA standard for complex hardware in airborne systems.

NTT Electronics created a graphics chip using Arteris’ network on chip technology. This is an interesting application for NoCs because of the high volume of traffic on a graphics chip. Graphics is one of those areas that is embarrassingly parallel, so adding order to the chaos of on-chip communications is vital.

RT-RK created a big-endian version of Android for the MIPS platform. There was already a little-endian version. Big endian and little endian were terms created years ago by Unix vendors, depending on whether you read zeros and ones from left-to-right or right-to-left. It was an analogy to the big end of the egg or the little end. It’s a good thing eggs aren’t round.

Sales are up everywhere. STMicroelectronics also adopted Mentor’s Veloce emulation platform for next-generation set-top box chips. It should be noted, however, that even though we insist on calling these set-top boxes, nothing can ever rest on a flat-panel TV. Perhaps we need a new name.

Also on the sales front, Cadence inked a deal with TSMC for integrated signoff at 65nm with synthesis, place and route and RC extraction. Cadence also won new business from HSilicon for mixed-signal and low-power tools,  and from LSI for mixed-signal technology.

And in the same vein, Aptina adopted Apache Design System’s analysis, optimization and signoff technology for its image sensors. Apache also started the year with record bookings and revenue for Q1. We like hearing that kind of news.

eSilicon and Brite Semiconductor joined Synopsys’ IP OEM partner program. This puts eSilicon into the same group as Open-Silicon and Global Unichip. Apparently this is a club you need to join if you build chips for other companies.

Global Unichip, meanwhile, also licensed ARM’s IP portfolio. This is an interesting company to watch because of TSMC’s hedged investment in a company that rivals eSilicon and Open-Silicon, both of which are TSMC customers. It’s like riding a bicycle on a narrow trail next to a precipice. You don’t want to make any sudden movements. http://www.arm.com/about/newsroom/global-unichip-licenses-comprehensive-arm-ip-portfolio.php

By Ed Sperling
eSilicon will acquire Silicon Design Solutions, which makes memory IP cores. SDS is headquartered in Silicon Valley, but it has design centers in Vietnam and Texas.

Apparently things were better than expected at Virage Logic. The company updated its guidance for the quarter, pushing its numbers upward by as much as $1 million. Executive chairman Daniel McCranie attributed the change to rapid integration of acquisitions, controlling spending and a “significant increase” in royalties. We all like that kind of news.

Synopsys rolled out DesignWare DDR multiPHY IP, fusing support for six different DDR standards in a single PHY. This is the IP version of a package deal. http://synopsys.mediaroom.com/index.php?s=43&item=789

Cadence won a deal with STMicroelectronics to use its OrCAD PSpice technology for evaluating analog and power ICs.

As strong as the FPGA market is in the United States and Europe, it’s exploding in places like China and India. Proof point: Actel’s 24 x 5 technical support. It’s not that chip engineers work the same kind of hours as software developers—the Mountain Dew swigging night owls. But they do work in a lot of different time zones these days.

By Pallab Chatterjee

Field solvers have always been part of the Parasitic Extraction (PEX) world, but due to their long run times and complexity in configuration, their role was relegated to the setup/reference table generation for the pattern based 1-D and 2-D RC extraction tools. That’s about to change.

Mentor, in combination with STMicroelectronics, one of it customers, said that at 22nm field solvers are the required method of determining the PEX values with full live data. This acknowledgment follows Silicon Frontline’s claim that the necessity for the new technology is mandatory starting at the 32nm process node due to process complexity.

For process technologies from 2 microns through the 65nm technology node, PEX has been utilizing full 3D Maxwell’s Equations electric field solvers to help determine the R and C values for static conditions that are the technology tables used by all extractors. Based on the industry-leading and reference product Raphael (TMA to Avanti to Synopsys), the accuracy for determining what the extracted values should be has been set by the text description of the vertical process topology (layer stacking and inter-layer dielectrics) used to drive the PEX tools.

The field solver is used to create the vertical and coupling capacitance values between the interconnect layers with respect to substrate and to adjacent interconnects. Because these values change with spacing and with how many layers appear at a time (for example, M2 over substrate vs. M2 under M3 + over M1 over well over substrate), the generation of the reference tables for a process could literally takes days for all the computations to finish.  The results are a complex table of drawn patterns that the PEX tools searches for in the layout, and when it finds one it determines the size and factors that with the values in the reference table.

At 32nm and below this method is no longer sufficient, however. The technology that is used to make the 11-15 interconnect layer processes now has enormous variability in layer thickness (both interconnect layer and inter-layer dielectric). There also are differences in the profiles in terms of the size and shape of single vs. multiple vias, as well as changes in the via profiles per layer. And just to make things even more complicated, there are multiple materials used for contacts and vias by context (gate poly contacts vs. field poly contacts, for example.) As a result, it is no longer possible to create a static reference table of characteristics for “look up” by the PEX tool.

The PEX environment must now operate in true 3D mode—instead of 1D of look down or 2D of look down and to the side—with full process flow information, to determine dynamically what the R’s and C’s should be for a given net, in all conditions and patterns of the net.

Silvaco introduced its Clever product nearly 10 years ago to address this issue at the IP/gate level. It is a full multi-threaded, multi-core-aware 3D field solver that has been used to address these issues for critical design in image sensors, memories, and other highly capacitance sensitive structures since the 1 micron arena. The product has been used mostly by integrated device manufacturers (IDMs) and fabs, due to the close reliance on having access to the process flow information that is needed to drive the tool, as well as the reluctance by the fabs to release that level of information to most end customers.

In the new scenario, Silicon Frontline, Mentor (and most likely Synopsys in the near future), will work with foundries and IDMs to get the appropriate process and modeling information and secure it in the tool, so the information is both available and unreadable by people.  This new cooperation was driven by the necessity of the process technology, not any inherent new-found trust with the EDA vendors, to be able to have SOC and IP designers create functional parts.

The Silicon Frontline product has been commercially available since mid 2009. Mentor’s tool will be named and available soon. And most of the customers are assuming the Synopsys offering will be announced sometime this year. These products have applicability at larger geometry processes using chip-to-chip stacked die, as there is significant coupling from the thinned and “potato-chip profile” top chip that is connected to through-silicon vias or other bonds.

By Ed Sperling

It was a good week for thinking out of the package.

Mentor Graphics acquired Valor Computerized Systems, a recognition that system problems now extend well beyond the chip. Valor’s expertise is in PCB software and DFM. The purchase price was about $50 million, including $32.5 million in cash and 5.6 million shares of Mentor stock. Interestingly, Valor’s revenue for 2008—the last full year it reported—was about $40 million.

Mentor also inked a three-year joint-development deal with STMicroelectronics to develop advanced SoC design solutions down to 20nm.

Actel appears to be benefiting from its new SmartFusion rollout. The company updated guidance, saying Q1 revenue will be up 4% to 8%, instead of 2% to 6% it had previously reported. http://www.actel.com/company/press/files/busupdateQ110.pdf

Cadence is expanding its academic network in Europe, adding three universities from Bucharest, Stockholm and Braunschweig for everything from PCB design to low-power methodology.

Intel rolled out its first six-core 32nm Xeon chip for servers, claiming it offers 60% more performance for the same power consumption of 130 watts. Versions of the chips with lower clock speeds can use as little as 40 watts.

Synopsys gobbled up another software prototyping supplier—CoWare—a company that never quite made it public despite its historically close relationship with Cadence. This pretty much clears out the field of software prototyping companies. Synopsys has announced plans to buy VaST. It already bought Virtio in 2006. And Wind River snapped up Virtutech before it was acquired by Intel.

Whether this is good or bad depends on your point of view, but it’s hard to argue that SoCs cannot be improved—particularly when it comes to multicore and multi-power domain implementations—when software is considered way up front in the design. Terms of the CoWare deal weren’t disclosed, meaning the purchase price wasn’t significant enough to warrant disclosing them.

Speaking of acquisitions, memory maker Micron is buying Numonyx, the joint venture between STMicroelectronics, Intel and Francisco Partners for $1.27 billion in stock. Memory is a nasty node-by-node competitive business, and anything that can be done to gain an edge is worth a lot of money.

TSMC’s numbers exploded in January vs. the previous year—up 134%–but they slipped slightly from December 2009, down 4.5%. It’s hard to read too much into consecutive monthly fluctuations, but year-over-year numbers are a sign that growth is back. action=detail&language=E&newsid=4541 TSMC also expanded its relations with IC makers and technology centers inside of China, but that’s all we know. The rest is in Chinese.