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Behold the Intrinsic Value of IP

Monday, March 13th, 2017

By Grant Pierce, CEO

Sonics, Inc.

Editor’s Note [this article was written in response to questions about IP licensing practices.  A follow-up article will be published in the next 24 hours with the title :” Determining a Fair Royalty Value for IP”].

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Understanding the intrinsic value of Intellectual Property is like beauty, it is in the eye of the beholder.  The beholder of IP Value is ultimately the user/consumer of that IP – the buyers. Buyers tend to value IP based upon their ability to utilize that IP to create competitive advantage, and therefore higher value for their end product. The IP Value figure above was created to capture this concept.

To be clear, this view is NOT about relative bargaining power between buyer and the supplier of IP – the seller –  that is built on the basis of patents. Mounds of court cases and text books exist that explore the question of patent strength. What I am positing is that viewing IP value as a matter of a buyer’s perception is a useful way to think of the intrinsic value of IP.

Position A on the value chart is a classification of IP that allows little differentiation by the buyer, but is addressing a more elastic market opportunity. This would likely be a Standard IP type that would implement an open standard. IP in this category would likely have multiple sources and therefore competitive pricing.  Although compliance with the standard would be valued by the buyer, the price of the IP itself would be likely lower reflecting its commodity nature. Here, the value might be equated to the cost of internally creating equivalent IP. Since few, if any, buyers in this category would see advantage for making this IP themselves and because there are likely many sellers, the intrinsic value of this IP is determined on a “buy vs buy” basis.  Buyers are going to buy this IP regardless, so they’ll look for the seller with the proposition most favorable to the buyer – which often is just about price.

Position B on the value chart is a classification of IP that allows for differentiation by the buyer, but addresses a more elastic market. IP in this category might be less constrained by standards requirements. It is likely that buyers would implement unique instantiations of this IP type and as a result command some end competitive advantage. Buyers in this category could make this IP themselves, but because there are commercial alternatives, the intrinsic value is determined by applying a “make vs buy” analysis. The value proposition of the sellers of this type of IP often include some important, but soft value propositions (e.g., ease of re-use, time-to-market, esoteric features), the make vs buy determination is highly variable and often buyer-specific. This in part explains the variability of pricing for this type of IP.

Position C on the value chart is a classification of IP that serves a less elastic market and empowers buyers to differentiate through their unique implementations of that IP. This classification of IP supports license fees and larger, more consistent, royalty rates. IP in this category becomes the competitive differentiation that sways large market share to the winning products incorporating that IP. This category supports some of the larger IP companies in the marketplace today. Buyers in this category are not going to make the IP themselves because the cost of development of the product and its ecosystem is too prohibitive and risky. The intrinsic value really comes down to what the seller charges.

This is a “buy vs not make” decision – meaning one either buys the IP or it doesn’t bother to make the product. A unique hallmark of IP in this position is that so long as the seller applies pricing consistently, then all buyers know at the very least that they are not disadvantaged relative to the competition and will continue to buy. Sellers will often give some technology away to encourage long-term lock in. For these reasons, pricing of IP in this space tends to be quite stable. That pricing level must subjectively be below the level that customers begin to perform unnatural acts and explore unusual alternatives.  So long as it does, the price charged probably represents accurately the intrinsic value.

Position D on the value chart is a classification of IP that requires adherence to a standard. Like category A, adherence to the standard does not necessarily allow differentiation to the buyer. The buyer of this category of IP might be required to use this IP in order to gain access to the market itself. Though the lack of end-product differentiation available to the buyer might suggest a lower license fee and/or lower to zero royalty rate, we see a significantly less elastic market for this IP type.

This IP category tends to comprise products adhering to closed and/or proprietary standards. IP products built on such closed and/or proprietary standards have given rise to several significant IP business franchises in the marketplace today. The IP in position D is in part characterized by the need to spend significant time and money to develop, market and maintain (defend) their position, in addition to spending on IP development. For this reason, teasing out the intrinsic value of this IP is not as straightforward as “make vs buy.” Pricing is really viewed more as a tax. So the intrinsic value determination is based on a “Fair Tax” basis. If buyers think the tax is no longer “fair,” for any reason, they will make the move to a different technology.

Examples:

Position A:  USB, PCI, memory interfaces (Synopsys)

Position B:  Configurable Processors, Analog IP cores (Synopsys, Cadence)

Position C:  General Purpose Processors, Graphics, DSP, NoC, EPU (ARM, Imagination, CEVA, Sonics)

Position D: CDMA, Noise Reduction, DDR (Qualcomm, Dolby, Rambus)

Why Customer Success is Paramount

Sonics is an IP supplier whose products tend to reside in the Type C category. Sonics sets its semiconductor IP pricing as a function of the value of the SoC design/chip that uses the IP. There is a spectrum of value functions for the Sonics IP depending upon the type of chip, complexity of design, target power/performance, expected volume, and other factors. Defining the upper and lower bounds of the value spectrum depends upon an approximation of these factors for each particular chip design and customer.

Royalties are one component of the price of IP and are a way of risk sharing to allow customers to bring their products to market without having to pay the full value of the incorporated IP up front. The benefit being that the creator and supplier of the IP is essentially investing in the overall success of the user’s product by accepting the deferred royalty payment. Sonics views the royalty component of its IP pricing as “customer success fees.”

With its recently introduced EPU technology, Sonics has adopted an IP business model based upon an annual technology access fee and a per power grain usage fee due at chip tapeout. Under this model, customers have unlimited use of the technology to explore power control for as many designs as they want, but only pay for their actual IP usage in a completed design. The tape out fee is calculated based on the number of power grains used in the design on a sliding scale. The more power grains customers use, the more energy saved, and the lower the cost per grain. Using more power grains drives lower energy consumption by the chip – buyers increase the market value of their chips using Sonics’ EPU technology. The bottom line is that Sonics’ IP business model depends on customers successfully completing their designs using Sonics IP.

Blog Review – Monday, February 13, 2017

Monday, February 13th, 2017

Among this week’s topics: two important announcements: the OpenFog Consortium and IEEE Standard for the Functional Verification Language e; a panel discusses the Internet and beyond; Mentor Graphics applies IoT to PCB design; FASTR accelerates the connected car and why USB is not as easy as 123

The importance of IP blocks is a given, but Rocke Acree, ON Semiconductor, explains how selection also has to consider technology and support tools. The company has collaborated with Hexius Semiconductor to qualify analog IP blocks to reduce design cycles and development time.

There are specific constraints, challenges and design requirements for PCBs designed for the burgeoning IoT market. John McMillan, Mentor Graphics has created a two-part blog focused on this topic.

Doing a quickstep around the topic of USB, Eric Huang, Synopsys, explores verification and FPGA prototyping for best results. He recommends some design rules, a test site, then curiously, throws in some political comment, a film review and dance-related jokes to end the blog.

It may not be an understatement by Rhonda Dirvin, ARM, to say that the day the OpenFog Consortium announced its reference architecture is the day we have all been waiting for. Hyperbole? Possibly not, as it defines how secure, interoperable products should be built – just what the connected world needs. She helpfully includes a link to the architecture, and a heads-up on a presentation at Mobile World Congress in Barcelona, Spain (Feb 27 to March 3).

If there is an award for Most Apt Acronym, the Future of Automotive Security Technology Research (FASTR) consortium, must be a contender. The uncredited Rambus blog reviews the brief history of the consortium, and discusses its recent manifesto, looking at why it is need for a secure, connected vehicle industry.

2017 begins with the publication of IEEE Std 1647 2016, the IEEE Standard for the Functional Verification Language e. of 2017. Efrat Shneydor, Cadence Design, looks at the enhancements which have been made and proficiently summarizes the highlights.

Generic connectivity is not enough – NASA has been designing, building and launching satellite systems with the goal of providing connectivity throughout the world. The concept and realities of the Internet of Space is the panel discussion topic, reported by John Blyler, Chip Design Magazine.

Caroline Hayes, Senior Editor

Blog Review – Monday, January 23, 2017

Monday, January 23rd, 2017

This week’s blogs show the human face of automated driving; and why energy should be taken seriously. There is lift-off for SpaceX to bring more satellite comms and a poetic turn, in the style of Rudyar Kipling’s classic poem.

There is a human element to automated driving, namely Human Machine Interface (HMI) and Jack Weast, Intel, uses his second blog post to examine how and why it can be used. He promises more in part three into the company’s research.

Energy is a serious business, says Grant Pierce, Sonics, and the electronics industry must shoulder some responsibility for power savings. The company, with Semico Research is conducting a survey and wants your help into understanding today’s and tomorrow’s power requirements.

Boosting the satellites to provide point-to-point communications, the SpaceX Falcon 9 rocket put the first 10 Iridium NEXT satellites into Low Earth Orbit (LEO), equipped with Xilinx space-grade Virtex-5QV FPGAs to implement the satellites’ On Board Processor (OBP) hardware. Steve Liebson, Xilinx, includes a link to a video describing the constellation and the launch.

Celebrating the relationship with Ericsson, Dassault Systèmes’ Olivier Ribet, looks at how the latter’s Networked Society will transform the way we interact with the world around us and meet technology challenges, such as 5G, IoT and the cloud.

Moving to 10nm and lower process geometries pushes the boundaries of FinFET and the custom layout flow and this means trouble ahead, warns Graham Etchells.

A touch of culture, with a poem “wot I wrote” by Keith Hanna, Mentor Graphics. He deftly tackles Computational Fluid Dynamics (CFD) as Rudyard Kipling might.

Image data and the mysteries of how to create, access and use a Qimage to greatest effect is detailed by Laszlo Agocs, Qt, with three case studies to illustrate what can be done.

A sharp video addressing the interconnect verification challenges is hosted by Nimrod Reiss. Cadence’s Corrie Callenbach has found and highlighted the video.

Caroline Hayes, senior editor

Blog Review – Tuesday, November 22, 2016

Tuesday, November 22nd, 2016

New specs for PCI Express 4.0; Smart homes gateway webinar this week; sensors – kits and tools; the car’s the connected star; Intel unleashes AI

Change is good – isn’t it? Richard Solomon, Synopsys, prepares for the latest draft of PCI Express 4.0, with some hacks for navigating the 1,400 pages.

Following a triumphant introduction at ARM TechCon 016, Diya Soubra, ARM, examines the ARM Cortex-M33 from the dedicated co-processor interface to security around the IoT.

Steer clear of manipulating a layout hierarchy, advises Rishu Misri Jaggi, Cadence Design Systems. She advocates the Layout XL Generation command to put together a Virtuoso Layout XL-compliant design, with some sound reasoning – and a video – to back up her promotion.

A study to save effort is always a winner and Aditya Mittal and Bhavesh Shrivastava, Arrow, include the results of their comparisons in performing typical debug tasks. Although the aim is to save time, the authors have spent time in doing a thorough job on this study.

Are smart homes a viable reality? Benny Harven, Imagination Technologies, asks for a diary not for a webinar later this week (Nov 23) for smart home gateways – how to make them cost-effective and secure.

Changes in working practice mean sensors and security need attention and some help. Scott Jones, Maxim Integrated looks at the company’s latest reference design.

Still with sensors, Brian Derrick, Mentor Graphics Design, looks at how smartphones are opening up opportunities for sensor-based features for the IoT.

This week’s LA Auto Show, inspires Danny Shapiro, NVIDIA, to look at how the company is driving technology trends in vehicles. Amongst the name dropping (Tesla, Audi, IBM Watson) some of the pictures in the blog inspire pure auto-envy.

A guide to artificial intelligence (AI) by Douglas Fisher, Intel, has some insights into where and how it can be used and how the company is ‘upstreaming’ the technology.

Caroline Hayes, Senior Editor

Blog Review –Monday, October 24 2016

Monday, October 24th, 2016

The how, what and why of time-of-flight sensors; Conference season: ARM TechCon 2016 and IoT Solutions Congress; Save time on big data analysis; In praise of FPGAs; Is it time for augmented and virtual reality?

Drastically reducing big data analysis is music to a data scientist’s ears. Larry Hardesty reports on researchers at MIT (Massachusetts Institute of Technology) have presented an automated system that can reduce preparation and analysis from months to just hours.

Keeping an eye on the nation’s bank vaults, Robert Vamosi, Synopsys, looks at the what bank regulators are doing to ramp up cybersecurity.

If you can’t head to Barcelona, Spain this week for IoT Solutions World Congress (October 25-27), Jonathan Ballon, Intel, reveals what the company will unveil, including a keynote: IoT: From Hype to Reality, what 5G means, smart cities and a hackathon.

Tired of the buzz, and seeking enlightenment, Jeff Bier, Berkeley Design, delves into just what is augmented reality and virtual reality. He examines hardware and software, markets and what is needed for widespread adoption.

Closer to home, 2016 ARM TechCon, in Santa Clara, California (October 25 – 27), Phil Brumby, Mentor Graphics, offers a heads-up on its industrial robot demo, using Nucleus RTOS separated by ARM TrustZone, and the ECU (Engine Control Unit) demo in a Linux-hosted In-Vehicle Infotainment (IVI) system. There is also a technical session: Making Sure your UI makes the most of the ARM-based SoC (Thurs, 10.30am, Ballroom E)

The role of memory is reviewed by Paul McLellan, Cadence Design System, as he discusses MemCon keynotes by Hugh Durdan, VP of the IP Group and Steve Pwalowski, VP of Advanced Computing Solutions at Micron. There is comprehensive pricing strategy and a look at industry trends.

A teardown of the Apple iPhone 7, by Dick James, Chipworks, links STMicroelectronics’ time-of-flight sensors with the Starship Enterprise. The blog has a comprehensive answer to questions such as what are these sensors and why are they in phones.

If the IoT is flexible, Zibi Zalewski, Aldec, argues, then FPGAs can tailor solutions without major investments in an ASIC. He takes Xilinx’s Zynq-7000 All-Programmable SoC as a starting point and illustrates how it can boost performance for IoT gateways.

Elegantly illustrating how multiple Eclipse projects can be run on a single microcontroller with MicroEJ, Charlottem, ARM, runs through a connected washing machine that can communicate via Bluetooth, MQTT, Z-Wave and LWM2M.

Caroline Hayes, Senior Editor

Blog Review – Monday, October 10, 2016

Monday, October 10th, 2016

This week, bloggers look at the newly released ARM Cortex-R52 and its support, NVIDIA floats the idea of AI in automotives, Dassault Systèmes looks at underwater construction, Intrinsic-ID’s CEO shares about security, and there is a glimpse into the loneliness of the long distance debugger

There is a peek into the Xilinx Embedded Software Community Conference as Steve Leibson, Xilinx, shares the OKI IDS real-time, object-detection system using a Zynq SoC.

The lure of the ocean, and the glamor of Porsche and Volvo SUVs, meant that NVIDIA appealed to all-comers at its inaugural GPU Technology Conference Europe. It parked a Porsche Macan and a Volvo XC90 on top of the Ocean Diva, docked at Amsterdam. Making waves, the Xavier SoC, the Quadro demonstration and a discussion about AI in the automotive industry.

Worried about IoT security, Robert Vamosi, Synopsys, looks at the source code that targets firmware on IoT devices, and fears where else it may be used.

Following the launch of the ARM Cortex-R52 processor, which raises the bar in terms of functional safety, Jason Andrews looks at the development tools available for the new ARMv8-R architecture, alongside a review of what’s new in the processor offering.

If you are new to portable stimulus, Tom A, Cadence, has put together a comprehensive blog about the standard designed to help developers with verification reuse, test automation and coverage. Of course, he also mentions the role of the company’s Perspec System Verifier, but this is an informative blog, not a marketing pitch.

Undersea hotels sounds like the holiday of the future, and Deepak Datye, Dassault Systèmes, shows how structures for wonderful pieces of architecture can be realized with the company’s , the 3DExperience Platform.

Capturing the frustration of an engineer mid-debug, Rich Edelman, Mentor Graphics, contributes a long, blow-by-blow account of that elusive, thankless task, that he names UVM Misery, where a customer’s bug, is your bug now.

Giving Pim Tuyls, CEO of Intrinsic-ID, a grilling about security, Gabe Moretti, Chip Design magazine, teases out the difference between security and integrity and how to increase security in ways that will be adopted across the industry.

Blog Review – Monday, September 26, 2016

Monday, September 26th, 2016

Robotic surgery reaches new levels, and ARM raises safety critical benchmarks with Cortex-R52, supported by Synopsys tools. There is a preview of Intel’s DVCon Europe’s presentation for virtual systems and DTF proves to be a classic rulebook.

Described as a ‘fairy tale’ by the grateful recipient, surgeon using a joystick to remove a membrane from the patient’s eye could sound like an Orwellian nightmare, but Tom Smithyman, ANSYS, has collected his favorite blogs, one of which is on the BBC website and explains how surgeons at the John Radcliffe Hospital performed robotic-assisted eye surgery.

You may have heard that ARM launched its Cortex-R52, ARMv8-R processor and hot on the heels of the announcement, Synopsys has announced design support for safety critical automotive, healthcare and industrial applications, reports Phil Dworsky, Synopsys.

Still with ARM, Rob Coombs, explains how mobile security architecture can be adapted for IoT applications, with copious graphics and an introduction to TrustZone for ARMv8-M on microcontrollers.

The more things change, the more they stay the same, can be the conclusion reading a blog by Stephen Pateras, Mentor Graphics, who shows that DFT-related rules hold true now, as they did in the 1980s.

Is a coup is in the offing at the IEEE? John Blyler Systems Design Engineering, makes sure of the facts by checking with the current President-Elect, Karen Bartleson about the proposed amendment to the IEEE constitution ahead of next month’s vote.

DVCon Europe 2016 takes place in the German city of Munich next month and Jakob Engblorn, Intel, will present a paper there based on integrating SystemC models into a virtual system. For those who can’t attend in person, his blog previews his technical and informative paper.

Caroline Hayes, Senior Editor

Blog Review, Monday, September 12, 2016

Monday, September 12th, 2016

This week, we find the legacy of Star Trek at 50; celebrate design challenges from NXP and Hackster.io; investigate criminal activity and speculate on Bluetooth 5 and headphone design; arriving late for an FPGA verification tutorial and how depth sensors make sense of a 3D world

The enduring appeal of Star Trek on its 50th anniversary sets Tom Smithyman, Ansys, thinking about communications, and how Qualcomm challenged engineers to emulate the great and the good of the USS Enterprise and create Dr McCoy’s medical tricorder.

Another challenge is laid down by NXP, which has teamed up with Hackster.io, for engineers to fulfil the potential of NXP’s Kinetis FlexIO for the IoT. Donnie Garcia, ARM, tracks how engineers can maximize the, often over-looked, microcontrollers at the edge of the IoT, with some arachnid-like illustrations.

Quoting a bank robber is an unusual opening for a technology blog, but Matthew Rosenquist, Intel, uses Willie Sutton to help us understand the cybercriminal. His blog about cryptocurrencies, like Bitcoin, and how to protect transactions is a detailed look at the cyber economy – and this is just part one.

Apple’s decision to remove the headphone jack in its latest phone has been met with derision, but one positive is that it has prompted Paul Williamson, ARM, to speculate on the whether wireless accessories could be boosted as Bluetooth 5 brings faster data rates.

How have I missed the first three parts of Mentor Graphics’ Harry Foster’s blog about Functional Verification? Part 4 looks at FPGA verification and some handy ‘escapes’ for effective verification, written by an engineer, for engineers.

Anyone designing consumer electronics will be familiar with the DDR PHY interface (DFI) protocol for signal, timing and transfer. Deepak Gupta, Synsopsys has written a clear, comprehensive analysis of how and why it is needed and used most effectively.

Continuing a theme he has explored before, Jeff Bier, Berkeley Design Technology, looks at depth sensing and what companies are doing with varieties of depth sensors.

We all love Whiteboard Wednesdays, and Corrie Callenbach, Cadence Design Systems, highlights Michelle Mao’s hierarchical CNN design for traffic sign recognition, highlighting Tensilica Vision DSPs.

Caroline Hayes, Senior Editor

Blog Review Monday, August 29, 2016

Monday, August 29th, 2016

This week’s blogs are futuristic, with machine learning, from Intel, augmented reality from Synopsys, smart city software from Dassault Systèmes, questions and answers about autonomous vehicles, and security issues, around devices and MQTT on the IoT.

Artificial intelligence is the next great wave, predicts Lenny Tran, Intel. His post looks at machine learning and Intel’s High Performance Computing architecture is part of the way forward in machine learning.

On a similar theme, Hezi Saar, Synopsys, examines the Microsoft 28nm SoC and is impressed with the possibilities for augmented reality that the HoloLens Processing Units has for this developing marketplace.

If you are dissatisfied with your present office location, Dassault Systèmes has plans for smart faciliites, reports Akio. He describes some illuminating projects using 3D Experience City, real-time monitoring, the IoT and systems operations for a comfortable workspace in smart cities.

It’s all about teamwork according to Brandon Wade, Aldec, who offers an introduction to the AXI protocol. His post summarizes the protocol specifications and shares his revelation at how understanding the protocol opens up a world of design possibilities.

Autonomous cars are occupying a lot of Eamonn Ahearne’s, ON Semiconductor, time. Living in the hotbed of self-drive test, he reads, visits and analyses what is happening and is disappointed that hardware is being eclipsed by software in the popularity stakes.

Also occupied with autonomous vehicles, Andrew Macleod, Mentor Graphics, starts with an update on electric vehicles, and moves onto the disconnect between ADAS technologies and autonomous vehicles and the engineering challenges that can be addressed using a single ECU (Engine Control Unit).

Attending the Linley Mobile & Wearables Conference, Paul McLellan, Cadence Design Systems, pays attention to Asaf Ashkenazi of Cryptography Research (now part of Rambus) and his well-illustrated post reports how devices can be secured.

An IoT network, powered by the ISO/IEC PRF 20922 standard MQTT (MQ Telemetry Transport) can be at risk, warns Wilfred Nilsen, ARM. It is a sound warning about personal information being vulnerable to MQTT brokers. Luckily, he offers a solution, introducing the SMQ IoT protocol.

Caroline Hayes, Senior Editor

Blog Review – Monday, August 15 2016

Monday, August 15th, 2016

In this collection, we define the IoT, investigate IP fingerprinting, and break into vehicles in the name of crypto-research. There is also prophesizing about 5G and disruption technology for technology, and relationship advice for computing and data.

Empathizing with anyone who has ever struggled with CMSIS RTOS API, Liviu Ionescu, ARM, offers a helping hand, catalogues the issues that can be encountered and reassures designers they are not alone and, more importantly, offers practical help.

Putting IP fingerprints to work may sound like the brief for an episode of CSI, but it is Warren Savage’s, (IP-extreme) recipe for successful SoC tapeout. He does do some CSI-style digging to thoroughly explain how to delve into a chip’s IP to limit the risks associated with IP reuse.

Listening intently at the Linley Mobile Conference, Paul McLellan, Cadence, sees the advent of 5G as good news for high-capacity, high-speed, low-latency wireless networks and linked with all things IoT.

Famous couplings, love and marriage, horse and carriage, could be joined by computing and data. Rob Crooke, Intel, believes that an increase in data and increased computing will transform cloud computing, but that memory storage has to keep up to realize smart cities to autonomous vehicles, industrial automation, medicine, immersive gaming to name a few. His post covers 3D XPoint and 3D NAND technology.

On security detail this week, Gabe Moretti, Chip Design magazine, finds a white paper from Intrinsic-ID that he recommends on the topic of embedded authentication which is vital to the secure operation of the IoT.

At the end of this year, the last Volkswagen Camper, (or kombi) van, will roll off the assembly line in Brazil. Robert Vamosi, Synopsys, includes the iconic vehicle in his post about a hack related in a paper authored by researchers at the University of Birmingham to clone a VW remote entry systems. The paper was presented at the Usenix cybersecurity conference in Austin, Texas, with reassurances that the group is in ‘constructive’ talks with VW.

For a vintage automobile to the latest, EV and PHEVs, Andrew Macleod, Mentor Graphics, looks at disruption they may bring to the automotive industry. Referring to account technology manager Paul Johnston’s presentation at 2016 IESF, he touches on the electrical engineering and embedded software challenges as well as the predicted scale of the EV industry.

Still looking at a market rather than the technology, Alex Voica, Imagination Technologies, looks at the IoT. He has some interesting graphs and statistics and asks some interesting questions around definitions, from what is the IoT and what defines a device.

Caroline Hayes, Senior Editor

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