Can startups still survive in an increasingly complex, high up-front investment world? System-Level Design posed that question to Mentor Graphics, Synopsys, Oasys and an end user.

By Ed Sperling

System-Level Design sat down with Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group; Serge Leef, vice president of new ventures and general manager of the System-Level Engineering Division at Mentor Graphics; John Busco, CAD manager and blogger, and Sanjiv Kaul, executive chairman at Oasys. What follows are excerpts of that conversation.

SLD: Where is EDA today? Is it more valuable than it used to be?
Leef: EDA user crossroads right now, which has to do with what’s happening with our customers. The group of customers we historically have served is dividing into two camps. One group is doing huge, very complex platform chips. They need sophisticated back-end flow tools, as well as sophisticated front-end tools that allow them to model and experiment with sophisticated 500 million-gate designs. The process for those people is being strained on both edges. However, there are fewer and fewer people that can afford to do huge chips like this, and certainly fewer that can afford to manufacture them. The second group that is emerging and becoming much more prominent is the group that does systems. Their challenge is to take those systems and add value to them, whether it’s through software or industrial design or packaging. The community that’s emerging includes system designers, for whom the large, vertically focused platform chips are becoming more adequate. The motivation for them to do original hardware declines. But they do have to solve system-design problems.
Kaul: You can’t get a chip designed without EDA, and chip design is still very important to our economy. But if you do an analysis on the EDA industry, its competitive position is diminishing. There are fewer people doing these big chips. There is less differentiation between the EDA players. Some would argue there are too many EDA players, and therefore the differentiation is less and the negotiating power of the EDA players is diminished. If you talk to EDA companies, they think they’re not getting enough value for what they produce. It’s more a structure of the industry, with regard to the customers and the competitive position of the industry.
Leef: The trend of the separation of the design community means the EDA industry is having a hard time satisfying the platform chip designers because they really are pushing the state of the art. At the same time, they don’t know what to do about the system-level designers. We have one market that’s diminishing in size but growing in complexity, and then we have this other market that is potentially large but we don’t know how to tap it.

SLD: What’s the user perspective?
Busco: Of course EDA is important, but the value is splitting because the way the design community is getting strung out over many generations of silicon. For people that are still willing to design ASICs for their application at 130nm, or even FPGAs, EDA is necessary. But it’s more of a commodity product. If you’re designing at 40nm 32nm or 28nm, EDA is not only important, it’s incredibly valuable. You can’t do you design without it. That market is getting smaller because the NRE costs are becoming such a high hurdle that many companies cannot justify the design. But for those that can justify it, EDA is just as valuable as it was in the past.
Domic: There are people doing very important and profitable designs at 130nm, and there are people moving to 28nm. The spread is much larger than it used to be. I don’t need the latest signal integrity analysis tools if I’m going to be doing another 130nm derivative. On the other hand, I see that even with the decrease of the number of very large chips, the number of licenses we see being consumed by our customers continues to go up. Going to 32nm and 28nm and forward, we’re finally getting to the point where the only ones able to make the investment will be two or three [EDA] companies. Startups tend to go for not even a tool but a subset of a tool. To design a 100 million-cell chip, very few companies can do it.

SLD: We’re coming at this from two perspectives. One is from the user, the other is from the EDA company.
Domic: But if someone today wants to provide a full place-and-route solution with all the parasitic extraction, DRC and LVS, the R&D investment EDA companies need to make is enormous. You can’t invest more than 30% or 35% of your sales in R&D or Wall Street will question your existence. So we’re seeing a similar problem in EDA. A customer cannot just say they’ll design a 50 million-cell chip. EDA is seeing the same problem. They have to be selective about where they develop their tools.
Kaul: One of the challenges for EDA has been that with new technologies it doesn’t take a very large team to build the technology. Most successful products were built by four or five brilliant guys. Obviously the first release of the product has to have enough value that people will buy it, and the bar can go higher and higher as you move into more complex technologies. But that’s one of the reasons there has been more competition in EDA than is probably healthy.

SLD: Will that continue?
Kaul: As long as the current solutions are not meeting the needs of customers—if it takes five days to run place-and-route on a complex block, for example—there is an opportunity for someone to come in with a better solution. If you need 20,000 servers to run simulation and you’d like to see a 20x improvement, there’s an opportunity. It’s not easy, but it’s what you have to do.
Leef: When I started working at Intel in 1982, they believed the reason they would win was architectural superiority, their ability to push the state of the art in process, and because of their CAD tools. At that time, the EDA landscape was pretty bare and Intel had 300 to 400 people working on EDA tools. It was predicated on the fact that Intel didn’t believe anyone outside of Intel understood their problem well enough to solve it for them. At 22nm, Intel once again believes no one else understands its problem. It’s not inconceivable we might start seeing big semiconductor players bringing EDA back in house.
Kaul: IBM already uses a lot of internal tools.
Domic: It’s more complicated than that. Every quarter Synopsys announces we had one customer that contributed more than 10% of our revenue. At the same time, the internal team than what they had for EDA is larger. I don’t see a return to internal tools, but I do see a combination where they work with a few suppliers in specific areas, and those areas may change in time.
Leef: But if Intel decided one day that it was important enough to distinguish itself with EDA, that could have a big effect. It’s not economically challenging for them.
Domic: Nobody has money to do everything.
Busco: There will continue to be innovation by startups and small shops. It’s something that everyone benefits from. EDA is an academically rigorous and exciting field, so there are a lot of extremely bright people going into these areas. They’re anxious to start up a company with a small team, and we see the benefits. There are needs for new point tools. Some of the existing tools can’t keep up with design sizes or process complexities. Either the point tools from these startups will solve the problem or they will wake up the major players, which is a side benefit. The major players have a strong tendency to become complacent or focus their efforts elsewhere. When a startup shows them that something can be done in a revolutionary way either the startup will walk away with the business or the established player will turn the battleship and come up with a much better product, as well.

SLD: At 28nm and below, are the big chipmakers relying on internally developed tools until the other stuff becomes commercially available?
Busco: It depends on the style of designs. For digital ICs, commercial EDA comprises the vast majority of the solution. Companies have CAD groups to integrate flows and develop point tools where they can add value, but a customer will not write anything like a place-and-route or synthesis tool. Back when signal integrity was a novelty, we may have had to develop our own tricks. But now it’s part of every EDA tool, so there’s no need to develop an in-house solution.
Kaul: Whatever EDA can solve, customers will buy commercially. But EDA companies also have to make business decisions. They try to solve problems they think will give them a competitive advantage or which they can make a business out of. There are certain problems where the data required to make a good product is proprietary. Intel and IBM don’t want to share that with you. They’ll develop it themselves. Either that or the EDA companies don’t want to solve the problem for them because it makes no sense economically. But if these companies can buy commercially, it’s less expensive.
Domic: If you look at innovation at the large companies, Mentor and Synopsys have done a good job providing things that didn’t exist like, lithography checks. Everybody did chip layouts, even though to keep up with the set of rules at 28nm is tough. But when you look at lithography checks, we built a completely new router that will carry us to 28nm and 22nm. When I do see internal efforts, it’s because there is a lot of flux in terms of preferred rules. Every company interested in coming out early with a new technology is doing their own schemes to develop what is important and what isn’t. The investment from the large companies has been pretty significant and has managed to satisfy IC developers. I don’t see many people trying to develop their own lithography checker.
Leef: In the areas where the tool footprint is well defined, the major EDA vendors jump in, invest heavily and come up with good solutions. In areas where the footprint of the tool and the definition of the need are fuzzy, that’s where the customers have a tendency to invest their internal cycles and do things specific to them. But if you’re architecting a chip with 500 million gates, the architectural and system-level alternatives are profound and the EDA industry has not come up with a cohesive set of tool footprints in that area. Almost every customer I talk with that’s trying to solve front-end problems has a home-cooked solution or some combination of commercial, public domain and home-cooked. The boundaries between what the commercial tools can provide and what the in-house tools can provide are fluid, and that’s where we see internal EDA groups putting a lot of effort.

By Ellen Konieczny

As active devices and interconnect wires shrink and are placed closer together with the march of Moore’s Law, signal integrity is becoming a huge concern. If it is not maintained, a design’s future may be marred by lower yields, unreliable performance, and failure to work efficiently—if at all.

For low-power and radio-frequency (RF) designs, which are being produced at a steady climb, this challenge is even more daunting. Such designs involve numerous aspects that make it more difficult to ensure signal integrity. Due to their very nature, RF designs also face more severe consequences if signal-integrity rears its head in the form of problems like interference and noise.

Among the design aspects that threaten low-power designs, for example, are multiple power operating modes, multiple voltage supplies, voltage and frequency scaling, and voltage islands. As noted by Shekhar Kapoor, Synopsys’ senior product marketing manager for the Galaxy Signoff Solution, “The use of low-power techniques, such as power islands and on-off switching behavior, can exacerbate signal-integrity issues. The potential issues to worry about include dynamic voltage drop, power-grid electromigration, and electromagnetic-interference (EMI) noise. All these effects could worsen if care is not taken to manage the in-rush current in turning on power switches, for example.”

To overcome this challenge, Kapoor recommends a holistic approach to handling signal integrity that has in-design and signoff analysis working together. To mitigate the signal and power-grid integrity issues, place-and-route tools must provide various optimization and fixing techniques. Examples include wire-width adjustments, multiple via insertions, and buffering. In addition, the signoff parasitic extraction and timing/signal-integrity solutions must offer detailed debug and fixing to address any undetected problems before tapeout. At smaller nodes—especially below 40-nm process technologies—the parasitics have become context-specific (i.e., layout-dependent). To ensure silicon accuracy, the extraction tools must model the context-specific device parasitics as part of the extraction process. They can then account for the amplified effects of the MOS device parasitics at smaller nodes.

Beyond a winning approach, the key to successful low-power design is really a mindset. The techniques used to achieve low-power design introduce a high level of complexity at the levels of system design, functional verification, IC physical design, and IC testing. To achieve success, it is therefore essential that the designer keep the low-power aspect in mind beginning with the earliest stages of design. According to Michael Buehler-Garcia, director of marketing at Mentor Graphics’ Design to Silicon Division, “Engineers need ways to evaluate different architectural approaches to power reduction early in the design process, at the system level. They also need to verify functionality in detail, ensuring that transitions between power modes do not create logical errors and that state retention is handled correctly when parts of a chip are temporarily powered down.”

RF Design Poses Further Hazards
The RF aspect of a design adds a much more complex set of challenges, as it is essential that the integrity of the communication path be maintained. Among the chief concerns are electromagnetic (EM) degradation and EM-interference (EMI) noise. Dave Robertson, vice president of analog technology for Analog Devices, says his company sees the maintenance of signal integrity being comprised of two elements: Amplifying, processing, and transmitting the signal with minimal degradation due to distortion or device noise, and minimizing the effects of induced external signals from crosstalk, power-supply noise, or other external interference

The simplicity with which those two goals can be stated belies their complexity—especially considering the short time to market for RF products. This issue is compounded by the fact that signal integrity traditionally has been a concern in the digital-circuit rather than the RF domain. Thankfully, as signal-integrity issues began to rear their heads in high-speed communications designs, software developers have pruned signal-integrity analysis environments to address both device and circuit models. With today’s shrinking ICs interacting more with both active neighboring devices and interconnects, it is crucial that such interactions are modeled accurately.

During analog design, custom IC layout and simulation tools are used to accurately model the behavior of an RF or other analog circuit. The designer can therefore determine if signal integrity will be compromised by interactions within the cell itself. Yet Mentor’s Buehler-Garcia notes the designer also must avoid signal-integrity problems when the RF cell is placed within the context of a full mixed-signal IC, which may interact with other circuits including digital signals.

Once active and passive device models have explored all of the high-frequency effects, signal integrity may be ensured by using a comprehensive set of analysis engines that leverage that modeling capability. According to Ted Mido, senior staff engineer for Synopsys’ circuit simulation product line, designers must be sure to exercise both of these options. He notes that most designers rely on time-domain analysis for final behavioral verification. Therefore, the baseline would be to have high-performance, high-capacity transient and transient noise analyses.

In the early design phase, Mido notes that system or subsystem behaviors may be predicted by using small-signal frequency-domain analysis to predict system S-parameters, small-signal noise parameters, transfer functions, and so on at a particular operating point. In addition, a statistical eye-diagram simulation can predict deterministic channel noises like inter-symbol interference, duty cycle distortion, and periodic noise. Finally, large-signal steady state analysis may be used to predict nonlinear and modulation effects. Of course, these analysis engines must be able to accurately accommodate all of the high-frequency effects originally modeled.

Although electronic-design-automation (EDA) tools are clearly working to ensure signal integrity in RF designs, a lot may be gained in the hardware design as well. As ADI’s Robertson notes, “There are CAD tools for capturing and analyzing parasitic resistance and capacitances, but it can be difficult to come up with models of sufficient accuracy, and for large chips it is generally impractical to exhaustively capture and simulate these parasitics. Different circuit topologies and architectures may make the problem much better or much worse, so circuit innovation can often relieve what was perceived as a ‘hard physical constraint.’”

Beyond Moore’s Law, ADI recognizes a number of challenges spawned by the functional density involved in mixed-signal and RF integration. Although active power density is a fundamental challenge, some relief may be found in advanced packaging solutions. Similarly, powering down idle blocks offers advantages when dealing with inactive power density from leakage currents in very deep-submicron CMOS. It should be noted that this benefit does come at the cost of more sophisticated power management circuits and systems.

In terms of current density, the fine metal pitch and increasing functional densities can cause electromigration and IR drop problems in the on-chip interconnect. The process solution is to use copper and thick copper interconnect. Yet bump and flip-chip packaging can provide a 2D bonding approach so these currents do not need to be routed all the way across the chip. Such approaches also reduce the inductance of these connections.

The signal-integrity puzzle will only grow more complex as designs continue to shrink while consuming less power and incorporating more wireless capability. Going forward, for example, it is critical for designers to realize that signal integrity will need to be considered between chips as well as on chips. Mido states, “The massive integration of cores on vertically stacked chips (3D ICs) that don’t necessarily feature the latest transistor technology node is becoming common. Therefore, high-speed communication between cores/chips is becoming important. With the increasing operational frequencies of these digital communication bus/links, bit-error-rate (BER) prediction is also becoming important (See Figure 1).”

Figure 1: For accurate bit-error rate predictions in high-speed digital communications, it is critical to account for aspects like high-frequency loss mechanisms, millions of possible bit patterns, special techniques for equalizing digital signal shape both in transmitter and receiver side, and multiple noise mechanisms.

Five experts sound off to System-Level Design on the state of synthesis and what’s needed in the future: Shawn McCloud, product line director for Catapult C Synthesis at Mentor Graphics; Chris Eddington, director of marketing for system-lvel products at Synopsys; Brett Cline, VP of marketing at Forte Design Systems; Andy Biddle, director of business development at Magma and Sanjiv Kaul, executive chairman at Oasys.

By Pallab Chatterjee

The high cost of SoC development at advanced process nodes is forcing a significant shift in many of the methodologies used in design.

Hierarchical design methods are giving way to IP integration and hierarchical analysis at the architectural and functional design levels. Previously, large blocks were implemented at the top level of the chip and the analysis was pushed off until these top blocks were done and the chip was checked as a whole. The rising complexity of today’s designs and the ability to interpret results from current EDA tools cannot sustain this approach.

This shift in design tasks has been a major point of discussion at a number of recent industry events. The focal point of integration and analysis was presented formally for discussion by Jim Hogan and Paul McLellan at the recent ICCAD conference, and was amplified through the rest of the ICCAD conference as well as at ARM’s Techcon3, the MEMS Executive Congress and the Low Power Workshop. While the main context of the discussion by Hogan and McLellan was EDA business models and the location of the rapidly dissolving profit margins and value in the design flow, the technical conferences presented panels and papers exemplifying the new focal point and methodology.

The role of the integration phase has pretty much been unchanged since the start of IC design. It is separated into three levels: component/device design, IP/block design and architectural/system design integration. While the breadth of the work at these levels has grown and now includes level-specific analysis, the overall scope of the levels remains fairly unchanged over the past 30 years. The component/device design activity has shifted from being a common task performed by all semiconductor companies to a specialized task performed by just a small portion of the supply chain and specialty semiconductor firms.

The MEMS and Low Power events focused on the base process technology and new application device areas. Both areas, which are currently undergoing double-digit revenue growth, are focused on traditional component-level design and process per device functional performance optimization. The MEMS and low power marketplaces have joined standard product memories and largely shifted out of the modern design ecosystem, requiring them to use the old “IDM style” design flow. Due to a lack of transportable and standard design tools, these markets create custom devices, IP blocks and then final full designs on in-house flows for in-house standard product chips.

There is no functional multi-company IP market in these channels. The primary analysis tools are at the mathematical, mechanical and physics levels rather than transportable in high-level languages. The analysis also is very company- and function-specific rather than standards-based.

Following this trend, the fabs and IDMs that are still in the primitive device creation market have been focusing on creation of customized software tools to support integration and analysis. ICCAD had several papers on NBTI (negative bias temperature instability), SEE (single event error), thermal issues, yield and reliability tools and models created by these device manufacturers to perform fab-line specific-use analysis. These are not general-purpose tools with large target audiences. Instead, they are being created by the fabs and IDMs, in conjunction with the universities, for internal use.

At the ARM event, ARM was the primary transistor-level provider of design knowledge for sub-90nm processes, surrounded by an ecosystem that includes a large number of design partners who could use these transistor-level elements as function blocks. Among them are IP and software companies targeting the next level of hierarchical major design activity, which includes analyzing and optimizing these IP blocks. Correspondingly, the technical sessions were no longer focused on the creation and use of the IP in a technology node, but on the integration and interoperability of the IP blocks to implement functions.

Follow the money
The biggest shift in the design trend is that most of the integration and analysis is solely a hardware task, even though the largest development portion for an SOC is the application software. This effort is currently both the largest segment of the development cost and the largest manpower allocation on a project. The software is implemented at multiple levels from microcode to control in-hardware state machines and embedded processors/controllers to standard interface control firmware (such as for DDR3 memory control) to higher-level code such as ECC, operating systems, GUIs, and in-system applications.

The software requires co-verification and iteration of the logic hardware, possibly the IP selected and the software/firmware. This activity is now performed in high-level languages, which are typically many orders of abstraction above the mathematics and physics level issues of the manufacturing process. As a result, there are many traps for the creation of high-level SoC systems that are physically realizable and yieldable.

The biggest challenges facing cost-effective yield in new SOC designs aren’t necessarily the lithographic process or the actual wafer fab. More important is that the designs are being created at high levels of abstraction without regard for the realities of having sub-wavelength active transistors that need to be manufactured in high volume. The systems designers have been hiding behind the “comfort” of the ESL and high-level EDA tools, and have lost touch with the devices that make up the functions. As a result, there is little regard or respect for the concept of a single chip with billions of devices on it, all of which have to work as planned.

Engineers at the conferences say a lot of the issues are due to the commercial EDA vendors making SoC tools having spent literally decades away from the semiconductor manufacturing and device R&D floor, and creating solutions that produce algorithmically and mathematically valid solutions that also are physically unrealistic and which cannot be implemented. As the vendors do not have a good feel for the validity of solution, so go the solutions from their tools not being valid from an engineering perspective. An example of this gap in understanding is the creation of hardware logic solutions with firmware control, which return a fatal error rate in the 1 part per millions region. Given an optimistic perspective that these errors occur in the 1 part per 100 million range, a 1 billion-plus transistor device would then have more than 10 fatal errors in the design.

The knowledge base of creation, integration and verification will need to be re-unified to address this issue. Only then can the industry reverse the point tool segregation of the problem that has been promoted by the EDA industry for the past 20 years so that modern SoC design once again will not be the domain of just a few semiconductor companies.

By Ed Sperling
System-Level Design sat down with Frank Schirrmeister, director of product development in Synopsys’ solutions group; Ghislain Kaiser CEO of DOCEA Power: John Sanguinetti, CTO at Forte Design Systems; Vincent Perrier, Cofluent Design co-founder and director of products and marketing.

SLD: Where do models fit into the standards world?
Perrier: Models are becoming the central things that engineers work with. But it goes much further than just translating the code into gates on the chip. There are power models, performance models and virtual platform models. It can be a custom-based approach by aggregating multiple IP blocks or a top-down approach starting from a functional or architectural description or a power model. These are very different approaches for designs.
Sanguinetti: There’s a lot more impetus to settle on a standard when you have models that people want to use from different sources.
Perrier: The whole point of models in ESL is to make sure those models work together.
Sanguinetti: Right, but those models are coming from different places.
Perrier: There also are a lot of them. Today you cannot find one model to represent all the different facets of a design. If you want a full picture of a system, you need to get all those models together, combine them, and simulate them so you can make your architectural tradeoff decisions on the basis of power. Power is becoming as important as everything.
Kaiser: The first goal for a system now is to improve interoperability because of all the complexity. You need to adapt that for every domain. That’s the case with power and timing.

SLD: Whenever a company turns over technology to a standards group, they have a jump on everyone else because they know the technology better. Is that window shrinking or growing?
Sanguinetti: It depends on the technology. If you need a standard to make models interoperate, no one has a big advantage.
Schirrmeister: It’s not a complexity issue. That’s solved according to how a design process is structured. The standards support that structure. If you look at the next big systems on chip, you have blocks in there and you need to be able to deal with those blocks. That includes development of the blocks, which is where high-level synthesis comes in. You need standards for a language that you can use to synthesize. You need to be able to deal with re-use of those blocks. That’s where SPIRIT comes in. You characterize those blocks and give them power formats. And then you need to integrate those blocks into the full chip. So you need the higher-level model for verification and for performance analysis, which is where TLM simulation comes in. It’s not that complexity influences the window. It’s that the complexity changes the design process, and for the different components you have individual windows on how to deal with this.

SLD: How far along are we with this?
Schirrmeister: With TLM 2.0, it’s like we’ve standardized on the VCR with VHS, but all the remotes don’t interoperate because everyone has different controls. That’s the next thing we’re trying to standardize on—the configuration and control of those TLM models. Those standards grow and build on each other.
Perrier: The EDA industry has a lot to learn from the software industry in this domain. They are way ahead of us in this area because they have been dealing with interoperability for a long time.
Schirrmeister: They have been dealing with this problem since 1968, and the last time I checked they still haven’t figured it out. But there is at least some interoperability in the software world. I assume you’re talking about UML (Unified Modeling Language).
Perrier: UML is one. There are also meta-model techniques. IP-XACT is an XML-based standard. In the software world you have Ecore, which an Eclipse implementation of the [Object Management Group] standard.

SLD: The software world has its own issues that have been going on for decades, most notably in operating systems, interfaces and parallelization.
Schirrmeister: And I’m not sure what we’ll actually learn from the software side. In the software world you have a company like Microsoft saying, ‘Here it is,’ and everyone has to deal with it. The same was true with UML for awhile, where Rational and Telelogic were dominating the market.

SLD: But isn’t this still a top-down definition?
Schirrmeister: Everything does need to fit into a top-down model, but the work is being done in two directions. The problem is that it’s like digging a tunnel from both sides where you don’t meet in the middle. You’re pushing down with high-levels of abstraction and UML is tunneling up, but they don’t quite meet. Now we are trying to figure out ways to see how UML will fit.
Kaiser: This is the challenge of the ESL domain. But if a new standard appears, there is a question of whether it will survive because it has to join these two worlds, from UML to hardware constraints.
Schirrmeister: When you talk about standardization, it’s always about restriction. You have this big item about what UML covers, and conceivably you can develop a profile of UML that may fit into something that will be able to synthesize down to RTL. That’s like a UML for hardware profiler. If this is SystemC, there is a subset that is synthesizable. The same happened with Verilog in the past.
Perrier: The software industry calls this domain-specific languages.

SLD: So is UML the answer?
Kaiser: I’m not sure that today UML can respond to the hardware constraints. We may have to modify UML because it was not created for hardware.
Schirrmeister: A standard never does something for itself. You always have to have a user need. Hardware developers are not that concerned if something is UML compliant. They have a very specific need to get to a virtualized model of the embedded hardware they’re developing as fast as possible so they can start software development. If my solution happens to be that I have a technology that takes UML, restrains it to a domain-specific subset and then allows a fast implementation, they will happily adopt it because it serves their need. But they won’t do it because it’s UML.
Sanguinetti: That’s a very relevant point to this discussion. Back when Synapse was working on a precursor to SystemC, I looked at UML. It was too far removed from the kinds of problems we were looking at.
Schirrmeister: I think we are getting closer. It’s just a question of how fast is the train going.

System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCPIP), and Michael Meredith, vice president of technical marketing at Forte Design Systems. What follows are excerpts of that conversation.

By Ed Sperling

SLD: Problems lead to standards, followed by new problems that require standards. What are the problems that need addressing now?

Schulz: Our next effort will be to create a standard for 3D chip integration. This is an important area as Moore’s Law runs out of economic steam, if not technologically. The need for stacking die, and having standards for through-stack vias, how you handle the electrical modeling of that and the geometrical positioning and synchronizing of them has to be done not only across a multivendor flow for a particular die, but across different companies that are putting together the different die that you’re assembling into a package. Many companies have said they’ve gone as far as they can go without standards. You need the processor and stacked memory. If you’re doing a wireless communication device you’ll need the RF fabric with analog baseband on top of some digital and some memory. Often it’s easier and cheaper to do it with different die.

SLD: Is that because of heat?

Schulz: Both heat and economics. To continue integration in 2D is getting too costly, the line lengths are too long, there are uncertainties of how you do the routing, the design fabric—everything has its own specialty from a manufacturing standpoint. The real estate is a problem.

Meredith: As a general rule of thumb, the need for standards in EDA are always at the top and at the bottom. At the bottom, it’s where new process geometries create new challenges. And at the top, as we try to raise the level of abstraction we’ve got SystemC and ESL standards.

Trivedi: Whether it’s top and bottom or front and back, the IP goes all over the place. How you use it, deploy it, verify it and integrate it may be in the middle of the design process. I think of it more as exigencies, not top or bottom

Mackintosh: I think the hotspot right now in all of this is the economy. The result is that more people are open to standards and need to share costs. They’re far more open to collaborating and getting to market faster because there are fewer opportunities these days. Standards allow you to commoditize expert knowledge.

Barkley: Even internally at IBM we’ve been trying to share IP among the P series and Z series. We had to enforce internal standards just to be able to share things among our own groups. In terms of sharing costs, IBM years ago had its own internal models, GL1, NBRs, which really gave us a competitive advantage. What we found is that we couldn’t afford to do everything ourselves. We started working on OpenAccess in 2003. We’ve gone from GL1 to Oasis. We’ve gone from internal data models like VIM and CDBA to OpenAccess. We’ve moved away from our internal models and rules to industry standards, which allows us to use some of the vendor simulation and analysis tools we had to develop internally. That actually prevented us from using some of the vendor-provided software, which we had access to for years.

SLD: IBM has always trumpeted its proprietary tools as a competitive advantage. Has it gotten too expensive to continue with that?

Barkley: Yes, and that’s no longer the case. At the end of the day we have to make designers productive. There are some conflicting opinions inside of IBM, but from a high level our design executives never considered this stuff proprietary. Over the last five years we’ve been collaborating with Cadence on the advanced routing and chip optimization. We shared technology, design rules and software IP. There’s not a whole lot we consider proprietary now except product road maps. We are not an EDA organization.

Trivedi: From a user perspective, you can see why sharing makes sense. They are creating a subsystem that needs to prototype outside, so they need to have certain standards and well-defined processes, or they need to import things because they can’t do everything themselves. It’s a matter of what the rationale is for you to share. At one time IBM, HP, Intel and TI did everything themselves. Everyone was an IDM (integrated device manufacturer). There was no need to share. The only thing you knew was how many pins it had and there was a data sheet. That was the interface. Now you’re working at a much more granular level. I can only produce libraries, for example, that everyone else uses. Or I produce this IP block and everyone else uses it. Or I develop the software and I need to know your register definition.

Meredith: The financial model is the same, whether you’re collaborating or sharing. People don’t have the money to do everything themselves. They need to be able to collaborate with specialists in some areas. What that requires is the creation of an ecosystem of specialists working together.

Trivedi: The question is really how much control you want to exert and how much you can exert. The more control you can exert, the less need for standards.

Schulz: That also means you’re self-sufficient, from A to Z.

Meredith: But if there are five gorillas in the industry, that means each job is being done five times and their customers are paying for it to be done five times. It’s an inefficient approach to delivering value.

SLD: Let’s roll this back a little bit. When did big companies like IBM and TI stop developing their own tools and begin using off-the-shelf tools? And why?

Schulz: It’s a function of the maturing of the industry. Back in the 1970s at TI we grew our own crystals. As the industry matures, you specialize. And a bad economy forces those issues. In the past, we weren’t at the level of complexity involved now in moving from concept to packaged device. In the past, the IDMs owned their own fabs. Many of them are fab-lite these days. The business is much more fragmented. We have more integration, more features, and more levels of abstraction.

Mackintosh: The issue is integration. Because of that, there’s much more compartmentalization across the chain. The result is that people can only afford to play in certain areas.

SLD: And they need to extract value from those areas.

Mackintosh: Yes. They need to decide which areas to play in and eventually they have to learn to share.

All of the major EDA vendors and standards groups are pitching modeling as the next level of abstraction for advanced process nodes, but is it working as planned for the chipmakers? System-Level Design caught up with Frans Theeuwen, Department Manager for System Design at NXP Semiconductors Corp. to discuss system-level design and power modeling.

By Ann Steffora Mutschler

SLD: How long has NXP designed at the system-level for production chips?

Frans Theeuwen: It depends on what you call ‘system-level design.’ We have been doing hardware/software co-verification activities for quite some time, which goes back about eight years. Many things we are doing in system-level design are creating virtual prototypes and software development for virtual prototypes. We first did that for production designs about three or four years ago. There was one chip for identification, used in banking applications, and now we are using it more heavily in the area of television chips (consumer electronics). What we are doing now for consumer applications is transaction-level modeling and using that mostly for software development.

SLD: What works and what doesn’t in this area?

Theeuwen: The largest problem for introduction is you need to create all the models. That requires quite an investment if you want to reuse that within the company. In 2007 and 2008, we did quite an investment in creating lots of models for our standard SoCs, so for all the IPs that are there. That’s one thing that is important. The other thing is that most people want to use these virtual prototypes for accurate simulations – for really cycle accurate things. That is what you should not do because then the models are much too complicated and you are too late. If you do transaction-level modeling, you can still do software development, so convincing people they should use one use case for software development and create the models for that, and then do software development for that.

SLD: How long have you been doing power modeling on the transaction level, and are you using tools that you created or outside tools?

Theeuwen: For power modeling on the transaction level, I think we started four years ago. Before we started on the transaction level we did it for power estimation on the gate level. Then, later on, we extended this capability of power modeling at the gate level to go up in abstraction to the transaction level, and there we created our own tools.

SLD: How is the learning curve for the engineers in terms of power modeling?

Theeuwen: Our power models are part of the SystemC TLM models. First, you have to create TLM SystemC models, and then you can put the power models to that. First, you must have all the TLM models available and then you can think about power modeling. We’ve only been working on full-fledged TLM models for a few years, so now we can add the power models to that and the extra work is not that much. Once you have the TLM model, then adding the power view is really not so much work and we rely there on the gate level simulation. As most of the designs are reused – about 90% to 95% of large SoCs is reused – you can have quite accurate power models because you have the RTL so you can simulate. If you have that on the TLM level, you can have quite accurate power modeling on your whole SoC. There are only a few parts for which you do not have implementations and there you need high-level power estimates.

SLD: What are some other issues that need to be addressed at the system level?

Theeuwen: The largest problem with TLM modeling is that interoperability between models is still very difficult. TLM 2.0 is a step in a good direction, so it gives a bit of framework, but if you are modeling in TLM 2.0 there is no guarantee that everything works together.

SLD: What is missing from TLM 2.0?

Theeuwen: One part of being interoperable is being able to connect models to each other with the same buses and pins, and things like that. But also, in a complete system, how scheduling works or how different parts run on a multiprocessor design and how does that change, and how it interfaces to memory. All of those things are still not standardized.

By Pallab Chatterjee

Samsung is changing its product line to reflect its new push for “360 degrees of green,” from components to recycling of those components.

The reason: Environmental concerns are influencing buying patterns in consumer electronics and in the enterprise. Results of recent surveys indicate 29% of the buying decision is based on energy savings, environmentally friendly manufacturing, environmentally certified recycling programs and green components.

These buying decisions will even support premium pricing on products with these features. As a result, the majority of the products at Samsung are being re-engineered from the industrial design to system design, and from features to component design and manufacturing.

The scope of the green program is enormous. All 37 of Samsung’s factories will be ISO 14001 certified, and the company’s Austin semiconductor facility will be EPA Green Power certified because it is powered by wind energy. The company also has re-engineered the following product lines to be 100% compliant with the ENERGY STAR guidelines: HDTVs, monitors, printers, notebooks, dishwashers, and clothes washers. Additionally, Samsung’s LCD and PDP TVs exceed ENERGY STAR 3.0 by at least 15%; its LED edge lit TVs by at least 50%, and its monitors and notebooks are also EPEAT Silver rated or higher.

On the component side the company’s two main green products are DDR3 memories and solid state drives (SSDs). The DDR3 memories also feature a lowered operating voltage of 1.35v rather than the standard 1.8v for DDR2 and 1.5v for DDR3. With the new 45nm process, this results in a 48GB DDR3 RAM, in an enterprise application, being able to operate at 20W as compared with 90W for the current standard of 32GB with DDR2.

The SSDs using the new NAND flash chips result in large power and performance improvements over traditional high performance HDDs. The power savings in the SSDs over the HDDs are 1W vs. 2.5W on active mode, 0.1W vs. 1.5W in idle mode and 0.06W vs. 0.2W in standby mode. With the increased performance available with the SSDs this results in an operating benefit of 6065 IOPS/W vs. 30 IOPS/W and 8.1 IOPS/dollar vs. 0.7 IOPS/dollar. This represents a significant energy use and operating cost benefit for the enterprise market.

On the handset side, Samsung has redesigned its products to include some models based on “bio-plastic,” an electronic-only virtual manual, an ENERGY STAR wall charger, reduced shipping packaging made from recycled material and a low power AMOLED display rather than an LCD. This display has 65% reduced battery consumption while being able to still display 3G and 4G services.

On the display side, there is a design from the traditional RGB displays (in LCD technology) to their Pentile RGBW LED display format. The addition of a white LED to the display options reduced the time for the high power mode where you have all three Red, Green and Blue LEDs are on simultaneously. This shift along, with a change from CCFL to LED backlight and lightpipe based edge LED backlight, has driven the reduction in operating voltage for the displays itself while maintaining or improving the contrast ratio. The new driver electronics also employ interfaces to high speed low power memories so there is no power penalty on the increased scan rate (120 hz and 240hz) display products. The logic power is shifting form 4.0v to 3.0v and further power reduction is in place from the use of active dimming over the display (dimming by region) rather than global dimming of the backlight. This same technology is going into the industrial display market in addition to the consumer tv market.

The overall re-design of the products from the component level, to ROHS compliance for assembly to final industrial design and distribution has impacted the entire cycle and has now added new design criteria all product designs.

Prasad Subramaniam, vice president of design technology at eSilicon, talks with System-Level Design Editor Ed Sperling about the challenges at future process nodes.